arch/arm/boot/dts/stm32f429.dtsi

   1 /*
   2  * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  *     You should have received a copy of the GNU General Public
  20  *     License along with this file; if not, write to the Free
  21  *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  22  *     MA 02110-1301 USA
  23  *
  24  * Or, alternatively,
  25  *
  26  *  b) Permission is hereby granted, free of charge, to any person
  27  *     obtaining a copy of this software and associated documentation
  28  *     files (the "Software"), to deal in the Software without
  29  *     restriction, including without limitation the rights to use,
  30  *     copy, modify, merge, publish, distribute, sublicense, and/or
  31  *     sell copies of the Software, and to permit persons to whom the
  32  *     Software is furnished to do so, subject to the following
  33  *     conditions:
  34  *
  35  *     The above copyright notice and this permission notice shall be
  36  *     included in all copies or substantial portions of the Software.
  37  *
  38  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  39  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  40  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  41  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  42  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  43  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  44  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  45  *     OTHER DEALINGS IN THE SOFTWARE.
  46  */
  47
  48 #include "armv7-m.dtsi"
  49 #include <dt-bindings/clock/stm32fx-clock.h>
  50 #include <dt-bindings/mfd/stm32f4-rcc.h>
  51
  52 / {
  53         #address-cells = <1>;
  54         #size-cells = <1>;
  55
  56         clocks {
  57                 clk_hse: clk-hse {
  58                         #clock-cells = <0>;
  59                         compatible = "fixed-clock";
  60                         clock-frequency = <0>;
  61                 };
  62
  63                 clk_lse: clk-lse {
  64                         #clock-cells = <0>;
  65                         compatible = "fixed-clock";
  66                         clock-frequency = <32768>;
  67                 };
  68
  69                 clk_lsi: clk-lsi {
  70                         #clock-cells = <0>;
  71                         compatible = "fixed-clock";
  72                         clock-frequency = <32000>;
  73                 };
  74
  75                 clk_i2s_ckin: i2s-ckin {
  76                         #clock-cells = <0>;
  77                         compatible = "fixed-clock";
  78                         clock-frequency = <0>;
  79                 };
  80         };
  81
  82         soc {
  83                 romem: nvmem@1fff7800 {
  84                         compatible = "st,stm32f4-otp";
  85                         reg = <0x1fff7800 0x400>;
  86                         #address-cells = <1>;
  87                         #size-cells = <1>;
  88                         ts_cal1: calib@22c {
  89                                 reg = <0x22c 0x2>;
  90                         };
  91                         ts_cal2: calib@22e {
  92                                 reg = <0x22e 0x2>;
  93                         };
  94                 };
  95
  96                 timer2: timer@40000000 {
  97                         compatible = "st,stm32-timer";
  98                         reg = <0x40000000 0x400>;
  99                         interrupts = <28>;
 100                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
 101                         status = "disabled";
 102                 };
 103
 104                 timers2: timers@40000000 {
 105                         #address-cells = <1>;
 106                         #size-cells = <0>;
 107                         compatible = "st,stm32-timers";
 108                         reg = <0x40000000 0x400>;
 109                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
 110                         clock-names = "int";
 111                         status = "disabled";
 112
 113                         pwm {
 114                                 compatible = "st,stm32-pwm";
 115                                 #pwm-cells = <3>;
 116                                 status = "disabled";
 117                         };
 118
 119                         timer@1 {
 120                                 compatible = "st,stm32-timer-trigger";
 121                                 reg = <1>;
 122                                 status = "disabled";
 123                         };
 124                 };
 125
 126                 timer3: timer@40000400 {
 127                         compatible = "st,stm32-timer";
 128                         reg = <0x40000400 0x400>;
 129                         interrupts = <29>;
 130                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
 131                         status = "disabled";
 132                 };
 133
 134                 timers3: timers@40000400 {
 135                         #address-cells = <1>;
 136                         #size-cells = <0>;
 137                         compatible = "st,stm32-timers";
 138                         reg = <0x40000400 0x400>;
 139                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
 140                         clock-names = "int";
 141                         status = "disabled";
 142
 143                         pwm {
 144                                 compatible = "st,stm32-pwm";
 145                                 #pwm-cells = <3>;
 146                                 status = "disabled";
 147                         };
 148
 149                         timer@2 {
 150                                 compatible = "st,stm32-timer-trigger";
 151                                 reg = <2>;
 152                                 status = "disabled";
 153                         };
 154                 };
 155
 156                 timer4: timer@40000800 {
 157                         compatible = "st,stm32-timer";
 158                         reg = <0x40000800 0x400>;
 159                         interrupts = <30>;
 160                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
 161                         status = "disabled";
 162                 };
 163
 164                 timers4: timers@40000800 {
 165                         #address-cells = <1>;
 166                         #size-cells = <0>;
 167                         compatible = "st,stm32-timers";
 168                         reg = <0x40000800 0x400>;
 169                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
 170                         clock-names = "int";
 171                         status = "disabled";
 172
 173                         pwm {
 174                                 compatible = "st,stm32-pwm";
 175                                 #pwm-cells = <3>;
 176                                 status = "disabled";
 177                         };
 178
 179                         timer@3 {
 180                                 compatible = "st,stm32-timer-trigger";
 181                                 reg = <3>;
 182                                 status = "disabled";
 183                         };
 184                 };
 185
 186                 timer5: timer@40000c00 {
 187                         compatible = "st,stm32-timer";
 188                         reg = <0x40000c00 0x400>;
 189                         interrupts = <50>;
 190                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
 191                 };
 192
 193                 timers5: timers@40000c00 {
 194                         #address-cells = <1>;
 195                         #size-cells = <0>;
 196                         compatible = "st,stm32-timers";
 197                         reg = <0x40000C00 0x400>;
 198                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
 199                         clock-names = "int";
 200                         status = "disabled";
 201
 202                         pwm {
 203                                 compatible = "st,stm32-pwm";
 204                                 #pwm-cells = <3>;
 205                                 status = "disabled";
 206                         };
 207
 208                         timer@4 {
 209                                 compatible = "st,stm32-timer-trigger";
 210                                 reg = <4>;
 211                                 status = "disabled";
 212                         };
 213                 };
 214
 215                 timer6: timer@40001000 {
 216                         compatible = "st,stm32-timer";
 217                         reg = <0x40001000 0x400>;
 218                         interrupts = <54>;
 219                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
 220                         status = "disabled";
 221                 };
 222
 223                 timers6: timers@40001000 {
 224                         #address-cells = <1>;
 225                         #size-cells = <0>;
 226                         compatible = "st,stm32-timers";
 227                         reg = <0x40001000 0x400>;
 228                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
 229                         clock-names = "int";
 230                         status = "disabled";
 231
 232                         timer@5 {
 233                                 compatible = "st,stm32-timer-trigger";
 234                                 reg = <5>;
 235                                 status = "disabled";
 236                         };
 237                 };
 238
 239                 timer7: timer@40001400 {
 240                         compatible = "st,stm32-timer";
 241                         reg = <0x40001400 0x400>;
 242                         interrupts = <55>;
 243                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
 244                         status = "disabled";
 245                 };
 246
 247                 timers7: timers@40001400 {
 248                         #address-cells = <1>;
 249                         #size-cells = <0>;
 250                         compatible = "st,stm32-timers";
 251                         reg = <0x40001400 0x400>;
 252                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
 253                         clock-names = "int";
 254                         status = "disabled";
 255
 256                         timer@6 {
 257                                 compatible = "st,stm32-timer-trigger";
 258                                 reg = <6>;
 259                                 status = "disabled";
 260                         };
 261                 };
 262
 263                 timers12: timers@40001800 {
 264                         #address-cells = <1>;
 265                         #size-cells = <0>;
 266                         compatible = "st,stm32-timers";
 267                         reg = <0x40001800 0x400>;
 268                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>;
 269                         clock-names = "int";
 270                         status = "disabled";
 271
 272                         pwm {
 273                                 compatible = "st,stm32-pwm";
 274                                 #pwm-cells = <3>;
 275                                 status = "disabled";
 276                         };
 277
 278                         timer@11 {
 279                                 compatible = "st,stm32-timer-trigger";
 280                                 reg = <11>;
 281                                 status = "disabled";
 282                         };
 283                 };
 284
 285                 timers13: timers@40001c00 {
 286                         compatible = "st,stm32-timers";
 287                         reg = <0x40001C00 0x400>;
 288                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
 289                         clock-names = "int";
 290                         status = "disabled";
 291
 292                         pwm {
 293                                 compatible = "st,stm32-pwm";
 294                                 #pwm-cells = <3>;
 295                                 status = "disabled";
 296                         };
 297                 };
 298
 299                 timers14: timers@40002000 {
 300                         compatible = "st,stm32-timers";
 301                         reg = <0x40002000 0x400>;
 302                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
 303                         clock-names = "int";
 304                         status = "disabled";
 305
 306                         pwm {
 307                                 compatible = "st,stm32-pwm";
 308                                 #pwm-cells = <3>;
 309                                 status = "disabled";
 310                         };
 311                 };
 312
 313                 rtc: rtc@40002800 {
 314                         compatible = "st,stm32-rtc";
 315                         reg = <0x40002800 0x400>;
 316                         clocks = <&rcc 1 CLK_RTC>;
 317                         clock-names = "ck_rtc";
 318                         assigned-clocks = <&rcc 1 CLK_RTC>;
 319                         assigned-clock-parents = <&rcc 1 CLK_LSE>;
 320                         interrupt-parent = <&exti>;
 321                         interrupts = <17 1>;
 322                         interrupt-names = "alarm";
 323                         st,syscfg = <&pwrcfg 0x00 0x100>;
 324                         status = "disabled";
 325                 };
 326
 327                 iwdg: watchdog@40003000 {
 328                         compatible = "st,stm32-iwdg";
 329                         reg = <0x40003000 0x400>;
 330                         clocks = <&clk_lsi>;
 331                         clock-names = "lsi";
 332                         status = "disabled";
 333                 };
 334
 335                 spi2: spi@40003800 {
 336                         #address-cells = <1>;
 337                         #size-cells = <0>;
 338                         compatible = "st,stm32f4-spi";
 339                         reg = <0x40003800 0x400>;
 340                         interrupts = <36>;
 341                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI2)>;
 342                         status = "disabled";
 343                 };
 344
 345                 spi3: spi@40003c00 {
 346                         #address-cells = <1>;
 347                         #size-cells = <0>;
 348                         compatible = "st,stm32f4-spi";
 349                         reg = <0x40003c00 0x400>;
 350                         interrupts = <51>;
 351                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI3)>;
 352                         status = "disabled";
 353                 };
 354
 355                 usart2: serial@40004400 {
 356                         compatible = "st,stm32-uart";
 357                         reg = <0x40004400 0x400>;
 358                         interrupts = <38>;
 359                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART2)>;
 360                         status = "disabled";
 361                 };
 362
 363                 usart3: serial@40004800 {
 364                         compatible = "st,stm32-uart";
 365                         reg = <0x40004800 0x400>;
 366                         interrupts = <39>;
 367                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART3)>;
 368                         status = "disabled";
 369                         dmas = <&dma1 1 4 0x400 0x0>,
 370                                <&dma1 3 4 0x400 0x0>;
 371                         dma-names = "rx", "tx";
 372                 };
 373
 374                 usart4: serial@40004c00 {
 375                         compatible = "st,stm32-uart";
 376                         reg = <0x40004c00 0x400>;
 377                         interrupts = <52>;
 378                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART4)>;
 379                         status = "disabled";
 380                 };
 381
 382                 usart5: serial@40005000 {
 383                         compatible = "st,stm32-uart";
 384                         reg = <0x40005000 0x400>;
 385                         interrupts = <53>;
 386                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART5)>;
 387                         status = "disabled";
 388                 };
 389
 390                 i2c1: i2c@40005400 {
 391                         compatible = "st,stm32f4-i2c";
 392                         reg = <0x40005400 0x400>;
 393                         interrupts = <31>,
 394                                      <32>;
 395                         resets = <&rcc STM32F4_APB1_RESET(I2C1)>;
 396                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>;
 397                         #address-cells = <1>;
 398                         #size-cells = <0>;
 399                         status = "disabled";
 400                 };
 401
 402                 dac: dac@40007400 {
 403                         compatible = "st,stm32f4-dac-core";
 404                         reg = <0x40007400 0x400>;
 405                         resets = <&rcc STM32F4_APB1_RESET(DAC)>;
 406                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(DAC)>;
 407                         clock-names = "pclk";
 408                         #address-cells = <1>;
 409                         #size-cells = <0>;
 410                         status = "disabled";
 411
 412                         dac1: dac@1 {
 413                                 compatible = "st,stm32-dac";
 414                                 #io-channels-cells = <1>;
 415                                 reg = <1>;
 416                                 status = "disabled";
 417                         };
 418
 419                         dac2: dac@2 {
 420                                 compatible = "st,stm32-dac";
 421                                 #io-channels-cells = <1>;
 422                                 reg = <2>;
 423                                 status = "disabled";
 424                         };
 425                 };
 426
 427                 usart7: serial@40007800 {
 428                         compatible = "st,stm32-uart";
 429                         reg = <0x40007800 0x400>;
 430                         interrupts = <82>;
 431                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART7)>;
 432                         status = "disabled";
 433                 };
 434
 435                 usart8: serial@40007c00 {
 436                         compatible = "st,stm32-uart";
 437                         reg = <0x40007c00 0x400>;
 438                         interrupts = <83>;
 439                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART8)>;
 440                         status = "disabled";
 441                 };
 442
 443                 timers1: timers@40010000 {
 444                         #address-cells = <1>;
 445                         #size-cells = <0>;
 446                         compatible = "st,stm32-timers";
 447                         reg = <0x40010000 0x400>;
 448                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM1)>;
 449                         clock-names = "int";
 450                         status = "disabled";
 451
 452                         pwm {
 453                                 compatible = "st,stm32-pwm";
 454                                 #pwm-cells = <3>;
 455                                 status = "disabled";
 456                         };
 457
 458                         timer@0 {
 459                                 compatible = "st,stm32-timer-trigger";
 460                                 reg = <0>;
 461                                 status = "disabled";
 462                         };
 463                 };
 464
 465                 timers8: timers@40010400 {
 466                         #address-cells = <1>;
 467                         #size-cells = <0>;
 468                         compatible = "st,stm32-timers";
 469                         reg = <0x40010400 0x400>;
 470                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM8)>;
 471                         clock-names = "int";
 472                         status = "disabled";
 473
 474                         pwm {
 475                                 compatible = "st,stm32-pwm";
 476                                 #pwm-cells = <3>;
 477                                 status = "disabled";
 478                         };
 479
 480                         timer@7 {
 481                                 compatible = "st,stm32-timer-trigger";
 482                                 reg = <7>;
 483                                 status = "disabled";
 484                         };
 485                 };
 486
 487                 usart1: serial@40011000 {
 488                         compatible = "st,stm32-uart";
 489                         reg = <0x40011000 0x400>;
 490                         interrupts = <37>;
 491                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART1)>;
 492                         status = "disabled";
 493                         dmas = <&dma2 2 4 0x400 0x0>,
 494                                <&dma2 7 4 0x400 0x0>;
 495                         dma-names = "rx", "tx";
 496                 };
 497
 498                 usart6: serial@40011400 {
 499                         compatible = "st,stm32-uart";
 500                         reg = <0x40011400 0x400>;
 501                         interrupts = <71>;
 502                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART6)>;
 503                         status = "disabled";
 504                 };
 505
 506                 adc: adc@40012000 {
 507                         compatible = "st,stm32f4-adc-core";
 508                         reg = <0x40012000 0x400>;
 509                         interrupts = <18>;
 510                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
 511                         clock-names = "adc";
 512                         interrupt-controller;
 513                         #interrupt-cells = <1>;
 514                         #address-cells = <1>;
 515                         #size-cells = <0>;
 516                         status = "disabled";
 517
 518                         adc1: adc@0 {
 519                                 compatible = "st,stm32f4-adc";
 520                                 #io-channel-cells = <1>;
 521                                 reg = <0x0>;
 522                                 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
 523                                 interrupt-parent = <&adc>;
 524                                 interrupts = <0>;
 525                                 dmas = <&dma2 0 0 0x400 0x0>;
 526                                 dma-names = "rx";
 527                                 status = "disabled";
 528                         };
 529
 530                         adc2: adc@100 {
 531                                 compatible = "st,stm32f4-adc";
 532                                 #io-channel-cells = <1>;
 533                                 reg = <0x100>;
 534                                 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC2)>;
 535                                 interrupt-parent = <&adc>;
 536                                 interrupts = <1>;
 537                                 dmas = <&dma2 3 1 0x400 0x0>;
 538                                 dma-names = "rx";
 539                                 status = "disabled";
 540                         };
 541
 542                         adc3: adc@200 {
 543                                 compatible = "st,stm32f4-adc";
 544                                 #io-channel-cells = <1>;
 545                                 reg = <0x200>;
 546                                 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC3)>;
 547                                 interrupt-parent = <&adc>;
 548                                 interrupts = <2>;
 549                                 dmas = <&dma2 1 2 0x400 0x0>;
 550                                 dma-names = "rx";
 551                                 status = "disabled";
 552                         };
 553                 };
 554
 555                 sdio: sdio@40012c00 {
 556                         compatible = "arm,pl180", "arm,primecell";
 557                         arm,primecell-periphid = <0x00880180>;
 558                         reg = <0x40012c00 0x400>;
 559                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(SDIO)>;
 560                         clock-names = "apb_pclk";
 561                         interrupts = <49>;
 562                         max-frequency = <48000000>;
 563                         status = "disabled";
 564                 };
 565
 566                 spi1: spi@40013000 {
 567                         #address-cells = <1>;
 568                         #size-cells = <0>;
 569                         compatible = "st,stm32f4-spi";
 570                         reg = <0x40013000 0x400>;
 571                         interrupts = <35>;
 572                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI1)>;
 573                         status = "disabled";
 574                 };
 575
 576                 spi4: spi@40013400 {
 577                         #address-cells = <1>;
 578                         #size-cells = <0>;
 579                         compatible = "st,stm32f4-spi";
 580                         reg = <0x40013400 0x400>;
 581                         interrupts = <84>;
 582                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI4)>;
 583                         status = "disabled";
 584                 };
 585
 586                 syscfg: system-config@40013800 {
 587                         compatible = "syscon";
 588                         reg = <0x40013800 0x400>;
 589                 };
 590
 591                 exti: interrupt-controller@40013c00 {
 592                         compatible = "st,stm32-exti";
 593                         interrupt-controller;
 594                         #interrupt-cells = <2>;
 595                         reg = <0x40013C00 0x400>;
 596                         interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
 597                 };
 598
 599                 timers9: timers@40014000 {
 600                         #address-cells = <1>;
 601                         #size-cells = <0>;
 602                         compatible = "st,stm32-timers";
 603                         reg = <0x40014000 0x400>;
 604                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM9)>;
 605                         clock-names = "int";
 606                         status = "disabled";
 607
 608                         pwm {
 609                                 compatible = "st,stm32-pwm";
 610                                 #pwm-cells = <3>;
 611                                 status = "disabled";
 612                         };
 613
 614                         timer@8 {
 615                                 compatible = "st,stm32-timer-trigger";
 616                                 reg = <8>;
 617                                 status = "disabled";
 618                         };
 619                 };
 620
 621                 timers10: timers@40014400 {
 622                         compatible = "st,stm32-timers";
 623                         reg = <0x40014400 0x400>;
 624                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>;
 625                         clock-names = "int";
 626                         status = "disabled";
 627
 628                         pwm {
 629                                 compatible = "st,stm32-pwm";
 630                                 #pwm-cells = <3>;
 631                                 status = "disabled";
 632                         };
 633                 };
 634
 635                 timers11: timers@40014800 {
 636                         compatible = "st,stm32-timers";
 637                         reg = <0x40014800 0x400>;
 638                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>;
 639                         clock-names = "int";
 640                         status = "disabled";
 641
 642                         pwm {
 643                                 compatible = "st,stm32-pwm";
 644                                 #pwm-cells = <3>;
 645                                 status = "disabled";
 646                         };
 647                 };
 648
 649                 spi5: spi@40015000 {
 650                         #address-cells = <1>;
 651                         #size-cells = <0>;
 652                         compatible = "st,stm32f4-spi";
 653                         reg = <0x40015000 0x400>;
 654                         interrupts = <85>;
 655                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI5)>;
 656                         status = "disabled";
 657                 };
 658
 659                 spi6: spi@40015400 {
 660                         #address-cells = <1>;
 661                         #size-cells = <0>;
 662                         compatible = "st,stm32f4-spi";
 663                         reg = <0x40015400 0x400>;
 664                         interrupts = <86>;
 665                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI6)>;
 666                         status = "disabled";
 667                 };
 668
 669                 pwrcfg: power-config@40007000 {
 670                         compatible = "syscon";
 671                         reg = <0x40007000 0x400>;
 672                 };
 673
 674                 ltdc: display-controller@40016800 {
 675                         compatible = "st,stm32-ltdc";
 676                         reg = <0x40016800 0x200>;
 677                         interrupts = <88>, <89>;
 678                         resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
 679                         clocks = <&rcc 1 CLK_LCD>;
 680                         clock-names = "lcd";
 681                         status = "disabled";
 682                 };
 683
 684                 crc: crc@40023000 {
 685                         compatible = "st,stm32f4-crc";
 686                         reg = <0x40023000 0x400>;
 687                         clocks = <&rcc 0 STM32F4_AHB1_CLOCK(CRC)>;
 688                         status = "disabled";
 689                 };
 690
 691                 rcc: rcc@40023800 {
 692                         #reset-cells = <1>;
 693                         #clock-cells = <2>;
 694                         compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
 695                         reg = <0x40023800 0x400>;
 696                         clocks = <&clk_hse>, <&clk_i2s_ckin>;
 697                         st,syscfg = <&pwrcfg>;
 698                         assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
 699                         assigned-clock-rates = <1000000>;
 700                 };
 701
 702                 dma1: dma-controller@40026000 {
 703                         compatible = "st,stm32-dma";
 704                         reg = <0x40026000 0x400>;
 705                         interrupts = <11>,
 706                                      <12>,
 707                                      <13>,
 708                                      <14>,
 709                                      <15>,
 710                                      <16>,
 711                                      <17>,
 712                                      <47>;
 713                         clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA1)>;
 714                         #dma-cells = <4>;
 715                 };
 716
 717                 dma2: dma-controller@40026400 {
 718                         compatible = "st,stm32-dma";
 719                         reg = <0x40026400 0x400>;
 720                         interrupts = <56>,
 721                                      <57>,
 722                                      <58>,
 723                                      <59>,
 724                                      <60>,
 725                                      <68>,
 726                                      <69>,
 727                                      <70>;
 728                         clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2)>;
 729                         #dma-cells = <4>;
 730                         st,mem2mem;
 731                 };
 732
 733                 mac: ethernet@40028000 {
 734                         compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
 735                         reg = <0x40028000 0x8000>;
 736                         reg-names = "stmmaceth";
 737                         interrupts = <61>;
 738                         interrupt-names = "macirq";
 739                         clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
 740                         clocks = <&rcc 0 STM32F4_AHB1_CLOCK(ETHMAC)>,
 741                                         <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACTX)>,
 742                                         <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACRX)>;
 743                         st,syscon = <&syscfg 0x4>;
 744                         snps,pbl = <8>;
 745                         snps,mixed-burst;
 746                         status = "disabled";
 747                 };
 748
 749                 usbotg_hs: usb@40040000 {
 750                         compatible = "snps,dwc2";
 751                         reg = <0x40040000 0x40000>;
 752                         interrupts = <77>;
 753                         clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHS)>;
 754                         clock-names = "otg";
 755                         status = "disabled";
 756                 };
 757
 758                 usbotg_fs: usb@50000000 {
 759                         compatible = "st,stm32f4x9-fsotg";
 760                         reg = <0x50000000 0x40000>;
 761                         interrupts = <67>;
 762                         clocks = <&rcc 0 39>;
 763                         clock-names = "otg";
 764                         status = "disabled";
 765                 };
 766
 767                 dcmi: dcmi@50050000 {
 768                         compatible = "st,stm32-dcmi";
 769                         reg = <0x50050000 0x400>;
 770                         interrupts = <78>;
 771                         resets = <&rcc STM32F4_AHB2_RESET(DCMI)>;
 772                         clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>;
 773                         clock-names = "mclk";
 774                         pinctrl-names = "default";
 775                         pinctrl-0 = <&dcmi_pins>;
 776                         dmas = <&dma2 1 1 0x414 0x3>;
 777                         dma-names = "tx";
 778                         status = "disabled";
 779                 };
 780
 781                 rng: rng@50060800 {
 782                         compatible = "st,stm32-rng";
 783                         reg = <0x50060800 0x400>;
 784                         interrupts = <80>;
 785                         clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>;
 786
 787                 };
 788         };
 789 };
 790
 791 &systick {
 792         clocks = <&rcc 1 SYSTICK>;
 793         status = "okay";
 794 };