2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public
20 * License along with this file; if not, write to the Free
21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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48 #include "skeleton.dtsi"
49 #include "armv7-m.dtsi"
50 #include <dt-bindings/pinctrl/stm32f429-pinfunc.h>
56 compatible = "fixed-clock";
57 clock-frequency = <0>;
62 dma-ranges = <0xc0000000 0x0 0x10000000>;
64 timer2: timer@40000000 {
65 compatible = "st,stm32-timer";
66 reg = <0x40000000 0x400>;
68 clocks = <&rcc 0 128>;
72 timer3: timer@40000400 {
73 compatible = "st,stm32-timer";
74 reg = <0x40000400 0x400>;
76 clocks = <&rcc 0 129>;
80 timer4: timer@40000800 {
81 compatible = "st,stm32-timer";
82 reg = <0x40000800 0x400>;
84 clocks = <&rcc 0 130>;
88 timer5: timer@40000c00 {
89 compatible = "st,stm32-timer";
90 reg = <0x40000c00 0x400>;
92 clocks = <&rcc 0 131>;
95 timer6: timer@40001000 {
96 compatible = "st,stm32-timer";
97 reg = <0x40001000 0x400>;
99 clocks = <&rcc 0 132>;
103 timer7: timer@40001400 {
104 compatible = "st,stm32-timer";
105 reg = <0x40001400 0x400>;
107 clocks = <&rcc 0 133>;
111 usart2: serial@40004400 {
112 compatible = "st,stm32-usart", "st,stm32-uart";
113 reg = <0x40004400 0x400>;
115 clocks = <&rcc 0 145>;
119 usart3: serial@40004800 {
120 compatible = "st,stm32-usart", "st,stm32-uart";
121 reg = <0x40004800 0x400>;
123 clocks = <&rcc 0 146>;
127 usart4: serial@40004c00 {
128 compatible = "st,stm32-uart";
129 reg = <0x40004c00 0x400>;
131 clocks = <&rcc 0 147>;
135 usart5: serial@40005000 {
136 compatible = "st,stm32-uart";
137 reg = <0x40005000 0x400>;
139 clocks = <&rcc 0 148>;
143 usart7: serial@40007800 {
144 compatible = "st,stm32-usart", "st,stm32-uart";
145 reg = <0x40007800 0x400>;
147 clocks = <&rcc 0 158>;
151 usart8: serial@40007c00 {
152 compatible = "st,stm32-usart", "st,stm32-uart";
153 reg = <0x40007c00 0x400>;
155 clocks = <&rcc 0 159>;
159 usart1: serial@40011000 {
160 compatible = "st,stm32-usart", "st,stm32-uart";
161 reg = <0x40011000 0x400>;
163 clocks = <&rcc 0 164>;
167 usart6: serial@40011400 {
168 compatible = "st,stm32-usart", "st,stm32-uart";
169 reg = <0x40011400 0x400>;
171 clocks = <&rcc 0 165>;
175 syscfg: system-config@40013800 {
176 compatible = "syscon";
177 reg = <0x40013800 0x400>;
180 exti: interrupt-controller@40013c00 {
181 compatible = "st,stm32-exti";
182 interrupt-controller;
183 #interrupt-cells = <2>;
184 reg = <0x40013C00 0x400>;
185 interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
189 #address-cells = <1>;
191 compatible = "st,stm32f429-pinctrl";
192 ranges = <0 0x40020000 0x3000>;
195 gpioa: gpio@40020000 {
200 st,bank-name = "GPIOA";
203 gpiob: gpio@40020400 {
208 st,bank-name = "GPIOB";
211 gpioc: gpio@40020800 {
216 st,bank-name = "GPIOC";
219 gpiod: gpio@40020c00 {
224 st,bank-name = "GPIOD";
227 gpioe: gpio@40021000 {
230 reg = <0x1000 0x400>;
232 st,bank-name = "GPIOE";
235 gpiof: gpio@40021400 {
238 reg = <0x1400 0x400>;
240 st,bank-name = "GPIOF";
243 gpiog: gpio@40021800 {
246 reg = <0x1800 0x400>;
248 st,bank-name = "GPIOG";
251 gpioh: gpio@40021c00 {
254 reg = <0x1c00 0x400>;
256 st,bank-name = "GPIOH";
259 gpioi: gpio@40022000 {
262 reg = <0x2000 0x400>;
264 st,bank-name = "GPIOI";
267 gpioj: gpio@40022400 {
270 reg = <0x2400 0x400>;
272 st,bank-name = "GPIOJ";
275 gpiok: gpio@40022800 {
278 reg = <0x2800 0x400>;
279 clocks = <&rcc 0 10>;
280 st,bank-name = "GPIOK";
283 usart1_pins_a: usart1@0 {
285 pinmux = <STM32F429_PA9_FUNC_USART1_TX>;
291 pinmux = <STM32F429_PA10_FUNC_USART1_RX>;
296 usbotg_hs_pins_a: usbotg_hs@0 {
298 pinmux = <STM32F429_PH4_FUNC_OTG_HS_ULPI_NXT>,
299 <STM32F429_PI11_FUNC_OTG_HS_ULPI_DIR>,
300 <STM32F429_PC0_FUNC_OTG_HS_ULPI_STP>,
301 <STM32F429_PA5_FUNC_OTG_HS_ULPI_CK>,
302 <STM32F429_PA3_FUNC_OTG_HS_ULPI_D0>,
303 <STM32F429_PB0_FUNC_OTG_HS_ULPI_D1>,
304 <STM32F429_PB1_FUNC_OTG_HS_ULPI_D2>,
305 <STM32F429_PB10_FUNC_OTG_HS_ULPI_D3>,
306 <STM32F429_PB11_FUNC_OTG_HS_ULPI_D4>,
307 <STM32F429_PB12_FUNC_OTG_HS_ULPI_D5>,
308 <STM32F429_PB13_FUNC_OTG_HS_ULPI_D6>,
309 <STM32F429_PB5_FUNC_OTG_HS_ULPI_D7>;
316 ethernet0_mii: mii@0 {
318 pinmux = <STM32F429_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>,
319 <STM32F429_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>,
320 <STM32F429_PC2_FUNC_ETH_MII_TXD2>,
321 <STM32F429_PB8_FUNC_ETH_MII_TXD3>,
322 <STM32F429_PC3_FUNC_ETH_MII_TX_CLK>,
323 <STM32F429_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>,
324 <STM32F429_PA2_FUNC_ETH_MDIO>,
325 <STM32F429_PC1_FUNC_ETH_MDC>,
326 <STM32F429_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>,
327 <STM32F429_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>,
328 <STM32F429_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>,
329 <STM32F429_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>,
330 <STM32F429_PH6_FUNC_ETH_MII_RXD2>,
331 <STM32F429_PH7_FUNC_ETH_MII_RXD3>;
340 compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
341 reg = <0x40023800 0x400>;
345 dma1: dma-controller@40026000 {
346 compatible = "st,stm32-dma";
347 reg = <0x40026000 0x400>;
356 clocks = <&rcc 0 21>;
360 dma2: dma-controller@40026400 {
361 compatible = "st,stm32-dma";
362 reg = <0x40026400 0x400>;
371 clocks = <&rcc 0 22>;
376 ethernet0: dwmac@40028000 {
377 compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
378 reg = <0x40028000 0x8000>;
379 reg-names = "stmmaceth";
380 interrupts = <61>, <62>;
381 interrupt-names = "macirq", "eth_wake_irq";
382 clock-names = "stmmaceth", "tx-clk", "rx-clk";
383 clocks = <&rcc 0 25>, <&rcc 0 26>, <&rcc 0 27>;
384 st,syscon = <&syscfg 0x4>;
391 usbotg_hs: usb@40040000 {
392 compatible = "snps,dwc2";
394 reg = <0x40040000 0x40000>;
396 clocks = <&rcc 0 29>;
402 compatible = "st,stm32-rng";
403 reg = <0x50060800 0x400>;
405 clocks = <&rcc 0 38>;