arch/arm/boot/dts/stih410.dtsi

   1 /*
   2  * Copyright (C) 2014 STMicroelectronics Limited.
   3  * Author: Peter Griffin <peter.griffin@linaro.org>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * publishhed by the Free Software Foundation.
   8  */
   9 #include "stih410-clock.dtsi"
  10 #include "stih407-family.dtsi"
  11 #include "stih410-pinctrl.dtsi"
  12 #include <dt-bindings/gpio/gpio.h>
  13 / {
  14         aliases {
  15                 bdisp0 = &bdisp0;
  16         };
  17
  18         soc {
  19                 usb2_picophy1: phy2@0 {
  20                         compatible = "st,stih407-usb2-phy";
  21                         reg = <0 0>;
  22                         #phy-cells = <0>;
  23                         st,syscfg = <&syscfg_core 0xf8 0xf4>;
  24                         resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
  25                                  <&picophyreset STIH407_PICOPHY0_RESET>;
  26                         reset-names = "global", "port";
  27
  28                         status = "disabled";
  29                 };
  30
  31                 usb2_picophy2: phy3@0 {
  32                         compatible = "st,stih407-usb2-phy";
  33                         reg = <0 0>;
  34                         #phy-cells = <0>;
  35                         st,syscfg = <&syscfg_core 0xfc 0xf4>;
  36                         resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
  37                                  <&picophyreset STIH407_PICOPHY1_RESET>;
  38                         reset-names = "global", "port";
  39
  40                         status = "disabled";
  41                 };
  42
  43                 ohci0: usb@9a03c00 {
  44                         compatible = "st,st-ohci-300x";
  45                         reg = <0x9a03c00 0x100>;
  46                         interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
  47                         clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
  48                                  <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
  49                         resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
  50                                  <&softreset STIH407_USB2_PORT0_SOFTRESET>;
  51                         reset-names = "power", "softreset";
  52                         phys = <&usb2_picophy1>;
  53                         phy-names = "usb";
  54
  55                         status = "disabled";
  56                 };
  57
  58                 ehci0: usb@9a03e00 {
  59                         compatible = "st,st-ehci-300x";
  60                         reg = <0x9a03e00 0x100>;
  61                         interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
  62                         pinctrl-names = "default";
  63                         pinctrl-0 = <&pinctrl_usb0>;
  64                         clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
  65                                  <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
  66                         resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
  67                                  <&softreset STIH407_USB2_PORT0_SOFTRESET>;
  68                         reset-names = "power", "softreset";
  69                         phys = <&usb2_picophy1>;
  70                         phy-names = "usb";
  71
  72                         status = "disabled";
  73                 };
  74
  75                 ohci1: usb@9a83c00 {
  76                         compatible = "st,st-ohci-300x";
  77                         reg = <0x9a83c00 0x100>;
  78                         interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
  79                         clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
  80                                  <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
  81                         resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
  82                                  <&softreset STIH407_USB2_PORT1_SOFTRESET>;
  83                         reset-names = "power", "softreset";
  84                         phys = <&usb2_picophy2>;
  85                         phy-names = "usb";
  86
  87                         status = "disabled";
  88                 };
  89
  90                 ehci1: usb@9a83e00 {
  91                         compatible = "st,st-ehci-300x";
  92                         reg = <0x9a83e00 0x100>;
  93                         interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
  94                         pinctrl-names = "default";
  95                         pinctrl-0 = <&pinctrl_usb1>;
  96                         clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
  97                                  <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
  98                         resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
  99                                  <&softreset STIH407_USB2_PORT1_SOFTRESET>;
 100                         reset-names = "power", "softreset";
 101                         phys = <&usb2_picophy2>;
 102                         phy-names = "usb";
 103
 104                         status = "disabled";
 105                 };
 106
 107                 sti-display-subsystem@0 {
 108                         compatible = "st,sti-display-subsystem";
 109                         #address-cells = <1>;
 110                         #size-cells = <1>;
 111
 112                         reg = <0 0>;
 113                         assigned-clocks = <&clk_s_d2_quadfs 0>,
 114                                           <&clk_s_d2_quadfs 1>,
 115                                           <&clk_s_c0_pll1 0>,
 116                                           <&clk_s_c0_flexgen CLK_COMPO_DVP>,
 117                                           <&clk_s_c0_flexgen CLK_MAIN_DISP>,
 118                                           <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
 119                                           <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
 120                                           <&clk_s_d2_flexgen CLK_PIX_GDP1>,
 121                                           <&clk_s_d2_flexgen CLK_PIX_GDP2>,
 122                                           <&clk_s_d2_flexgen CLK_PIX_GDP3>,
 123                                           <&clk_s_d2_flexgen CLK_PIX_GDP4>;
 124
 125                         assigned-clock-parents = <0>,
 126                                                  <0>,
 127                                                  <0>,
 128                                                  <&clk_s_c0_pll1 0>,
 129                                                  <&clk_s_c0_pll1 0>,
 130                                                  <&clk_s_d2_quadfs 0>,
 131                                                  <&clk_s_d2_quadfs 1>,
 132                                                  <&clk_s_d2_quadfs 0>,
 133                                                  <&clk_s_d2_quadfs 0>,
 134                                                  <&clk_s_d2_quadfs 0>,
 135                                                  <&clk_s_d2_quadfs 0>;
 136
 137                         assigned-clock-rates = <297000000>,
 138                                                <297000000>,
 139                                                <0>,
 140                                                <400000000>,
 141                                                <400000000>;
 142
 143                         ranges;
 144
 145                         sti-compositor@9d11000 {
 146                                 compatible = "st,stih407-compositor";
 147                                 reg = <0x9d11000 0x1000>;
 148
 149                                 clock-names = "compo_main",
 150                                               "compo_aux",
 151                                               "pix_main",
 152                                               "pix_aux",
 153                                               "pix_gdp1",
 154                                               "pix_gdp2",
 155                                               "pix_gdp3",
 156                                               "pix_gdp4",
 157                                               "main_parent",
 158                                               "aux_parent";
 159
 160                                 clocks = <&clk_s_c0_flexgen CLK_COMPO_DVP>,
 161                                          <&clk_s_c0_flexgen CLK_COMPO_DVP>,
 162                                          <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
 163                                          <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
 164                                          <&clk_s_d2_flexgen CLK_PIX_GDP1>,
 165                                          <&clk_s_d2_flexgen CLK_PIX_GDP2>,
 166                                          <&clk_s_d2_flexgen CLK_PIX_GDP3>,
 167                                          <&clk_s_d2_flexgen CLK_PIX_GDP4>,
 168                                          <&clk_s_d2_quadfs 0>,
 169                                          <&clk_s_d2_quadfs 1>;
 170
 171                                 reset-names = "compo-main", "compo-aux";
 172                                 resets = <&softreset STIH407_COMPO_SOFTRESET>,
 173                                          <&softreset STIH407_COMPO_SOFTRESET>;
 174                                 st,vtg = <&vtg_main>, <&vtg_aux>;
 175                         };
 176
 177                         sti-tvout@8d08000 {
 178                                 compatible = "st,stih407-tvout";
 179                                 reg = <0x8d08000 0x1000>;
 180                                 reg-names = "tvout-reg";
 181                                 reset-names = "tvout";
 182                                 resets = <&softreset STIH407_HDTVOUT_SOFTRESET>;
 183                                 #address-cells = <1>;
 184                                 #size-cells = <1>;
 185                                 assigned-clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
 186                                                   <&clk_s_d2_flexgen CLK_TMDS_HDMI>,
 187                                                   <&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
 188                                                   <&clk_s_d0_flexgen CLK_PCM_0>,
 189                                                   <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
 190                                                   <&clk_s_d2_flexgen CLK_HDDAC>;
 191
 192                                 assigned-clock-parents = <&clk_s_d2_quadfs 0>,
 193                                                          <&clk_tmdsout_hdmi>,
 194                                                          <&clk_s_d2_quadfs 0>,
 195                                                          <&clk_s_d0_quadfs 0>,
 196                                                          <&clk_s_d2_quadfs 0>,
 197                                                          <&clk_s_d2_quadfs 0>;
 198                         };
 199
 200                         sti_hdmi: sti-hdmi@8d04000 {
 201                                 compatible = "st,stih407-hdmi";
 202                                 reg = <0x8d04000 0x1000>;
 203                                 reg-names = "hdmi-reg";
 204                                 #sound-dai-cells = <0>;
 205                                 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 206                                 interrupt-names = "irq";
 207                                 clock-names = "pix",
 208                                               "tmds",
 209                                               "phy",
 210                                               "audio",
 211                                               "main_parent",
 212                                               "aux_parent";
 213
 214                                 clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
 215                                          <&clk_s_d2_flexgen CLK_TMDS_HDMI>,
 216                                          <&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
 217                                          <&clk_s_d0_flexgen CLK_PCM_0>,
 218                                          <&clk_s_d2_quadfs 0>,
 219                                          <&clk_s_d2_quadfs 1>;
 220
 221                                 hdmi,hpd-gpio = <&pio5 3 GPIO_ACTIVE_LOW>;
 222                                 reset-names = "hdmi";
 223                                 resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>;
 224                                 ddc = <&hdmiddc>;
 225                         };
 226
 227                         sti-hda@8d02000 {
 228                                 compatible = "st,stih407-hda";
 229                                 status = "disabled";
 230                                 reg = <0x8d02000 0x400>, <0x92b0120 0x4>;
 231                                 reg-names = "hda-reg", "video-dacs-ctrl";
 232                                 clock-names = "pix",
 233                                               "hddac",
 234                                               "main_parent",
 235                                               "aux_parent";
 236                                 clocks = <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
 237                                          <&clk_s_d2_flexgen CLK_HDDAC>,
 238                                          <&clk_s_d2_quadfs 0>,
 239                                          <&clk_s_d2_quadfs 1>;
 240                         };
 241
 242                         sti-hqvdp@9c00000 {
 243                                 compatible = "st,stih407-hqvdp";
 244                                 reg = <0x9C00000 0x100000>;
 245                                 clock-names = "hqvdp", "pix_main";
 246                                 clocks = <&clk_s_c0_flexgen CLK_MAIN_DISP>,
 247                                          <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>;
 248                                 reset-names = "hqvdp";
 249                                 resets = <&softreset STIH407_HDQVDP_SOFTRESET>;
 250                                 st,vtg = <&vtg_main>;
 251                         };
 252                 };
 253
 254                 bdisp0:bdisp@9f10000 {
 255                         compatible = "st,stih407-bdisp";
 256                         reg = <0x9f10000 0x1000>;
 257                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 258                         clock-names = "bdisp";
 259                         clocks = <&clk_s_c0_flexgen CLK_IC_BDISP_0>;
 260                 };
 261
 262                 hva@8c85000 {
 263                         compatible = "st,st-hva";
 264                         reg = <0x8c85000 0x400>, <0x6000000 0x40000>;
 265                         reg-names = "hva_registers", "hva_esram";
 266                         interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
 267                                      <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 268                         clock-names = "clk_hva";
 269                         clocks = <&clk_s_c0_flexgen CLK_HVA>;
 270                 };
 271
 272                 thermal@91a0000 {
 273                         compatible = "st,stih407-thermal";
 274                         reg = <0x91a0000 0x28>;
 275                         clock-names = "thermal";
 276                         clocks = <&clk_sysin>;
 277                         interrupts = <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>;
 278                 };
 279
 280                 delta0@0 {
 281                         compatible = "st,st-delta";
 282                         clock-names = "delta",
 283                                       "delta-st231",
 284                                       "delta-flash-promip";
 285                         clocks = <&clk_s_c0_flexgen CLK_VID_DMU>,
 286                                  <&clk_s_c0_flexgen CLK_ST231_DMU>,
 287                                  <&clk_s_c0_flexgen CLK_FLASH_PROMIP>;
 288                 };
 289
 290                 sti-cec@94a087c {
 291                         compatible = "st,stih-cec";
 292                         reg = <0x94a087c 0x64>;
 293                         clocks = <&clk_sysin>;
 294                         clock-names = "cec-clk";
 295                         interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 296                         interrupt-names = "cec-irq";
 297                         pinctrl-names = "default";
 298                         pinctrl-0 = <&pinctrl_cec0_default>;
 299                         resets = <&softreset STIH407_LPM_SOFTRESET>;
 300                         hdmi-phandle = <&sti_hdmi>;
 301                 };
 302         };
 303 };