arch/arm/boot/dts/stih410.dtsi

   1 /*
   2  * Copyright (C) 2014 STMicroelectronics Limited.
   3  * Author: Peter Griffin <peter.griffin@linaro.org>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * publishhed by the Free Software Foundation.
   8  */
   9 #include "stih410-clock.dtsi"
  10 #include "stih407-family.dtsi"
  11 #include "stih410-pinctrl.dtsi"
  12 #include <dt-bindings/gpio/gpio.h>
  13 / {
  14         aliases {
  15                 bdisp0 = &bdisp0;
  16         };
  17
  18         soc {
  19                 usb2_picophy1: phy2 {
  20                         compatible = "st,stih407-usb2-phy";
  21                         #phy-cells = <0>;
  22                         st,syscfg = <&syscfg_core 0xf8 0xf4>;
  23                         resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
  24                                  <&picophyreset STIH407_PICOPHY0_RESET>;
  25                         reset-names = "global", "port";
  26
  27                         status = "disabled";
  28                 };
  29
  30                 usb2_picophy2: phy3 {
  31                         compatible = "st,stih407-usb2-phy";
  32                         #phy-cells = <0>;
  33                         st,syscfg = <&syscfg_core 0xfc 0xf4>;
  34                         resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
  35                                  <&picophyreset STIH407_PICOPHY1_RESET>;
  36                         reset-names = "global", "port";
  37
  38                         status = "disabled";
  39                 };
  40
  41                 ohci0: usb@9a03c00 {
  42                         compatible = "st,st-ohci-300x";
  43                         reg = <0x9a03c00 0x100>;
  44                         interrupts = <GIC_SPI 180 IRQ_TYPE_NONE>;
  45                         clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
  46                                  <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
  47                         resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
  48                                  <&softreset STIH407_USB2_PORT0_SOFTRESET>;
  49                         reset-names = "power", "softreset";
  50                         phys = <&usb2_picophy1>;
  51                         phy-names = "usb";
  52
  53                         status = "disabled";
  54                 };
  55
  56                 ehci0: usb@9a03e00 {
  57                         compatible = "st,st-ehci-300x";
  58                         reg = <0x9a03e00 0x100>;
  59                         interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
  60                         pinctrl-names = "default";
  61                         pinctrl-0 = <&pinctrl_usb0>;
  62                         clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
  63                                  <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
  64                         resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
  65                                  <&softreset STIH407_USB2_PORT0_SOFTRESET>;
  66                         reset-names = "power", "softreset";
  67                         phys = <&usb2_picophy1>;
  68                         phy-names = "usb";
  69
  70                         status = "disabled";
  71                 };
  72
  73                 ohci1: usb@9a83c00 {
  74                         compatible = "st,st-ohci-300x";
  75                         reg = <0x9a83c00 0x100>;
  76                         interrupts = <GIC_SPI 181 IRQ_TYPE_NONE>;
  77                         clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
  78                                  <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
  79                         resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
  80                                  <&softreset STIH407_USB2_PORT1_SOFTRESET>;
  81                         reset-names = "power", "softreset";
  82                         phys = <&usb2_picophy2>;
  83                         phy-names = "usb";
  84
  85                         status = "disabled";
  86                 };
  87
  88                 ehci1: usb@9a83e00 {
  89                         compatible = "st,st-ehci-300x";
  90                         reg = <0x9a83e00 0x100>;
  91                         interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;
  92                         pinctrl-names = "default";
  93                         pinctrl-0 = <&pinctrl_usb1>;
  94                         clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
  95                                  <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
  96                         resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
  97                                  <&softreset STIH407_USB2_PORT1_SOFTRESET>;
  98                         reset-names = "power", "softreset";
  99                         phys = <&usb2_picophy2>;
 100                         phy-names = "usb";
 101
 102                         status = "disabled";
 103                 };
 104
 105                 sti-display-subsystem {
 106                         compatible = "st,sti-display-subsystem";
 107                         #address-cells = <1>;
 108                         #size-cells = <1>;
 109
 110                         assigned-clocks = <&clk_s_d2_quadfs 0>,
 111                                           <&clk_s_d2_quadfs 0>,
 112                                           <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
 113                                           <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
 114                                           <&clk_s_d2_flexgen CLK_PIX_GDP1>,
 115                                           <&clk_s_d2_flexgen CLK_PIX_GDP2>,
 116                                           <&clk_s_d2_flexgen CLK_PIX_GDP3>,
 117                                           <&clk_s_d2_flexgen CLK_PIX_GDP4>;
 118
 119                         assigned-clock-parents = <0>,
 120                                                  <0>,
 121                                                  <&clk_s_d2_quadfs 0>,
 122                                                  <&clk_s_d2_quadfs 0>,
 123                                                  <&clk_s_d2_quadfs 0>,
 124                                                  <&clk_s_d2_quadfs 0>,
 125                                                  <&clk_s_d2_quadfs 0>,
 126                                                  <&clk_s_d2_quadfs 0>;
 127
 128                         assigned-clock-rates = <297000000>, <297000000>;
 129
 130                         ranges;
 131
 132                         sti-compositor@9d11000 {
 133                                 compatible = "st,stih407-compositor";
 134                                 reg = <0x9d11000 0x1000>;
 135
 136                                 clock-names = "compo_main",
 137                                               "compo_aux",
 138                                               "pix_main",
 139                                               "pix_aux",
 140                                               "pix_gdp1",
 141                                               "pix_gdp2",
 142                                               "pix_gdp3",
 143                                               "pix_gdp4",
 144                                               "main_parent",
 145                                               "aux_parent";
 146
 147                                 clocks = <&clk_s_c0_flexgen CLK_COMPO_DVP>,
 148                                          <&clk_s_c0_flexgen CLK_COMPO_DVP>,
 149                                          <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
 150                                          <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
 151                                          <&clk_s_d2_flexgen CLK_PIX_GDP1>,
 152                                          <&clk_s_d2_flexgen CLK_PIX_GDP2>,
 153                                          <&clk_s_d2_flexgen CLK_PIX_GDP3>,
 154                                          <&clk_s_d2_flexgen CLK_PIX_GDP4>,
 155                                          <&clk_s_d2_quadfs 0>,
 156                                          <&clk_s_d2_quadfs 1>;
 157
 158                                 reset-names = "compo-main", "compo-aux";
 159                                 resets = <&softreset STIH407_COMPO_SOFTRESET>,
 160                                          <&softreset STIH407_COMPO_SOFTRESET>;
 161                                 st,vtg = <&vtg_main>, <&vtg_aux>;
 162                         };
 163
 164                         sti-tvout@8d08000 {
 165                                 compatible = "st,stih407-tvout";
 166                                 reg = <0x8d08000 0x1000>;
 167                                 reg-names = "tvout-reg";
 168                                 reset-names = "tvout";
 169                                 resets = <&softreset STIH407_HDTVOUT_SOFTRESET>;
 170                                 #address-cells = <1>;
 171                                 #size-cells = <1>;
 172                                 assigned-clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
 173                                                   <&clk_s_d2_flexgen CLK_TMDS_HDMI>,
 174                                                   <&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
 175                                                   <&clk_s_d0_flexgen CLK_PCM_0>,
 176                                                   <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
 177                                                   <&clk_s_d2_flexgen CLK_HDDAC>;
 178
 179                                 assigned-clock-parents = <&clk_s_d2_quadfs 0>,
 180                                                          <&clk_tmdsout_hdmi>,
 181                                                          <&clk_s_d2_quadfs 0>,
 182                                                          <&clk_s_d0_quadfs 0>,
 183                                                          <&clk_s_d2_quadfs 0>,
 184                                                          <&clk_s_d2_quadfs 0>;
 185                         };
 186
 187                         sti-hdmi@8d04000 {
 188                                 compatible = "st,stih407-hdmi";
 189                                 reg = <0x8d04000 0x1000>;
 190                                 reg-names = "hdmi-reg";
 191                                 interrupts = <GIC_SPI 106 IRQ_TYPE_NONE>;
 192                                 interrupt-names = "irq";
 193                                 clock-names = "pix",
 194                                               "tmds",
 195                                               "phy",
 196                                               "audio",
 197                                               "main_parent",
 198                                               "aux_parent";
 199
 200                                 clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
 201                                          <&clk_s_d2_flexgen CLK_TMDS_HDMI>,
 202                                          <&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
 203                                          <&clk_s_d0_flexgen CLK_PCM_0>,
 204                                          <&clk_s_d2_quadfs 0>,
 205                                          <&clk_s_d2_quadfs 1>;
 206
 207                                 hdmi,hpd-gpio = <&pio5 3 GPIO_ACTIVE_LOW>;
 208                                 reset-names = "hdmi";
 209                                 resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>;
 210                                 ddc = <&hdmiddc>;
 211                         };
 212
 213                         sti-hda@8d02000 {
 214                                 compatible = "st,stih407-hda";
 215                                 reg = <0x8d02000 0x400>, <0x92b0120 0x4>;
 216                                 reg-names = "hda-reg", "video-dacs-ctrl";
 217                                 clock-names = "pix",
 218                                               "hddac",
 219                                               "main_parent",
 220                                               "aux_parent";
 221                                 clocks = <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
 222                                          <&clk_s_d2_flexgen CLK_HDDAC>,
 223                                          <&clk_s_d2_quadfs 0>,
 224                                          <&clk_s_d2_quadfs 1>;
 225                         };
 226                 };
 227
 228                 bdisp0:bdisp@9f10000 {
 229                         compatible = "st,stih407-bdisp";
 230                         reg = <0x9f10000 0x1000>;
 231                         interrupts = <GIC_SPI 38 IRQ_TYPE_NONE>;
 232                         clock-names = "bdisp";
 233                         clocks = <&clk_s_c0_flexgen CLK_IC_BDISP_0>;
 234                 };
 235         };
 236 };