arch/arm/boot/dts/stih407.dtsi

   1 /*
   2  * Copyright (C) 2015 STMicroelectronics Limited.
   3  * Author: Gabriel Fernandez <gabriel.fernandez@linaro.org>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * publishhed by the Free Software Foundation.
   8  */
   9 #include "stih407-clock.dtsi"
  10 #include "stih407-family.dtsi"
  11 #include <dt-bindings/gpio/gpio.h>
  12 / {
  13         soc {
  14                 sti-display-subsystem@0 {
  15                         compatible = "st,sti-display-subsystem";
  16                         #address-cells = <1>;
  17                         #size-cells = <1>;
  18                         reg = <0 0>;
  19                         assigned-clocks = <&clk_s_d2_quadfs 0>,
  20                                           <&clk_s_d2_quadfs 1>,
  21                                           <&clk_s_c0_pll1 0>,
  22                                           <&clk_s_c0_flexgen CLK_COMPO_DVP>,
  23                                           <&clk_s_c0_flexgen CLK_MAIN_DISP>,
  24                                           <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
  25                                           <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
  26                                           <&clk_s_d2_flexgen CLK_PIX_GDP1>,
  27                                           <&clk_s_d2_flexgen CLK_PIX_GDP2>,
  28                                           <&clk_s_d2_flexgen CLK_PIX_GDP3>,
  29                                           <&clk_s_d2_flexgen CLK_PIX_GDP4>;
  30
  31                         assigned-clock-parents = <0>,
  32                                                  <0>,
  33                                                  <0>,
  34                                                  <&clk_s_c0_pll1 0>,
  35                                                  <&clk_s_c0_pll1 0>,
  36                                                  <&clk_s_d2_quadfs 0>,
  37                                                  <&clk_s_d2_quadfs 1>,
  38                                                  <&clk_s_d2_quadfs 0>,
  39                                                  <&clk_s_d2_quadfs 0>,
  40                                                  <&clk_s_d2_quadfs 0>,
  41                                                  <&clk_s_d2_quadfs 0>;
  42
  43                         assigned-clock-rates = <297000000>,
  44                                                <108000000>,
  45                                                <0>,
  46                                                <400000000>,
  47                                                <400000000>;
  48
  49                         ranges;
  50
  51                         sti-compositor@9d11000 {
  52                                 compatible = "st,stih407-compositor";
  53                                 reg = <0x9d11000 0x1000>;
  54
  55                                 clock-names = "compo_main",
  56                                               "compo_aux",
  57                                               "pix_main",
  58                                               "pix_aux",
  59                                               "pix_gdp1",
  60                                               "pix_gdp2",
  61                                               "pix_gdp3",
  62                                               "pix_gdp4",
  63                                               "main_parent",
  64                                               "aux_parent";
  65
  66                                 clocks = <&clk_s_c0_flexgen CLK_COMPO_DVP>,
  67                                          <&clk_s_c0_flexgen CLK_COMPO_DVP>,
  68                                          <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
  69                                          <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
  70                                          <&clk_s_d2_flexgen CLK_PIX_GDP1>,
  71                                          <&clk_s_d2_flexgen CLK_PIX_GDP2>,
  72                                          <&clk_s_d2_flexgen CLK_PIX_GDP3>,
  73                                          <&clk_s_d2_flexgen CLK_PIX_GDP4>,
  74                                          <&clk_s_d2_quadfs 0>,
  75                                          <&clk_s_d2_quadfs 1>;
  76
  77                                 reset-names = "compo-main", "compo-aux";
  78                                 resets = <&softreset STIH407_COMPO_SOFTRESET>,
  79                                          <&softreset STIH407_COMPO_SOFTRESET>;
  80                                 st,vtg = <&vtg_main>, <&vtg_aux>;
  81                         };
  82
  83                         sti-tvout@8d08000 {
  84                                 compatible = "st,stih407-tvout";
  85                                 reg = <0x8d08000 0x1000>;
  86                                 reg-names = "tvout-reg";
  87                                 reset-names = "tvout";
  88                                 resets = <&softreset STIH407_HDTVOUT_SOFTRESET>;
  89                                 #address-cells = <1>;
  90                                 #size-cells = <1>;
  91                                 assigned-clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
  92                                                   <&clk_s_d2_flexgen CLK_TMDS_HDMI>,
  93                                                   <&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
  94                                                   <&clk_s_d0_flexgen CLK_PCM_0>,
  95                                                   <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
  96                                                   <&clk_s_d2_flexgen CLK_HDDAC>;
  97
  98                                 assigned-clock-parents = <&clk_s_d2_quadfs 0>,
  99                                                          <&clk_tmdsout_hdmi>,
 100                                                          <&clk_s_d2_quadfs 0>,
 101                                                          <&clk_s_d0_quadfs 0>,
 102                                                          <&clk_s_d2_quadfs 0>,
 103                                                          <&clk_s_d2_quadfs 0>;
 104                         };
 105
 106                         sti_hdmi: sti-hdmi@8d04000 {
 107                                 compatible = "st,stih407-hdmi";
 108                                 reg = <0x8d04000 0x1000>;
 109                                 reg-names = "hdmi-reg";
 110                                 #sound-dai-cells = <0>;
 111                                 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 112                                 interrupt-names = "irq";
 113                                 clock-names = "pix",
 114                                               "tmds",
 115                                               "phy",
 116                                               "audio",
 117                                               "main_parent",
 118                                               "aux_parent";
 119
 120                                 clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
 121                                          <&clk_s_d2_flexgen CLK_TMDS_HDMI>,
 122                                          <&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
 123                                          <&clk_s_d0_flexgen CLK_PCM_0>,
 124                                          <&clk_s_d2_quadfs 0>,
 125                                          <&clk_s_d2_quadfs 1>;
 126
 127                                 hdmi,hpd-gpio = <&pio5 3 GPIO_ACTIVE_LOW>;
 128                                 reset-names = "hdmi";
 129                                 resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>;
 130                                 ddc = <&hdmiddc>;
 131                         };
 132
 133                         sti-hda@8d02000 {
 134                                 compatible = "st,stih407-hda";
 135                                 reg = <0x8d02000 0x400>, <0x92b0120 0x4>;
 136                                 reg-names = "hda-reg", "video-dacs-ctrl";
 137                                 clock-names = "pix",
 138                                               "hddac",
 139                                               "main_parent",
 140                                               "aux_parent";
 141                                 clocks = <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
 142                                          <&clk_s_d2_flexgen CLK_HDDAC>,
 143                                          <&clk_s_d2_quadfs 0>,
 144                                          <&clk_s_d2_quadfs 1>;
 145                         };
 146                 };
 147         };
 148 };