2 * Copyright 2013 Linaro Ltd.
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
12 #include "ste-nomadik-pinctrl.dtsi"
17 /* Settings for all UART default and sleep states */
19 uart0_default_mode: uart0_default {
25 pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */
26 ste,config = <&in_pu>;
30 pins = "GPIO1_AJ3", "GPIO3_AH3"; /* RTS+TXD */
31 ste,config = <&out_hi>;
35 uart0_sleep_mode: uart0_sleep {
37 pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */
38 ste,config = <&slpm_in_wkup_pdis>;
42 pins = "GPIO1_AJ3"; /* RTS */
43 ste,config = <&slpm_out_hi_wkup_pdis>;
47 pins = "GPIO3_AH3"; /* TXD */
48 ste,config = <&slpm_out_wkup_pdis>;
54 uart1_default_mode: uart1_default {
57 groups = "u1rxtx_a_1";
60 pins = "GPIO4_AH6"; /* RXD */
61 ste,config = <&in_pu>;
65 pins = "GPIO5_AG6"; /* TXD */
66 ste,config = <&out_hi>;
70 uart1_sleep_mode: uart1_sleep {
72 pins = "GPIO4_AH6"; /* RXD */
73 ste,config = <&slpm_in_wkup_pdis>;
77 pins = "GPIO5_AG6"; /* TXD */
78 ste,config = <&slpm_out_wkup_pdis>;
84 uart2_default_mode: uart2_default {
87 groups = "u2rxtx_c_1";
90 pins = "GPIO29_W2"; /* RXD */
91 ste,config = <&in_pu>;
95 pins = "GPIO30_W3"; /* TXD */
96 ste,config = <&out_hi>;
100 uart2_sleep_mode: uart2_sleep {
102 pins = "GPIO29_W2"; /* RXD */
103 ste,config = <&in_wkup_pdis>;
107 pins = "GPIO30_W3"; /* TXD */
108 ste,config = <&out_wkup_pdis>;
113 /* Settings for all I2C default and sleep states */
115 i2c0_default_mode: i2c_default {
121 pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */
122 ste,config = <&in_pu>;
126 i2c0_sleep_mode: i2c_sleep {
128 pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */
129 ste,config = <&slpm_in_wkup_pdis>;
135 i2c1_default_mode: i2c_default {
141 pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */
142 ste,config = <&in_pu>;
146 i2c1_sleep_mode: i2c_sleep {
148 pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */
149 ste,config = <&slpm_in_wkup_pdis>;
155 i2c2_default_mode: i2c_default {
161 pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */
162 ste,config = <&in_pu>;
166 i2c2_sleep_mode: i2c_sleep {
168 pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */
169 ste,config = <&slpm_in_wkup_pdis>;
175 i2c3_default_mode: i2c_default {
181 pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */
182 ste,config = <&in_pu>;
186 i2c3_sleep_mode: i2c_sleep {
188 pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */
189 ste,config = <&slpm_in_wkup_pdis>;
195 * Activating I2C4 will conflict with UART1 about the same pins so do not
196 * enable I2C4 and UART1 at the same time.
199 i2c4_default_mode: i2c_default {
205 pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */
206 ste,config = <&in_pu>;
210 i2c4_sleep_mode: i2c_sleep {
212 pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */
213 ste,config = <&slpm_in_wkup_pdis>;
218 /* Settings for all SPI default and sleep states */
220 spi2_default_mode: spi_default {
223 groups = "spi2_oc1_2";
226 pins = "GPIO216_AG12"; /* FRM */
227 ste,config = <&gpio_out_hi>;
230 pins = "GPIO218_AH11"; /* RXD */
231 ste,config = <&in_pd>;
235 "GPIO215_AH13", /* TXD */
236 "GPIO217_AH12"; /* CLK */
237 ste,config = <&out_lo>;
241 spi2_idle_mode: spi_idle {
243 * The idle mode is basically sleep mode sans wakeups. Also
244 * note that we have muxes the pins off the function here
245 * as we do not state any muxing.
248 pins = "GPIO218_AH11"; /* RXD */
249 ste,config = <&slpm_in_pdis>;
252 pins = "GPIO215_AH13"; /* TXD */
253 ste,config = <&slpm_out_lo_pdis>;
256 pins = "GPIO217_AH12"; /* CLK */
257 ste,config = <&slpm_pdis>;
261 spi2_sleep_mode: spi_sleep {
264 "GPIO216_AG12", /* FRM */
265 "GPIO218_AH11"; /* RXD */
266 ste,config = <&slpm_in_wkup_pdis>;
269 pins = "GPIO215_AH13"; /* TXD */
270 ste,config = <&slpm_out_lo_wkup_pdis>;
273 pins = "GPIO217_AH12"; /* CLK */
274 ste,config = <&slpm_wkup_pdis>;
279 /* Settings for all MMC/SD/SDIO default and sleep states */
281 /* This is the external SD card slot, 4 bits wide */
282 sdi0_default_mode: sdi0_default {
289 "GPIO18_AC2", /* CMDDIR */
290 "GPIO19_AC1", /* DAT0DIR */
291 "GPIO20_AB4"; /* DAT2DIR */
292 ste,config = <&out_hi>;
295 pins = "GPIO22_AA3"; /* FBCLK */
296 ste,config = <&in_nopull>;
299 pins = "GPIO23_AA4"; /* CLK */
300 ste,config = <&out_lo>;
304 "GPIO24_AB2", /* CMD */
305 "GPIO25_Y4", /* DAT0 */
306 "GPIO26_Y2", /* DAT1 */
307 "GPIO27_AA2", /* DAT2 */
308 "GPIO28_AA1"; /* DAT3 */
309 ste,config = <&in_pu>;
313 sdi0_sleep_mode: sdi0_sleep {
316 "GPIO18_AC2", /* CMDDIR */
317 "GPIO19_AC1", /* DAT0DIR */
318 "GPIO20_AB4"; /* DAT2DIR */
319 ste,config = <&slpm_out_hi_wkup_pdis>;
323 "GPIO22_AA3", /* FBCLK */
324 "GPIO24_AB2", /* CMD */
325 "GPIO25_Y4", /* DAT0 */
326 "GPIO26_Y2", /* DAT1 */
327 "GPIO27_AA2", /* DAT2 */
328 "GPIO28_AA1"; /* DAT3 */
329 ste,config = <&slpm_in_wkup_pdis>;
332 pins = "GPIO23_AA4"; /* CLK */
333 ste,config = <&slpm_out_lo_wkup_pdis>;
339 /* This is the WLAN SDIO 4 bits wide */
340 sdi1_default_mode: sdi1_default {
346 pins = "GPIO208_AH16"; /* CLK */
347 ste,config = <&out_lo>;
350 pins = "GPIO209_AG15"; /* FBCLK */
351 ste,config = <&in_nopull>;
355 "GPIO210_AJ15", /* CMD */
356 "GPIO211_AG14", /* DAT0 */
357 "GPIO212_AF13", /* DAT1 */
358 "GPIO213_AG13", /* DAT2 */
359 "GPIO214_AH15"; /* DAT3 */
360 ste,config = <&in_pu>;
364 sdi1_sleep_mode: sdi1_sleep {
366 pins = "GPIO208_AH16"; /* CLK */
367 ste,config = <&slpm_out_lo_wkup_pdis>;
371 "GPIO209_AG15", /* FBCLK */
372 "GPIO210_AJ15", /* CMD */
373 "GPIO211_AG14", /* DAT0 */
374 "GPIO212_AF13", /* DAT1 */
375 "GPIO213_AG13", /* DAT2 */
376 "GPIO214_AH15"; /* DAT3 */
377 ste,config = <&slpm_in_wkup_pdis>;
383 /* This is the eMMC 8 bits wide, usually PoP eMMC */
384 sdi2_default_mode: sdi2_default {
390 pins = "GPIO128_A5"; /* CLK */
391 ste,config = <&out_lo>;
394 pins = "GPIO130_C8"; /* FBCLK */
395 ste,config = <&in_nopull>;
399 "GPIO129_B4", /* CMD */
400 "GPIO131_A12", /* DAT0 */
401 "GPIO132_C10", /* DAT1 */
402 "GPIO133_B10", /* DAT2 */
403 "GPIO134_B9", /* DAT3 */
404 "GPIO135_A9", /* DAT4 */
405 "GPIO136_C7", /* DAT5 */
406 "GPIO137_A7", /* DAT6 */
407 "GPIO138_C5"; /* DAT7 */
408 ste,config = <&in_pu>;
412 sdi2_sleep_mode: sdi2_sleep {
414 pins = "GPIO128_A5"; /* CLK */
415 ste,config = <&out_lo_wkup_pdis>;
419 "GPIO130_C8", /* FBCLK */
420 "GPIO129_B4"; /* CMD */
421 ste,config = <&in_wkup_pdis_en>;
425 "GPIO131_A12", /* DAT0 */
426 "GPIO132_C10", /* DAT1 */
427 "GPIO133_B10", /* DAT2 */
428 "GPIO134_B9", /* DAT3 */
429 "GPIO135_A9", /* DAT4 */
430 "GPIO136_C7", /* DAT5 */
431 "GPIO137_A7", /* DAT6 */
432 "GPIO138_C5"; /* DAT7 */
433 ste,config = <&in_wkup_pdis>;
439 /* This is the eMMC 8 bits wide, usually PCB-mounted eMMC */
440 sdi4_default_mode: sdi4_default {
446 pins = "GPIO203_AE23"; /* CLK */
447 ste,config = <&out_lo>;
450 pins = "GPIO202_AF25"; /* FBCLK */
451 ste,config = <&in_nopull>;
455 "GPIO201_AF24", /* CMD */
456 "GPIO200_AH26", /* DAT0 */
457 "GPIO199_AH23", /* DAT1 */
458 "GPIO198_AG25", /* DAT2 */
459 "GPIO197_AH24", /* DAT3 */
460 "GPIO207_AJ23", /* DAT4 */
461 "GPIO206_AG24", /* DAT5 */
462 "GPIO205_AG23", /* DAT6 */
463 "GPIO204_AF23"; /* DAT7 */
464 ste,config = <&in_pu>;
468 sdi4_sleep_mode: sdi4_sleep {
470 pins = "GPIO203_AE23"; /* CLK */
471 ste,config = <&out_lo_wkup_pdis>;
475 "GPIO202_AF25", /* FBCLK */
476 "GPIO201_AF24", /* CMD */
477 "GPIO200_AH26", /* DAT0 */
478 "GPIO199_AH23", /* DAT1 */
479 "GPIO198_AG25", /* DAT2 */
480 "GPIO197_AH24", /* DAT3 */
481 "GPIO207_AJ23", /* DAT4 */
482 "GPIO206_AG24", /* DAT5 */
483 "GPIO205_AG23", /* DAT6 */
484 "GPIO204_AF23"; /* DAT7 */
485 ste,config = <&slpm_in_wkup_pdis>;
491 * Multi-rate serial ports (MSPs) - MSP3 output is internal and
492 * cannot be muxed onto any pins.
495 msp0_default_mode: msp0_default {
498 groups = "msp0txrx_a_1", "msp0tfstck_a_1";
502 "GPIO12_AC4", /* TXD */
503 "GPIO15_AC3", /* RXD */
504 "GPIO13_AF3", /* TFS */
505 "GPIO14_AE3"; /* TCK */
506 ste,config = <&in_nopull>;
512 msp1_default_mode: msp1_default {
515 groups = "msp1txrx_a_1", "msp1_a_1";
519 ste,config = <&out_lo>;
526 ste,config = <&in_nopull>;
533 msp2_default_mode: msp2_default {
534 /* MSP2 usually used for HDMI audio */
541 "GPIO193_AH27", /* TXD */
542 "GPIO194_AF27", /* TCK */
543 "GPIO195_AG28"; /* TFS */
544 ste,config = <&in_pd>;
547 pins = "GPIO196_AG26"; /* RXD */
548 ste,config = <&out_lo>;
555 musb_default_mode: musb_default {
562 "GPIO256_AF28", /* NXT */
563 "GPIO258_AD29", /* XCLK */
564 "GPIO259_AC29", /* DIR */
565 "GPIO260_AD28", /* DAT7 */
566 "GPIO261_AD26", /* DAT6 */
567 "GPIO262_AE26", /* DAT5 */
568 "GPIO263_AG29", /* DAT4 */
569 "GPIO264_AE27", /* DAT3 */
570 "GPIO265_AD27", /* DAT2 */
571 "GPIO266_AC28", /* DAT1 */
572 "GPIO267_AC27"; /* DAT0 */
573 ste,config = <&in_nopull>;
576 pins = "GPIO257_AE29"; /* STP */
577 ste,config = <&out_hi>;
581 musb_sleep_mode: musb_sleep {
584 "GPIO256_AF28", /* NXT */
585 "GPIO258_AD29", /* XCLK */
586 "GPIO259_AC29"; /* DIR */
587 ste,config = <&slpm_wkup_pdis_en>;
590 pins = "GPIO257_AE29"; /* STP */
591 ste,config = <&slpm_out_hi_wkup_pdis>;
595 "GPIO260_AD28", /* DAT7 */
596 "GPIO261_AD26", /* DAT6 */
597 "GPIO262_AE26", /* DAT5 */
598 "GPIO263_AG29", /* DAT4 */
599 "GPIO264_AE27", /* DAT3 */
600 "GPIO265_AD27", /* DAT2 */
601 "GPIO266_AC28", /* DAT1 */
602 "GPIO267_AC27"; /* DAT0 */
603 ste,config = <&slpm_in_wkup_pdis_en>;
609 lcd_default_mode: lcd_default {
611 /* Mux in VSI0 and all the data lines */
614 "lcdvsi0_a_1", /* VSI0 for LCD */
615 "lcd_d0_d7_a_1", /* Data lines */
616 "lcd_d8_d11_a_1", /* TV-out */
617 "lcdvsi1_a_1"; /* VSI1 for HDMI */
622 "lcdaclk_b_1"; /* Clock line for TV-out */
626 "GPIO68_E1", /* VSI0 */
627 "GPIO69_E2"; /* VSI1 */
628 ste,config = <&in_pu>;
631 lcd_sleep_mode: lcd_sleep {
633 pins = "GPIO69_E2"; /* VSI1 */
634 ste,config = <&slpm_in_wkup_pdis>;
640 /* SKE keys on position 2 in an 8x8 matrix */
641 ske_kpa2_default_mode: ske_kpa2_default {
648 "GPIO153_B17", /* I7 */
649 "GPIO154_C16", /* I6 */
650 "GPIO155_C19", /* I5 */
651 "GPIO156_C17", /* I4 */
652 "GPIO161_D21", /* I3 */
653 "GPIO162_D20", /* I2 */
654 "GPIO163_C20", /* I1 */
655 "GPIO164_B21"; /* I0 */
656 ste,config = <&in_pd>;
660 "GPIO157_A18", /* O7 */
661 "GPIO158_C18", /* O6 */
662 "GPIO159_B19", /* O5 */
663 "GPIO160_B20", /* O4 */
664 "GPIO165_C21", /* O3 */
665 "GPIO166_A22", /* O2 */
666 "GPIO167_B24", /* O1 */
667 "GPIO168_C22"; /* O0 */
668 ste,config = <&out_lo>;
671 ske_kpa2_sleep_mode: ske_kpa2_sleep {
674 "GPIO153_B17", /* I7 */
675 "GPIO154_C16", /* I6 */
676 "GPIO155_C19", /* I5 */
677 "GPIO156_C17", /* I4 */
678 "GPIO161_D21", /* I3 */
679 "GPIO162_D20", /* I2 */
680 "GPIO163_C20", /* I1 */
681 "GPIO164_B21"; /* I0 */
682 ste,config = <&slpm_in_pu_wkup_pdis_en>;
686 "GPIO157_A18", /* O7 */
687 "GPIO158_C18", /* O6 */
688 "GPIO159_B19", /* O5 */
689 "GPIO160_B20", /* O4 */
690 "GPIO165_C21", /* O3 */
691 "GPIO166_A22", /* O2 */
692 "GPIO167_B24", /* O1 */
693 "GPIO168_C22"; /* O0 */
694 ste,config = <&slpm_out_lo_pdis>;
698 * SKE keys on position 1 and "other C1" combi giving
699 * six rows of six keys.
701 ske_kpaoc1_default_mode: ske_kpaoc1_default {
704 groups = "kp_a_1", "kp_oc1_1";
708 "GPIO91_B6", /* KP_O0 */
709 "GPIO90_A3", /* KP_O1 */
710 "GPIO87_B3", /* KP_O2 */
711 "GPIO86_C6", /* KP_O3 */
712 "GPIO96_D8", /* KP_O6 */
713 "GPIO94_D7"; /* KP_O7 */
714 ste,config = <&out_lo>;
718 "GPIO93_B7", /* KP_I0 */
719 "GPIO92_D6", /* KP_I1 */
720 "GPIO89_E6", /* KP_I2 */
721 "GPIO88_C4", /* KP_I3 */
722 "GPIO97_D9", /* KP_I6 */
723 "GPIO95_E8"; /* KP_I7 */
724 ste,config = <&in_pu>;
730 wlan_default_mode: wlan_default {
732 * Activate this mode with the WLAN chip.
733 * These are plain GPIO pins used by WLAN
737 "GPIO226_AF8", /* WLAN_PMU_EN */
738 "GPIO85_D5"; /* WLAN_ENA */
739 ste,config = <&gpio_out_lo>;
742 pins = "GPIO4_AH6"; /* WLAN_IRQ on UART1 */
743 ste,config = <&gpio_in_pu>;