arch/arm/boot/dts/socfpga_arria10.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright Altera Corporation (C) 2014. All rights reserved.
   4  */
   5
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
   8
   9 / {
  10         #address-cells = <1>;
  11         #size-cells = <1>;
  12
  13         cpus {
  14                 #address-cells = <1>;
  15                 #size-cells = <0>;
  16                 enable-method = "altr,socfpga-a10-smp";
  17
  18                 cpu0: cpu@0 {
  19                         compatible = "arm,cortex-a9";
  20                         device_type = "cpu";
  21                         reg = <0>;
  22                         next-level-cache = <&L2>;
  23                 };
  24                 cpu1: cpu@1 {
  25                         compatible = "arm,cortex-a9";
  26                         device_type = "cpu";
  27                         reg = <1>;
  28                         next-level-cache = <&L2>;
  29                 };
  30         };
  31
  32         pmu: pmu@ff111000 {
  33                 compatible = "arm,cortex-a9-pmu";
  34                 interrupt-parent = <&intc>;
  35                 interrupts = <0 124 4>, <0 125 4>;
  36                 interrupt-affinity = <&cpu0>, <&cpu1>;
  37                 reg = <0xff111000 0x1000>,
  38                       <0xff113000 0x1000>;
  39         };
  40
  41         intc: interrupt-controller@ffffd000 {
  42                 compatible = "arm,cortex-a9-gic";
  43                 #interrupt-cells = <3>;
  44                 interrupt-controller;
  45                 reg = <0xffffd000 0x1000>,
  46                       <0xffffc100 0x100>;
  47         };
  48
  49         soc {
  50                 #address-cells = <1>;
  51                 #size-cells = <1>;
  52                 compatible = "simple-bus";
  53                 device_type = "soc";
  54                 interrupt-parent = <&intc>;
  55                 ranges;
  56
  57                 amba {
  58                         compatible = "simple-bus";
  59                         #address-cells = <1>;
  60                         #size-cells = <1>;
  61                         ranges;
  62
  63                         pdma: pdma@ffda1000 {
  64                                 compatible = "arm,pl330", "arm,primecell";
  65                                 reg = <0xffda1000 0x1000>;
  66                                 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>,
  67                                              <0 84 IRQ_TYPE_LEVEL_HIGH>,
  68                                              <0 85 IRQ_TYPE_LEVEL_HIGH>,
  69                                              <0 86 IRQ_TYPE_LEVEL_HIGH>,
  70                                              <0 87 IRQ_TYPE_LEVEL_HIGH>,
  71                                              <0 88 IRQ_TYPE_LEVEL_HIGH>,
  72                                              <0 89 IRQ_TYPE_LEVEL_HIGH>,
  73                                              <0 90 IRQ_TYPE_LEVEL_HIGH>,
  74                                              <0 91 IRQ_TYPE_LEVEL_HIGH>;
  75                                 #dma-cells = <1>;
  76                                 clocks = <&l4_main_clk>;
  77                                 clock-names = "apb_pclk";
  78                                 resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>;
  79                                 reset-names = "dma", "dma-ocp";
  80                         };
  81                 };
  82
  83                 base_fpga_region {
  84                         #address-cells = <0x1>;
  85                         #size-cells = <0x1>;
  86
  87                         compatible = "fpga-region";
  88                         fpga-mgr = <&fpga_mgr>;
  89                 };
  90
  91                 clkmgr@ffd04000 {
  92                                 compatible = "altr,clk-mgr";
  93                                 reg = <0xffd04000 0x1000>;
  94
  95                                 clocks {
  96                                         #address-cells = <1>;
  97                                         #size-cells = <0>;
  98
  99                                         cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk {
 100                                                 #clock-cells = <0>;
 101                                                 compatible = "fixed-clock";
 102                                         };
 103
 104                                         cb_intosc_ls_clk: cb_intosc_ls_clk {
 105                                                 #clock-cells = <0>;
 106                                                 compatible = "fixed-clock";
 107                                         };
 108
 109                                         f2s_free_clk: f2s_free_clk {
 110                                                 #clock-cells = <0>;
 111                                                 compatible = "fixed-clock";
 112                                         };
 113
 114                                         osc1: osc1 {
 115                                                 #clock-cells = <0>;
 116                                                 compatible = "fixed-clock";
 117                                         };
 118
 119                                         main_pll: main_pll@40 {
 120                                                 #address-cells = <1>;
 121                                                 #size-cells = <0>;
 122                                                 #clock-cells = <0>;
 123                                                 compatible = "altr,socfpga-a10-pll-clock";
 124                                                 clocks = <&osc1>, <&cb_intosc_ls_clk>,
 125                                                          <&f2s_free_clk>;
 126                                                 reg = <0x40>;
 127
 128                                                 main_mpu_base_clk: main_mpu_base_clk {
 129                                                         #clock-cells = <0>;
 130                                                         compatible = "altr,socfpga-a10-perip-clk";
 131                                                         clocks = <&main_pll>;
 132                                                         div-reg = <0x140 0 11>;
 133                                                 };
 134
 135                                                 main_noc_base_clk: main_noc_base_clk {
 136                                                         #clock-cells = <0>;
 137                                                         compatible = "altr,socfpga-a10-perip-clk";
 138                                                         clocks = <&main_pll>;
 139                                                         div-reg = <0x144 0 11>;
 140                                                 };
 141
 142                                                 main_emaca_clk: main_emaca_clk@68 {
 143                                                         #clock-cells = <0>;
 144                                                         compatible = "altr,socfpga-a10-perip-clk";
 145                                                         clocks = <&main_pll>;
 146                                                         reg = <0x68>;
 147                                                 };
 148
 149                                                 main_emacb_clk: main_emacb_clk@6c {
 150                                                         #clock-cells = <0>;
 151                                                         compatible = "altr,socfpga-a10-perip-clk";
 152                                                         clocks = <&main_pll>;
 153                                                         reg = <0x6C>;
 154                                                 };
 155
 156                                                 main_emac_ptp_clk: main_emac_ptp_clk@70 {
 157                                                         #clock-cells = <0>;
 158                                                         compatible = "altr,socfpga-a10-perip-clk";
 159                                                         clocks = <&main_pll>;
 160                                                         reg = <0x70>;
 161                                                 };
 162
 163                                                 main_gpio_db_clk: main_gpio_db_clk@74 {
 164                                                         #clock-cells = <0>;
 165                                                         compatible = "altr,socfpga-a10-perip-clk";
 166                                                         clocks = <&main_pll>;
 167                                                         reg = <0x74>;
 168                                                 };
 169
 170                                                 main_sdmmc_clk: main_sdmmc_clk@78 {
 171                                                         #clock-cells = <0>;
 172                                                         compatible = "altr,socfpga-a10-perip-clk"
 173 ;
 174                                                         clocks = <&main_pll>;
 175                                                         reg = <0x78>;
 176                                                 };
 177
 178                                                 main_s2f_usr0_clk: main_s2f_usr0_clk@7c {
 179                                                         #clock-cells = <0>;
 180                                                         compatible = "altr,socfpga-a10-perip-clk";
 181                                                         clocks = <&main_pll>;
 182                                                         reg = <0x7C>;
 183                                                 };
 184
 185                                                 main_s2f_usr1_clk: main_s2f_usr1_clk@80 {
 186                                                         #clock-cells = <0>;
 187                                                         compatible = "altr,socfpga-a10-perip-clk";
 188                                                         clocks = <&main_pll>;
 189                                                         reg = <0x80>;
 190                                                 };
 191
 192                                                 main_hmc_pll_ref_clk: main_hmc_pll_ref_clk@84 {
 193                                                         #clock-cells = <0>;
 194                                                         compatible = "altr,socfpga-a10-perip-clk";
 195                                                         clocks = <&main_pll>;
 196                                                         reg = <0x84>;
 197                                                 };
 198
 199                                                 main_periph_ref_clk: main_periph_ref_clk@9c {
 200                                                         #clock-cells = <0>;
 201                                                         compatible = "altr,socfpga-a10-perip-clk";
 202                                                         clocks = <&main_pll>;
 203                                                         reg = <0x9C>;
 204                                                 };
 205                                         };
 206
 207                                         periph_pll: periph_pll@c0 {
 208                                                 #address-cells = <1>;
 209                                                 #size-cells = <0>;
 210                                                 #clock-cells = <0>;
 211                                                 compatible = "altr,socfpga-a10-pll-clock";
 212                                                 clocks = <&osc1>, <&cb_intosc_ls_clk>,
 213                                                          <&f2s_free_clk>, <&main_periph_ref_clk>;
 214                                                 reg = <0xC0>;
 215
 216                                                 peri_mpu_base_clk: peri_mpu_base_clk {
 217                                                         #clock-cells = <0>;
 218                                                         compatible = "altr,socfpga-a10-perip-clk";
 219                                                         clocks = <&periph_pll>;
 220                                                         div-reg = <0x140 16 11>;
 221                                                 };
 222
 223                                                 peri_noc_base_clk: peri_noc_base_clk {
 224                                                         #clock-cells = <0>;
 225                                                         compatible = "altr,socfpga-a10-perip-clk";
 226                                                         clocks = <&periph_pll>;
 227                                                         div-reg = <0x144 16 11>;
 228                                                 };
 229
 230                                                 peri_emaca_clk: peri_emaca_clk@e8 {
 231                                                         #clock-cells = <0>;
 232                                                         compatible = "altr,socfpga-a10-perip-clk";
 233                                                         clocks = <&periph_pll>;
 234                                                         reg = <0xE8>;
 235                                                 };
 236
 237                                                 peri_emacb_clk: peri_emacb_clk@ec {
 238                                                         #clock-cells = <0>;
 239                                                         compatible = "altr,socfpga-a10-perip-clk";
 240                                                         clocks = <&periph_pll>;
 241                                                         reg = <0xEC>;
 242                                                 };
 243
 244                                                 peri_emac_ptp_clk: peri_emac_ptp_clk@f0 {
 245                                                         #clock-cells = <0>;
 246                                                         compatible = "altr,socfpga-a10-perip-clk";
 247                                                         clocks = <&periph_pll>;
 248                                                         reg = <0xF0>;
 249                                                 };
 250
 251                                                 peri_gpio_db_clk: peri_gpio_db_clk@f4 {
 252                                                         #clock-cells = <0>;
 253                                                         compatible = "altr,socfpga-a10-perip-clk";
 254                                                         clocks = <&periph_pll>;
 255                                                         reg = <0xF4>;
 256                                                 };
 257
 258                                                 peri_sdmmc_clk: peri_sdmmc_clk@f8 {
 259                                                         #clock-cells = <0>;
 260                                                         compatible = "altr,socfpga-a10-perip-clk";
 261                                                         clocks = <&periph_pll>;
 262                                                         reg = <0xF8>;
 263                                                 };
 264
 265                                                 peri_s2f_usr0_clk: peri_s2f_usr0_clk@fc {
 266                                                         #clock-cells = <0>;
 267                                                         compatible = "altr,socfpga-a10-perip-clk";
 268                                                         clocks = <&periph_pll>;
 269                                                         reg = <0xFC>;
 270                                                 };
 271
 272                                                 peri_s2f_usr1_clk: peri_s2f_usr1_clk@100 {
 273                                                         #clock-cells = <0>;
 274                                                         compatible = "altr,socfpga-a10-perip-clk";
 275                                                         clocks = <&periph_pll>;
 276                                                         reg = <0x100>;
 277                                                 };
 278
 279                                                 peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk@104 {
 280                                                         #clock-cells = <0>;
 281                                                         compatible = "altr,socfpga-a10-perip-clk";
 282                                                         clocks = <&periph_pll>;
 283                                                         reg = <0x104>;
 284                                                 };
 285                                         };
 286
 287                                         mpu_free_clk: mpu_free_clk@60 {
 288                                                 #clock-cells = <0>;
 289                                                 compatible = "altr,socfpga-a10-perip-clk";
 290                                                 clocks = <&main_mpu_base_clk>, <&peri_mpu_base_clk>,
 291                                                          <&osc1>, <&cb_intosc_hs_div2_clk>,
 292                                                          <&f2s_free_clk>;
 293                                                 reg = <0x60>;
 294                                         };
 295
 296                                         noc_free_clk: noc_free_clk@64 {
 297                                                 #clock-cells = <0>;
 298                                                 compatible = "altr,socfpga-a10-perip-clk";
 299                                                 clocks = <&main_noc_base_clk>, <&peri_noc_base_clk>,
 300                                                          <&osc1>, <&cb_intosc_hs_div2_clk>,
 301                                                          <&f2s_free_clk>;
 302                                                 reg = <0x64>;
 303                                         };
 304
 305                                         s2f_user1_free_clk: s2f_user1_free_clk@104 {
 306                                                 #clock-cells = <0>;
 307                                                 compatible = "altr,socfpga-a10-perip-clk";
 308                                                 clocks = <&main_s2f_usr1_clk>, <&peri_s2f_usr1_clk>,
 309                                                          <&osc1>, <&cb_intosc_hs_div2_clk>,
 310                                                          <&f2s_free_clk>;
 311                                                 reg = <0x104>;
 312                                         };
 313
 314                                         sdmmc_free_clk: sdmmc_free_clk@f8 {
 315                                                 #clock-cells = <0>;
 316                                                 compatible = "altr,socfpga-a10-perip-clk";
 317                                                 clocks = <&main_sdmmc_clk>, <&peri_sdmmc_clk>,
 318                                                          <&osc1>, <&cb_intosc_hs_div2_clk>,
 319                                                          <&f2s_free_clk>;
 320                                                 fixed-divider = <4>;
 321                                                 reg = <0xF8>;
 322                                         };
 323
 324                                         l4_sys_free_clk: l4_sys_free_clk {
 325                                                 #clock-cells = <0>;
 326                                                 compatible = "altr,socfpga-a10-perip-clk";
 327                                                 clocks = <&noc_free_clk>;
 328                                                 fixed-divider = <4>;
 329                                         };
 330
 331                                         l4_main_clk: l4_main_clk {
 332                                                 #clock-cells = <0>;
 333                                                 compatible = "altr,socfpga-a10-gate-clk";
 334                                                 clocks = <&noc_free_clk>;
 335                                                 div-reg = <0xA8 0 2>;
 336                                                 clk-gate = <0x48 1>;
 337                                         };
 338
 339                                         l4_mp_clk: l4_mp_clk {
 340                                                 #clock-cells = <0>;
 341                                                 compatible = "altr,socfpga-a10-gate-clk";
 342                                                 clocks = <&noc_free_clk>;
 343                                                 div-reg = <0xA8 8 2>;
 344                                                 clk-gate = <0x48 2>;
 345                                         };
 346
 347                                         l4_sp_clk: l4_sp_clk {
 348                                                 #clock-cells = <0>;
 349                                                 compatible = "altr,socfpga-a10-gate-clk";
 350                                                 clocks = <&noc_free_clk>;
 351                                                 div-reg = <0xA8 16 2>;
 352                                                 clk-gate = <0x48 3>;
 353                                         };
 354
 355                                         mpu_periph_clk: mpu_periph_clk {
 356                                                 #clock-cells = <0>;
 357                                                 compatible = "altr,socfpga-a10-gate-clk";
 358                                                 clocks = <&mpu_free_clk>;
 359                                                 fixed-divider = <4>;
 360                                                 clk-gate = <0x48 0>;
 361                                         };
 362
 363                                         sdmmc_clk: sdmmc_clk {
 364                                                 #clock-cells = <0>;
 365                                                 compatible = "altr,socfpga-a10-gate-clk";
 366                                                 clocks = <&sdmmc_free_clk>;
 367                                                 clk-gate = <0xC8 5>;
 368                                                 clk-phase = <0 135>;
 369                                         };
 370
 371                                         qspi_clk: qspi_clk {
 372                                                 #clock-cells = <0>;
 373                                                 compatible = "altr,socfpga-a10-gate-clk";
 374                                                 clocks = <&l4_main_clk>;
 375                                                 clk-gate = <0xC8 11>;
 376                                         };
 377
 378                                         nand_x_clk: nand_x_clk {
 379                                                 #clock-cells = <0>;
 380                                                 compatible = "altr,socfpga-a10-gate-clk";
 381                                                 clocks = <&l4_mp_clk>;
 382                                                 clk-gate = <0xC8 10>;
 383                                         };
 384
 385                                         nand_ecc_clk: nand_ecc_clk {
 386                                                 #clock-cells = <0>;
 387                                                 compatible = "altr,socfpga-a10-gate-clk";
 388                                                 clocks = <&nand_x_clk>;
 389                                                 clk-gate = <0xC8 10>;
 390                                         };
 391
 392                                         nand_clk: nand_clk {
 393                                                 #clock-cells = <0>;
 394                                                 compatible = "altr,socfpga-a10-gate-clk";
 395                                                 clocks = <&nand_x_clk>;
 396                                                 fixed-divider = <4>;
 397                                                 clk-gate = <0xC8 10>;
 398                                         };
 399
 400                                         spi_m_clk: spi_m_clk {
 401                                                 #clock-cells = <0>;
 402                                                 compatible = "altr,socfpga-a10-gate-clk";
 403                                                 clocks = <&l4_main_clk>;
 404                                                 clk-gate = <0xC8 9>;
 405                                         };
 406
 407                                         usb_clk: usb_clk {
 408                                                 #clock-cells = <0>;
 409                                                 compatible = "altr,socfpga-a10-gate-clk";
 410                                                 clocks = <&l4_mp_clk>;
 411                                                 clk-gate = <0xC8 8>;
 412                                         };
 413
 414                                         s2f_usr1_clk: s2f_usr1_clk {
 415                                                 #clock-cells = <0>;
 416                                                 compatible = "altr,socfpga-a10-gate-clk";
 417                                                 clocks = <&peri_s2f_usr1_clk>;
 418                                                 clk-gate = <0xC8 6>;
 419                                         };
 420                                 };
 421                 };
 422
 423                 socfpga_axi_setup: stmmac-axi-config {
 424                         snps,wr_osr_lmt = <0xf>;
 425                         snps,rd_osr_lmt = <0xf>;
 426                         snps,blen = <0 0 0 0 16 0 0>;
 427                 };
 428
 429                 gmac0: ethernet@ff800000 {
 430                         compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";
 431                         altr,sysmgr-syscon = <&sysmgr 0x44 0>;
 432                         reg = <0xff800000 0x2000>;
 433                         interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
 434                         interrupt-names = "macirq";
 435                         /* Filled in by bootloader */
 436                         mac-address = [00 00 00 00 00 00];
 437                         snps,multicast-filter-bins = <256>;
 438                         snps,perfect-filter-entries = <128>;
 439                         tx-fifo-depth = <4096>;
 440                         rx-fifo-depth = <16384>;
 441                         clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>;
 442                         clock-names = "stmmaceth", "ptp_ref";
 443                         resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
 444                         reset-names = "stmmaceth", "stmmaceth-ocp";
 445                         snps,axi-config = <&socfpga_axi_setup>;
 446                         status = "disabled";
 447                 };
 448
 449                 gmac1: ethernet@ff802000 {
 450                         compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";
 451                         altr,sysmgr-syscon = <&sysmgr 0x48 8>;
 452                         reg = <0xff802000 0x2000>;
 453                         interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
 454                         interrupt-names = "macirq";
 455                         /* Filled in by bootloader */
 456                         mac-address = [00 00 00 00 00 00];
 457                         snps,multicast-filter-bins = <256>;
 458                         snps,perfect-filter-entries = <128>;
 459                         tx-fifo-depth = <4096>;
 460                         rx-fifo-depth = <16384>;
 461                         clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>;
 462                         clock-names = "stmmaceth", "ptp_ref";
 463                         resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
 464                         reset-names = "stmmaceth", "stmmaceth-ocp";
 465                         snps,axi-config = <&socfpga_axi_setup>;
 466                         status = "disabled";
 467                 };
 468
 469                 gmac2: ethernet@ff804000 {
 470                         compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";
 471                         altr,sysmgr-syscon = <&sysmgr 0x4C 16>;
 472                         reg = <0xff804000 0x2000>;
 473                         interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
 474                         interrupt-names = "macirq";
 475                         /* Filled in by bootloader */
 476                         mac-address = [00 00 00 00 00 00];
 477                         snps,multicast-filter-bins = <256>;
 478                         snps,perfect-filter-entries = <128>;
 479                         tx-fifo-depth = <4096>;
 480                         rx-fifo-depth = <16384>;
 481                         clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>;
 482                         clock-names = "stmmaceth", "ptp_ref";
 483                         resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
 484                         reset-names = "stmmaceth", "stmmaceth-ocp";
 485                         snps,axi-config = <&socfpga_axi_setup>;
 486                         status = "disabled";
 487                 };
 488
 489                 gpio0: gpio@ffc02900 {
 490                         #address-cells = <1>;
 491                         #size-cells = <0>;
 492                         compatible = "snps,dw-apb-gpio";
 493                         reg = <0xffc02900 0x100>;
 494                         resets = <&rst GPIO0_RESET>;
 495                         status = "disabled";
 496
 497                         porta: gpio-controller@0 {
 498                                 compatible = "snps,dw-apb-gpio-port";
 499                                 gpio-controller;
 500                                 #gpio-cells = <2>;
 501                                 snps,nr-gpios = <29>;
 502                                 reg = <0>;
 503                                 interrupt-controller;
 504                                 #interrupt-cells = <2>;
 505                                 interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
 506                         };
 507                 };
 508
 509                 gpio1: gpio@ffc02a00 {
 510                         #address-cells = <1>;
 511                         #size-cells = <0>;
 512                         compatible = "snps,dw-apb-gpio";
 513                         reg = <0xffc02a00 0x100>;
 514                         resets = <&rst GPIO1_RESET>;
 515                         status = "disabled";
 516
 517                         portb: gpio-controller@0 {
 518                                 compatible = "snps,dw-apb-gpio-port";
 519                                 gpio-controller;
 520                                 #gpio-cells = <2>;
 521                                 snps,nr-gpios = <29>;
 522                                 reg = <0>;
 523                                 interrupt-controller;
 524                                 #interrupt-cells = <2>;
 525                                 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
 526                         };
 527                 };
 528
 529                 gpio2: gpio@ffc02b00 {
 530                         #address-cells = <1>;
 531                         #size-cells = <0>;
 532                         compatible = "snps,dw-apb-gpio";
 533                         reg = <0xffc02b00 0x100>;
 534                         resets = <&rst GPIO2_RESET>;
 535                         status = "disabled";
 536
 537                         portc: gpio-controller@0 {
 538                                 compatible = "snps,dw-apb-gpio-port";
 539                                 gpio-controller;
 540                                 #gpio-cells = <2>;
 541                                 snps,nr-gpios = <27>;
 542                                 reg = <0>;
 543                                 interrupt-controller;
 544                                 #interrupt-cells = <2>;
 545                                 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
 546                         };
 547                 };
 548
 549                 fpga_mgr: fpga-mgr@ffd03000 {
 550                         compatible = "altr,socfpga-a10-fpga-mgr";
 551                         reg = <0xffd03000 0x100
 552                                0xffcfe400 0x20>;
 553                         clocks = <&l4_mp_clk>;
 554                         resets = <&rst FPGAMGR_RESET>;
 555                         reset-names = "fpgamgr";
 556                 };
 557
 558                 i2c0: i2c@ffc02200 {
 559                         #address-cells = <1>;
 560                         #size-cells = <0>;
 561                         compatible = "snps,designware-i2c";
 562                         reg = <0xffc02200 0x100>;
 563                         interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
 564                         clocks = <&l4_sp_clk>;
 565                         resets = <&rst I2C0_RESET>;
 566                         status = "disabled";
 567                 };
 568
 569                 i2c1: i2c@ffc02300 {
 570                         #address-cells = <1>;
 571                         #size-cells = <0>;
 572                         compatible = "snps,designware-i2c";
 573                         reg = <0xffc02300 0x100>;
 574                         interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
 575                         clocks = <&l4_sp_clk>;
 576                         resets = <&rst I2C1_RESET>;
 577                         status = "disabled";
 578                 };
 579
 580                 i2c2: i2c@ffc02400 {
 581                         #address-cells = <1>;
 582                         #size-cells = <0>;
 583                         compatible = "snps,designware-i2c";
 584                         reg = <0xffc02400 0x100>;
 585                         interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
 586                         clocks = <&l4_sp_clk>;
 587                         resets = <&rst I2C2_RESET>;
 588                         status = "disabled";
 589                 };
 590
 591                 i2c3: i2c@ffc02500 {
 592                         #address-cells = <1>;
 593                         #size-cells = <0>;
 594                         compatible = "snps,designware-i2c";
 595                         reg = <0xffc02500 0x100>;
 596                         interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
 597                         clocks = <&l4_sp_clk>;
 598                         resets = <&rst I2C3_RESET>;
 599                         status = "disabled";
 600                 };
 601
 602                 i2c4: i2c@ffc02600 {
 603                         #address-cells = <1>;
 604                         #size-cells = <0>;
 605                         compatible = "snps,designware-i2c";
 606                         reg = <0xffc02600 0x100>;
 607                         interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
 608                         clocks = <&l4_sp_clk>;
 609                         resets = <&rst I2C4_RESET>;
 610                         status = "disabled";
 611                 };
 612
 613                 spi0: spi@ffda4000 {
 614                         compatible = "snps,dw-apb-ssi";
 615                         #address-cells = <1>;
 616                         #size-cells = <0>;
 617                         reg = <0xffda4000 0x100>;
 618                         interrupts = <0 101 4>;
 619                         num-cs = <4>;
 620                         /*32bit_access;*/
 621                         clocks = <&spi_m_clk>;
 622                         resets = <&rst SPIM0_RESET>;
 623                         reset-names = "spi";
 624                         status = "disabled";
 625                 };
 626
 627                 spi1: spi@ffda5000 {
 628                         compatible = "snps,dw-apb-ssi";
 629                         #address-cells = <1>;
 630                         #size-cells = <0>;
 631                         reg = <0xffda5000 0x100>;
 632                         interrupts = <0 102 4>;
 633                         num-cs = <4>;
 634                         /*32bit_access;*/
 635                         tx-dma-channel = <&pdma 16>;
 636                         rx-dma-channel = <&pdma 17>;
 637                         clocks = <&spi_m_clk>;
 638                         resets = <&rst SPIM1_RESET>;
 639                         reset-names = "spi";
 640                         status = "disabled";
 641                 };
 642
 643                 sdr: sdr@ffcfb100 {
 644                         compatible = "altr,sdr-ctl", "syscon";
 645                         reg = <0xffcfb100 0x80>;
 646                 };
 647
 648                 L2: cache-controller@fffff000 {
 649                         compatible = "arm,pl310-cache";
 650                         reg = <0xfffff000 0x1000>;
 651                         interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
 652                         cache-unified;
 653                         cache-level = <2>;
 654                         prefetch-data = <1>;
 655                         prefetch-instr = <1>;
 656                         arm,shared-override;
 657                 };
 658
 659                 mmc: dwmmc0@ff808000 {
 660                         #address-cells = <1>;
 661                         #size-cells = <0>;
 662                         compatible = "altr,socfpga-dw-mshc";
 663                         reg = <0xff808000 0x1000>;
 664                         interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
 665                         fifo-depth = <0x400>;
 666                         clocks = <&l4_mp_clk>, <&sdmmc_clk>;
 667                         clock-names = "biu", "ciu";
 668                         resets = <&rst SDMMC_RESET>;
 669                         status = "disabled";
 670                 };
 671
 672                 nand: nand@ffb90000 {
 673                         #address-cells = <1>;
 674                         #size-cells = <0>;
 675                         compatible = "altr,socfpga-denali-nand";
 676                         reg = <0xffb90000 0x72000>,
 677                               <0xffb80000 0x10000>;
 678                         reg-names = "nand_data", "denali_reg";
 679                         interrupts = <0 99 4>;
 680                         clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;
 681                         clock-names = "nand", "nand_x", "ecc";
 682                         resets = <&rst NAND_RESET>;
 683                         status = "disabled";
 684                 };
 685
 686                 ocram: sram@ffe00000 {
 687                         compatible = "mmio-sram";
 688                         reg = <0xffe00000 0x40000>;
 689                 };
 690
 691                 eccmgr: eccmgr {
 692                         compatible = "altr,socfpga-a10-ecc-manager";
 693                         altr,sysmgr-syscon = <&sysmgr>;
 694                         #address-cells = <1>;
 695                         #size-cells = <1>;
 696                         interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,
 697                                      <0 0 IRQ_TYPE_LEVEL_HIGH>;
 698                         interrupt-controller;
 699                         #interrupt-cells = <2>;
 700                         ranges;
 701
 702                         sdramedac {
 703                                 compatible = "altr,sdram-edac-a10";
 704                                 altr,sdr-syscon = <&sdr>;
 705                                 interrupts = <17 IRQ_TYPE_LEVEL_HIGH>,
 706                                              <49 IRQ_TYPE_LEVEL_HIGH>;
 707                         };
 708
 709                         l2-ecc@ffd06010 {
 710                                 compatible = "altr,socfpga-a10-l2-ecc";
 711                                 reg = <0xffd06010 0x4>;
 712                                 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>,
 713                                              <32 IRQ_TYPE_LEVEL_HIGH>;
 714                         };
 715
 716                         ocram-ecc@ff8c3000 {
 717                                 compatible = "altr,socfpga-a10-ocram-ecc";
 718                                 reg = <0xff8c3000 0x400>;
 719                                 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>,
 720                                              <33 IRQ_TYPE_LEVEL_HIGH>;
 721                         };
 722
 723                         emac0-rx-ecc@ff8c0800 {
 724                                 compatible = "altr,socfpga-eth-mac-ecc";
 725                                 reg = <0xff8c0800 0x400>;
 726                                 altr,ecc-parent = <&gmac0>;
 727                                 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>,
 728                                              <36 IRQ_TYPE_LEVEL_HIGH>;
 729                         };
 730
 731                         emac0-tx-ecc@ff8c0c00 {
 732                                 compatible = "altr,socfpga-eth-mac-ecc";
 733                                 reg = <0xff8c0c00 0x400>;
 734                                 altr,ecc-parent = <&gmac0>;
 735                                 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>,
 736                                              <37 IRQ_TYPE_LEVEL_HIGH>;
 737                         };
 738
 739                         sdmmca-ecc@ff8c2c00 {
 740                                 compatible = "altr,socfpga-sdmmc-ecc";
 741                                 reg = <0xff8c2c00 0x400>;
 742                                 altr,ecc-parent = <&mmc>;
 743                                 interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
 744                                              <47 IRQ_TYPE_LEVEL_HIGH>,
 745                                              <16 IRQ_TYPE_LEVEL_HIGH>,
 746                                              <48 IRQ_TYPE_LEVEL_HIGH>;
 747                         };
 748
 749                         dma-ecc@ff8c8000 {
 750                                 compatible = "altr,socfpga-dma-ecc";
 751                                 reg = <0xff8c8000 0x400>;
 752                                 altr,ecc-parent = <&pdma>;
 753                                 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
 754                                              <42 IRQ_TYPE_LEVEL_HIGH>;
 755                         };
 756
 757                         usb0-ecc@ff8c8800 {
 758                                 compatible = "altr,socfpga-usb-ecc";
 759                                 reg = <0xff8c8800 0x400>;
 760                                 altr,ecc-parent = <&usb0>;
 761                                 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>,
 762                                              <34 IRQ_TYPE_LEVEL_HIGH>;
 763                         };
 764                 };
 765
 766                 qspi: spi@ff809000 {
 767                         compatible = "intel,socfpga-qspi", "cdns,qspi-nor";
 768                         #address-cells = <1>;
 769                         #size-cells = <0>;
 770                         reg = <0xff809000 0x100>,
 771                               <0xffa00000 0x100000>;
 772                         interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
 773                         cdns,fifo-depth = <128>;
 774                         cdns,fifo-width = <4>;
 775                         cdns,trigger-address = <0x00000000>;
 776                         clocks = <&qspi_clk>;
 777                         resets = <&rst QSPI_RESET>, <&rst QSPI_OCP_RESET>;
 778                         reset-names = "qspi", "qspi-ocp";
 779                         status = "disabled";
 780                 };
 781
 782                 rst: rstmgr@ffd05000 {
 783                         #reset-cells = <1>;
 784                         compatible = "altr,rst-mgr";
 785                         reg = <0xffd05000 0x100>;
 786                         altr,modrst-offset = <0x20>;
 787                 };
 788
 789                 scu: snoop-control-unit@ffffc000 {
 790                         compatible = "arm,cortex-a9-scu";
 791                         reg = <0xffffc000 0x100>;
 792                 };
 793
 794                 sysmgr: sysmgr@ffd06000 {
 795                         compatible = "altr,sys-mgr", "syscon";
 796                         reg = <0xffd06000 0x300>;
 797                         cpu1-start-addr = <0xffd06230>;
 798                 };
 799
 800                 /* Local timer */
 801                 timer@ffffc600 {
 802                         compatible = "arm,cortex-a9-twd-timer";
 803                         reg = <0xffffc600 0x100>;
 804                         interrupts = <1 13 0xf01>;
 805                         clocks = <&mpu_periph_clk>;
 806                 };
 807
 808                 timer0: timer0@ffc02700 {
 809                         compatible = "snps,dw-apb-timer";
 810                         interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>;
 811                         reg = <0xffc02700 0x100>;
 812                         clocks = <&l4_sp_clk>;
 813                         clock-names = "timer";
 814                         resets = <&rst SPTIMER0_RESET>;
 815                         reset-names = "timer";
 816                 };
 817
 818                 timer1: timer1@ffc02800 {
 819                         compatible = "snps,dw-apb-timer";
 820                         interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>;
 821                         reg = <0xffc02800 0x100>;
 822                         clocks = <&l4_sp_clk>;
 823                         clock-names = "timer";
 824                         resets = <&rst SPTIMER1_RESET>;
 825                         reset-names = "timer";
 826                 };
 827
 828                 timer2: timer2@ffd00000 {
 829                         compatible = "snps,dw-apb-timer";
 830                         interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>;
 831                         reg = <0xffd00000 0x100>;
 832                         clocks = <&l4_sys_free_clk>;
 833                         clock-names = "timer";
 834                         resets = <&rst L4SYSTIMER0_RESET>;
 835                         reset-names = "timer";
 836                 };
 837
 838                 timer3: timer3@ffd00100 {
 839                         compatible = "snps,dw-apb-timer";
 840                         interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>;
 841                         reg = <0xffd00100 0x100>;
 842                         clocks = <&l4_sys_free_clk>;
 843                         clock-names = "timer";
 844                         resets = <&rst L4SYSTIMER1_RESET>;
 845                         reset-names = "timer";
 846                 };
 847
 848                 uart0: serial0@ffc02000 {
 849                         compatible = "snps,dw-apb-uart";
 850                         reg = <0xffc02000 0x100>;
 851                         interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
 852                         reg-shift = <2>;
 853                         reg-io-width = <4>;
 854                         clocks = <&l4_sp_clk>;
 855                         resets = <&rst UART0_RESET>;
 856                         status = "disabled";
 857                 };
 858
 859                 uart1: serial1@ffc02100 {
 860                         compatible = "snps,dw-apb-uart";
 861                         reg = <0xffc02100 0x100>;
 862                         interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
 863                         reg-shift = <2>;
 864                         reg-io-width = <4>;
 865                         clocks = <&l4_sp_clk>;
 866                         resets = <&rst UART1_RESET>;
 867                         status = "disabled";
 868                 };
 869
 870                 usbphy0: usbphy {
 871                         #phy-cells = <0>;
 872                         compatible = "usb-nop-xceiv";
 873                         status = "okay";
 874                 };
 875
 876                 usb0: usb@ffb00000 {
 877                         compatible = "snps,dwc2";
 878                         reg = <0xffb00000 0xffff>;
 879                         interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
 880                         clocks = <&usb_clk>;
 881                         clock-names = "otg";
 882                         resets = <&rst USB0_RESET>;
 883                         reset-names = "dwc2";
 884                         phys = <&usbphy0>;
 885                         phy-names = "usb2-phy";
 886                         status = "disabled";
 887                 };
 888
 889                 usb1: usb@ffb40000 {
 890                         compatible = "snps,dwc2";
 891                         reg = <0xffb40000 0xffff>;
 892                         interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
 893                         clocks = <&usb_clk>;
 894                         clock-names = "otg";
 895                         resets = <&rst USB1_RESET>;
 896                         reset-names = "dwc2";
 897                         phys = <&usbphy0>;
 898                         phy-names = "usb2-phy";
 899                         status = "disabled";
 900                 };
 901
 902                 watchdog0: watchdog@ffd00200 {
 903                         compatible = "snps,dw-wdt";
 904                         reg = <0xffd00200 0x100>;
 905                         interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
 906                         clocks = <&l4_sys_free_clk>;
 907                         resets = <&rst L4WD0_RESET>;
 908                         status = "disabled";
 909                 };
 910
 911                 watchdog1: watchdog@ffd00300 {
 912                         compatible = "snps,dw-wdt";
 913                         reg = <0xffd00300 0x100>;
 914                         interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
 915                         clocks = <&l4_sys_free_clk>;
 916                         resets = <&rst L4WD1_RESET>;
 917                         status = "disabled";
 918                 };
 919         };
 920 };