1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2012 Altera <www.altera.com>
6 #include <dt-bindings/reset/altr,rst-mgr.h>
24 enable-method = "altr,socfpga-smp";
27 compatible = "arm,cortex-a9";
30 next-level-cache = <&L2>;
33 compatible = "arm,cortex-a9";
36 next-level-cache = <&L2>;
41 compatible = "arm,cortex-a9-pmu";
42 interrupt-parent = <&intc>;
43 interrupts = <0 176 4>, <0 177 4>;
44 interrupt-affinity = <&cpu0>, <&cpu1>;
45 reg = <0xff111000 0x1000>,
49 intc: interrupt-controller@fffed000 {
50 compatible = "arm,cortex-a9-gic";
51 #interrupt-cells = <3>;
53 reg = <0xfffed000 0x1000>,
60 compatible = "simple-bus";
62 interrupt-parent = <&intc>;
66 compatible = "simple-bus";
72 compatible = "arm,pl330", "arm,primecell";
73 reg = <0xffe01000 0x1000>;
74 interrupts = <0 104 4>,
83 clocks = <&l4_main_clk>;
84 clock-names = "apb_pclk";
85 resets = <&rst DMA_RESET>;
91 compatible = "fpga-region";
92 fpga-mgr = <&fpgamgr0>;
94 #address-cells = <0x1>;
99 compatible = "bosch,d_can";
100 reg = <0xffc00000 0x1000>;
101 interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>;
102 clocks = <&can0_clk>;
103 resets = <&rst CAN0_RESET>;
108 compatible = "bosch,d_can";
109 reg = <0xffc01000 0x1000>;
110 interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>;
111 clocks = <&can1_clk>;
112 resets = <&rst CAN1_RESET>;
117 compatible = "altr,clk-mgr";
118 reg = <0xffd04000 0x1000>;
121 #address-cells = <1>;
126 compatible = "fixed-clock";
131 compatible = "fixed-clock";
134 f2s_periph_ref_clk: f2s_periph_ref_clk {
136 compatible = "fixed-clock";
139 f2s_sdram_ref_clk: f2s_sdram_ref_clk {
141 compatible = "fixed-clock";
144 main_pll: main_pll@40 {
145 #address-cells = <1>;
148 compatible = "altr,socfpga-pll-clock";
154 compatible = "altr,socfpga-perip-clk";
155 clocks = <&main_pll>;
156 div-reg = <0xe0 0 9>;
160 mainclk: mainclk@4c {
162 compatible = "altr,socfpga-perip-clk";
163 clocks = <&main_pll>;
164 div-reg = <0xe4 0 9>;
168 dbg_base_clk: dbg_base_clk@50 {
170 compatible = "altr,socfpga-perip-clk";
171 clocks = <&main_pll>, <&osc1>;
172 div-reg = <0xe8 0 9>;
176 main_qspi_clk: main_qspi_clk@54 {
178 compatible = "altr,socfpga-perip-clk";
179 clocks = <&main_pll>;
183 main_nand_sdmmc_clk: main_nand_sdmmc_clk@58 {
185 compatible = "altr,socfpga-perip-clk";
186 clocks = <&main_pll>;
190 cfg_h2f_usr0_clk: cfg_h2f_usr0_clk@5c {
192 compatible = "altr,socfpga-perip-clk";
193 clocks = <&main_pll>;
198 periph_pll: periph_pll@80 {
199 #address-cells = <1>;
202 compatible = "altr,socfpga-pll-clock";
203 clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>;
206 emac0_clk: emac0_clk@88 {
208 compatible = "altr,socfpga-perip-clk";
209 clocks = <&periph_pll>;
213 emac1_clk: emac1_clk@8c {
215 compatible = "altr,socfpga-perip-clk";
216 clocks = <&periph_pll>;
220 per_qspi_clk: per_qsi_clk@90 {
222 compatible = "altr,socfpga-perip-clk";
223 clocks = <&periph_pll>;
227 per_nand_mmc_clk: per_nand_mmc_clk@94 {
229 compatible = "altr,socfpga-perip-clk";
230 clocks = <&periph_pll>;
234 per_base_clk: per_base_clk@98 {
236 compatible = "altr,socfpga-perip-clk";
237 clocks = <&periph_pll>;
241 h2f_usr1_clk: h2f_usr1_clk@9c {
243 compatible = "altr,socfpga-perip-clk";
244 clocks = <&periph_pll>;
249 sdram_pll: sdram_pll@c0 {
250 #address-cells = <1>;
253 compatible = "altr,socfpga-pll-clock";
254 clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>;
257 ddr_dqs_clk: ddr_dqs_clk@c8 {
259 compatible = "altr,socfpga-perip-clk";
260 clocks = <&sdram_pll>;
264 ddr_2x_dqs_clk: ddr_2x_dqs_clk@cc {
266 compatible = "altr,socfpga-perip-clk";
267 clocks = <&sdram_pll>;
271 ddr_dq_clk: ddr_dq_clk@d0 {
273 compatible = "altr,socfpga-perip-clk";
274 clocks = <&sdram_pll>;
278 h2f_usr2_clk: h2f_usr2_clk@d4 {
280 compatible = "altr,socfpga-perip-clk";
281 clocks = <&sdram_pll>;
286 mpu_periph_clk: mpu_periph_clk {
288 compatible = "altr,socfpga-perip-clk";
293 mpu_l2_ram_clk: mpu_l2_ram_clk {
295 compatible = "altr,socfpga-perip-clk";
300 l4_main_clk: l4_main_clk {
302 compatible = "altr,socfpga-gate-clk";
307 l3_main_clk: l3_main_clk {
309 compatible = "altr,socfpga-perip-clk";
314 l3_mp_clk: l3_mp_clk {
316 compatible = "altr,socfpga-gate-clk";
318 div-reg = <0x64 0 2>;
322 l3_sp_clk: l3_sp_clk {
324 compatible = "altr,socfpga-gate-clk";
325 clocks = <&l3_mp_clk>;
326 div-reg = <0x64 2 2>;
329 l4_mp_clk: l4_mp_clk {
331 compatible = "altr,socfpga-gate-clk";
332 clocks = <&mainclk>, <&per_base_clk>;
333 div-reg = <0x64 4 3>;
337 l4_sp_clk: l4_sp_clk {
339 compatible = "altr,socfpga-gate-clk";
340 clocks = <&mainclk>, <&per_base_clk>;
341 div-reg = <0x64 7 3>;
345 dbg_at_clk: dbg_at_clk {
347 compatible = "altr,socfpga-gate-clk";
348 clocks = <&dbg_base_clk>;
349 div-reg = <0x68 0 2>;
355 compatible = "altr,socfpga-gate-clk";
356 clocks = <&dbg_at_clk>;
357 div-reg = <0x68 2 2>;
361 dbg_trace_clk: dbg_trace_clk {
363 compatible = "altr,socfpga-gate-clk";
364 clocks = <&dbg_base_clk>;
365 div-reg = <0x6C 0 3>;
369 dbg_timer_clk: dbg_timer_clk {
371 compatible = "altr,socfpga-gate-clk";
372 clocks = <&dbg_base_clk>;
378 compatible = "altr,socfpga-gate-clk";
379 clocks = <&cfg_h2f_usr0_clk>;
383 h2f_user0_clk: h2f_user0_clk {
385 compatible = "altr,socfpga-gate-clk";
386 clocks = <&cfg_h2f_usr0_clk>;
390 emac_0_clk: emac_0_clk {
392 compatible = "altr,socfpga-gate-clk";
393 clocks = <&emac0_clk>;
397 emac_1_clk: emac_1_clk {
399 compatible = "altr,socfpga-gate-clk";
400 clocks = <&emac1_clk>;
404 usb_mp_clk: usb_mp_clk {
406 compatible = "altr,socfpga-gate-clk";
407 clocks = <&per_base_clk>;
409 div-reg = <0xa4 0 3>;
412 spi_m_clk: spi_m_clk {
414 compatible = "altr,socfpga-gate-clk";
415 clocks = <&per_base_clk>;
417 div-reg = <0xa4 3 3>;
422 compatible = "altr,socfpga-gate-clk";
423 clocks = <&per_base_clk>;
425 div-reg = <0xa4 6 3>;
430 compatible = "altr,socfpga-gate-clk";
431 clocks = <&per_base_clk>;
433 div-reg = <0xa4 9 3>;
436 gpio_db_clk: gpio_db_clk {
438 compatible = "altr,socfpga-gate-clk";
439 clocks = <&per_base_clk>;
441 div-reg = <0xa8 0 24>;
444 h2f_user1_clk: h2f_user1_clk {
446 compatible = "altr,socfpga-gate-clk";
447 clocks = <&h2f_usr1_clk>;
451 sdmmc_clk: sdmmc_clk {
453 compatible = "altr,socfpga-gate-clk";
454 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
459 sdmmc_clk_divided: sdmmc_clk_divided {
461 compatible = "altr,socfpga-gate-clk";
462 clocks = <&sdmmc_clk>;
467 nand_x_clk: nand_x_clk {
469 compatible = "altr,socfpga-gate-clk";
470 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
474 nand_ecc_clk: nand_ecc_clk {
476 compatible = "altr,socfpga-gate-clk";
477 clocks = <&nand_x_clk>;
483 compatible = "altr,socfpga-gate-clk";
484 clocks = <&nand_x_clk>;
485 clk-gate = <0xa0 10>;
491 compatible = "altr,socfpga-gate-clk";
492 clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;
493 clk-gate = <0xa0 11>;
496 ddr_dqs_clk_gate: ddr_dqs_clk_gate {
498 compatible = "altr,socfpga-gate-clk";
499 clocks = <&ddr_dqs_clk>;
503 ddr_2x_dqs_clk_gate: ddr_2x_dqs_clk_gate {
505 compatible = "altr,socfpga-gate-clk";
506 clocks = <&ddr_2x_dqs_clk>;
510 ddr_dq_clk_gate: ddr_dq_clk_gate {
512 compatible = "altr,socfpga-gate-clk";
513 clocks = <&ddr_dq_clk>;
517 h2f_user2_clk: h2f_user2_clk {
519 compatible = "altr,socfpga-gate-clk";
520 clocks = <&h2f_usr2_clk>;
527 fpga_bridge0: fpga_bridge@ff400000 {
528 compatible = "altr,socfpga-lwhps2fpga-bridge";
529 reg = <0xff400000 0x100000>;
530 resets = <&rst LWHPS2FPGA_RESET>;
531 clocks = <&l4_main_clk>;
535 fpga_bridge1: fpga_bridge@ff500000 {
536 compatible = "altr,socfpga-hps2fpga-bridge";
537 reg = <0xff500000 0x10000>;
538 resets = <&rst HPS2FPGA_RESET>;
539 clocks = <&l4_main_clk>;
543 fpga_bridge2: fpga-bridge@ff600000 {
544 compatible = "altr,socfpga-fpga2hps-bridge";
545 reg = <0xff600000 0x100000>;
546 resets = <&rst FPGA2HPS_RESET>;
547 clocks = <&l4_main_clk>;
551 fpga_bridge3: fpga-bridge@ffc25080 {
552 compatible = "altr,socfpga-fpga2sdram-bridge";
553 reg = <0xffc25080 0x4>;
557 fpgamgr0: fpgamgr@ff706000 {
558 compatible = "altr,socfpga-fpga-mgr";
559 reg = <0xff706000 0x1000
561 interrupts = <0 175 4>;
564 socfpga_axi_setup: stmmac-axi-config {
565 snps,wr_osr_lmt = <0xf>;
566 snps,rd_osr_lmt = <0xf>;
567 snps,blen = <0 0 0 0 16 0 0>;
570 gmac0: ethernet@ff700000 {
571 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
572 altr,sysmgr-syscon = <&sysmgr 0x60 0>;
573 reg = <0xff700000 0x2000>;
574 interrupts = <0 115 4>;
575 interrupt-names = "macirq";
576 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
577 clocks = <&emac_0_clk>;
578 clock-names = "stmmaceth";
579 resets = <&rst EMAC0_RESET>;
580 reset-names = "stmmaceth";
581 snps,multicast-filter-bins = <256>;
582 snps,perfect-filter-entries = <128>;
583 tx-fifo-depth = <4096>;
584 rx-fifo-depth = <4096>;
585 snps,axi-config = <&socfpga_axi_setup>;
589 gmac1: ethernet@ff702000 {
590 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
591 altr,sysmgr-syscon = <&sysmgr 0x60 2>;
592 reg = <0xff702000 0x2000>;
593 interrupts = <0 120 4>;
594 interrupt-names = "macirq";
595 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
596 clocks = <&emac_1_clk>;
597 clock-names = "stmmaceth";
598 resets = <&rst EMAC1_RESET>;
599 reset-names = "stmmaceth";
600 snps,multicast-filter-bins = <256>;
601 snps,perfect-filter-entries = <128>;
602 tx-fifo-depth = <4096>;
603 rx-fifo-depth = <4096>;
604 snps,axi-config = <&socfpga_axi_setup>;
608 gpio0: gpio@ff708000 {
609 #address-cells = <1>;
611 compatible = "snps,dw-apb-gpio";
612 reg = <0xff708000 0x1000>;
613 clocks = <&l4_mp_clk>;
614 resets = <&rst GPIO0_RESET>;
617 porta: gpio-controller@0 {
618 compatible = "snps,dw-apb-gpio-port";
621 snps,nr-gpios = <29>;
623 interrupt-controller;
624 #interrupt-cells = <2>;
625 interrupts = <0 164 4>;
629 gpio1: gpio@ff709000 {
630 #address-cells = <1>;
632 compatible = "snps,dw-apb-gpio";
633 reg = <0xff709000 0x1000>;
634 clocks = <&l4_mp_clk>;
635 resets = <&rst GPIO1_RESET>;
638 portb: gpio-controller@0 {
639 compatible = "snps,dw-apb-gpio-port";
642 snps,nr-gpios = <29>;
644 interrupt-controller;
645 #interrupt-cells = <2>;
646 interrupts = <0 165 4>;
650 gpio2: gpio@ff70a000 {
651 #address-cells = <1>;
653 compatible = "snps,dw-apb-gpio";
654 reg = <0xff70a000 0x1000>;
655 clocks = <&l4_mp_clk>;
656 resets = <&rst GPIO2_RESET>;
659 portc: gpio-controller@0 {
660 compatible = "snps,dw-apb-gpio-port";
663 snps,nr-gpios = <27>;
665 interrupt-controller;
666 #interrupt-cells = <2>;
667 interrupts = <0 166 4>;
672 #address-cells = <1>;
674 compatible = "snps,designware-i2c";
675 reg = <0xffc04000 0x1000>;
676 resets = <&rst I2C0_RESET>;
677 clocks = <&l4_sp_clk>;
678 interrupts = <0 158 0x4>;
683 #address-cells = <1>;
685 compatible = "snps,designware-i2c";
686 reg = <0xffc05000 0x1000>;
687 resets = <&rst I2C1_RESET>;
688 clocks = <&l4_sp_clk>;
689 interrupts = <0 159 0x4>;
694 #address-cells = <1>;
696 compatible = "snps,designware-i2c";
697 reg = <0xffc06000 0x1000>;
698 resets = <&rst I2C2_RESET>;
699 clocks = <&l4_sp_clk>;
700 interrupts = <0 160 0x4>;
705 #address-cells = <1>;
707 compatible = "snps,designware-i2c";
708 reg = <0xffc07000 0x1000>;
709 resets = <&rst I2C3_RESET>;
710 clocks = <&l4_sp_clk>;
711 interrupts = <0 161 0x4>;
716 compatible = "altr,socfpga-ecc-manager";
717 #address-cells = <1>;
722 compatible = "altr,socfpga-l2-ecc";
723 reg = <0xffd08140 0x4>;
724 interrupts = <0 36 1>, <0 37 1>;
728 compatible = "altr,socfpga-ocram-ecc";
729 reg = <0xffd08144 0x4>;
731 interrupts = <0 178 1>, <0 179 1>;
735 L2: cache-controller@fffef000 {
736 compatible = "arm,pl310-cache";
737 reg = <0xfffef000 0x1000>;
738 interrupts = <0 38 0x04>;
741 arm,tag-latency = <1 1 1>;
742 arm,data-latency = <2 1 1>;
744 prefetch-instr = <1>;
746 arm,double-linefill = <1>;
747 arm,double-linefill-incr = <0>;
748 arm,double-linefill-wrap = <1>;
749 arm,prefetch-drop = <0>;
750 arm,prefetch-offset = <7>;
754 compatible = "altr,l3regs", "syscon";
755 reg = <0xff800000 0x1000>;
758 mmc: dwmmc0@ff704000 {
759 compatible = "altr,socfpga-dw-mshc";
760 reg = <0xff704000 0x1000>;
761 interrupts = <0 139 4>;
762 fifo-depth = <0x400>;
763 #address-cells = <1>;
765 clocks = <&l4_mp_clk>, <&sdmmc_clk_divided>;
766 clock-names = "biu", "ciu";
767 resets = <&rst SDMMC_RESET>;
771 nand0: nand@ff900000 {
772 #address-cells = <0x1>;
774 compatible = "altr,socfpga-denali-nand";
775 reg = <0xff900000 0x100000>,
776 <0xffb80000 0x10000>;
777 reg-names = "nand_data", "denali_reg";
778 interrupts = <0x0 0x90 0x4>;
779 clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;
780 clock-names = "nand", "nand_x", "ecc";
781 resets = <&rst NAND_RESET>;
785 ocram: sram@ffff0000 {
786 compatible = "mmio-sram";
787 reg = <0xffff0000 0x10000>;
791 compatible = "intel,socfpga-qspi", "cdns,qspi-nor";
792 #address-cells = <1>;
794 reg = <0xff705000 0x1000>,
796 interrupts = <0 151 4>;
797 cdns,fifo-depth = <128>;
798 cdns,fifo-width = <4>;
799 cdns,trigger-address = <0x00000000>;
800 clocks = <&qspi_clk>;
801 resets = <&rst QSPI_RESET>;
805 rst: rstmgr@ffd05000 {
807 compatible = "altr,rst-mgr";
808 reg = <0xffd05000 0x1000>;
809 altr,modrst-offset = <0x10>;
812 scu: snoop-control-unit@fffec000 {
813 compatible = "arm,cortex-a9-scu";
814 reg = <0xfffec000 0x100>;
818 compatible = "altr,sdr-ctl", "syscon";
819 reg = <0xffc25000 0x1000>;
820 resets = <&rst SDR_RESET>;
824 compatible = "altr,sdram-edac";
825 altr,sdr-syscon = <&sdr>;
826 interrupts = <0 39 4>;
830 compatible = "snps,dw-apb-ssi";
831 #address-cells = <1>;
833 reg = <0xfff00000 0x1000>;
834 interrupts = <0 154 4>;
836 clocks = <&spi_m_clk>;
837 resets = <&rst SPIM0_RESET>;
843 compatible = "snps,dw-apb-ssi";
844 #address-cells = <1>;
846 reg = <0xfff01000 0x1000>;
847 interrupts = <0 155 4>;
849 clocks = <&spi_m_clk>;
850 resets = <&rst SPIM1_RESET>;
855 sysmgr: sysmgr@ffd08000 {
856 compatible = "altr,sys-mgr", "syscon";
857 reg = <0xffd08000 0x4000>;
862 compatible = "arm,cortex-a9-twd-timer";
863 reg = <0xfffec600 0x100>;
864 interrupts = <1 13 0xf01>;
865 clocks = <&mpu_periph_clk>;
868 timer0: timer0@ffc08000 {
869 compatible = "snps,dw-apb-timer";
870 interrupts = <0 167 4>;
871 reg = <0xffc08000 0x1000>;
872 clocks = <&l4_sp_clk>;
873 clock-names = "timer";
874 resets = <&rst SPTIMER0_RESET>;
875 reset-names = "timer";
878 timer1: timer1@ffc09000 {
879 compatible = "snps,dw-apb-timer";
880 interrupts = <0 168 4>;
881 reg = <0xffc09000 0x1000>;
882 clocks = <&l4_sp_clk>;
883 clock-names = "timer";
884 resets = <&rst SPTIMER1_RESET>;
885 reset-names = "timer";
888 timer2: timer2@ffd00000 {
889 compatible = "snps,dw-apb-timer";
890 interrupts = <0 169 4>;
891 reg = <0xffd00000 0x1000>;
893 clock-names = "timer";
894 resets = <&rst OSC1TIMER0_RESET>;
895 reset-names = "timer";
898 timer3: timer3@ffd01000 {
899 compatible = "snps,dw-apb-timer";
900 interrupts = <0 170 4>;
901 reg = <0xffd01000 0x1000>;
903 clock-names = "timer";
904 resets = <&rst OSC1TIMER1_RESET>;
905 reset-names = "timer";
908 uart0: serial0@ffc02000 {
909 compatible = "snps,dw-apb-uart";
910 reg = <0xffc02000 0x1000>;
911 interrupts = <0 162 4>;
914 clocks = <&l4_sp_clk>;
917 dma-names = "tx", "rx";
918 resets = <&rst UART0_RESET>;
921 uart1: serial1@ffc03000 {
922 compatible = "snps,dw-apb-uart";
923 reg = <0xffc03000 0x1000>;
924 interrupts = <0 163 4>;
927 clocks = <&l4_sp_clk>;
930 dma-names = "tx", "rx";
931 resets = <&rst UART1_RESET>;
936 compatible = "usb-nop-xceiv";
941 compatible = "snps,dwc2";
942 reg = <0xffb00000 0xffff>;
943 interrupts = <0 125 4>;
944 clocks = <&usb_mp_clk>;
946 resets = <&rst USB0_RESET>;
947 reset-names = "dwc2";
949 phy-names = "usb2-phy";
954 compatible = "snps,dwc2";
955 reg = <0xffb40000 0xffff>;
956 interrupts = <0 128 4>;
957 clocks = <&usb_mp_clk>;
959 resets = <&rst USB1_RESET>;
960 reset-names = "dwc2";
962 phy-names = "usb2-phy";
966 watchdog0: watchdog@ffd02000 {
967 compatible = "snps,dw-wdt";
968 reg = <0xffd02000 0x1000>;
969 interrupts = <0 171 4>;
971 resets = <&rst L4WD0_RESET>;
975 watchdog1: watchdog@ffd03000 {
976 compatible = "snps,dw-wdt";
977 reg = <0xffd03000 0x1000>;
978 interrupts = <0 172 4>;
980 resets = <&rst L4WD1_RESET>;