arch/arm/boot/dts/socfpga.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2012 Altera <www.altera.com>
   4  */
   5
   6 #include <dt-bindings/reset/altr,rst-mgr.h>
   7
   8 / {
   9         #address-cells = <1>;
  10         #size-cells = <1>;
  11
  12         aliases {
  13                 serial0 = &uart0;
  14                 serial1 = &uart1;
  15                 timer0 = &timer0;
  16                 timer1 = &timer1;
  17                 timer2 = &timer2;
  18                 timer3 = &timer3;
  19         };
  20
  21         cpus {
  22                 #address-cells = <1>;
  23                 #size-cells = <0>;
  24                 enable-method = "altr,socfpga-smp";
  25
  26                 cpu0: cpu@0 {
  27                         compatible = "arm,cortex-a9";
  28                         device_type = "cpu";
  29                         reg = <0>;
  30                         next-level-cache = <&L2>;
  31                 };
  32                 cpu1: cpu@1 {
  33                         compatible = "arm,cortex-a9";
  34                         device_type = "cpu";
  35                         reg = <1>;
  36                         next-level-cache = <&L2>;
  37                 };
  38         };
  39
  40         pmu: pmu@ff111000 {
  41                 compatible = "arm,cortex-a9-pmu";
  42                 interrupt-parent = <&intc>;
  43                 interrupts = <0 176 4>, <0 177 4>;
  44                 interrupt-affinity = <&cpu0>, <&cpu1>;
  45                 reg = <0xff111000 0x1000>,
  46                       <0xff113000 0x1000>;
  47         };
  48
  49         intc: interrupt-controller@fffed000 {
  50                 compatible = "arm,cortex-a9-gic";
  51                 #interrupt-cells = <3>;
  52                 interrupt-controller;
  53                 reg = <0xfffed000 0x1000>,
  54                       <0xfffec100 0x100>;
  55         };
  56
  57         soc {
  58                 #address-cells = <1>;
  59                 #size-cells = <1>;
  60                 compatible = "simple-bus";
  61                 device_type = "soc";
  62                 interrupt-parent = <&intc>;
  63                 ranges;
  64
  65                 amba {
  66                         compatible = "simple-bus";
  67                         #address-cells = <1>;
  68                         #size-cells = <1>;
  69                         ranges;
  70
  71                         pdma: pdma@ffe01000 {
  72                                 compatible = "arm,pl330", "arm,primecell";
  73                                 reg = <0xffe01000 0x1000>;
  74                                 interrupts = <0 104 4>,
  75                                              <0 105 4>,
  76                                              <0 106 4>,
  77                                              <0 107 4>,
  78                                              <0 108 4>,
  79                                              <0 109 4>,
  80                                              <0 110 4>,
  81                                              <0 111 4>;
  82                                 #dma-cells = <1>;
  83                                 clocks = <&l4_main_clk>;
  84                                 clock-names = "apb_pclk";
  85                                 resets = <&rst DMA_RESET>;
  86                                 reset-names = "dma";
  87                         };
  88                 };
  89
  90                 base_fpga_region {
  91                         compatible = "fpga-region";
  92                         fpga-mgr = <&fpgamgr0>;
  93
  94                         #address-cells = <0x1>;
  95                         #size-cells = <0x1>;
  96                 };
  97
  98                 can0: can@ffc00000 {
  99                         compatible = "bosch,d_can";
 100                         reg = <0xffc00000 0x1000>;
 101                         interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>;
 102                         clocks = <&can0_clk>;
 103                         resets = <&rst CAN0_RESET>;
 104                         status = "disabled";
 105                 };
 106
 107                 can1: can@ffc01000 {
 108                         compatible = "bosch,d_can";
 109                         reg = <0xffc01000 0x1000>;
 110                         interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>;
 111                         clocks = <&can1_clk>;
 112                         resets = <&rst CAN1_RESET>;
 113                         status = "disabled";
 114                 };
 115
 116                 clkmgr@ffd04000 {
 117                                 compatible = "altr,clk-mgr";
 118                                 reg = <0xffd04000 0x1000>;
 119
 120                                 clocks {
 121                                         #address-cells = <1>;
 122                                         #size-cells = <0>;
 123
 124                                         osc1: osc1 {
 125                                                 #clock-cells = <0>;
 126                                                 compatible = "fixed-clock";
 127                                         };
 128
 129                                         osc2: osc2 {
 130                                                 #clock-cells = <0>;
 131                                                 compatible = "fixed-clock";
 132                                         };
 133
 134                                         f2s_periph_ref_clk: f2s_periph_ref_clk {
 135                                                 #clock-cells = <0>;
 136                                                 compatible = "fixed-clock";
 137                                         };
 138
 139                                         f2s_sdram_ref_clk: f2s_sdram_ref_clk {
 140                                                 #clock-cells = <0>;
 141                                                 compatible = "fixed-clock";
 142                                         };
 143
 144                                         main_pll: main_pll@40 {
 145                                                 #address-cells = <1>;
 146                                                 #size-cells = <0>;
 147                                                 #clock-cells = <0>;
 148                                                 compatible = "altr,socfpga-pll-clock";
 149                                                 clocks = <&osc1>;
 150                                                 reg = <0x40>;
 151
 152                                                 mpuclk: mpuclk@48 {
 153                                                         #clock-cells = <0>;
 154                                                         compatible = "altr,socfpga-perip-clk";
 155                                                         clocks = <&main_pll>;
 156                                                         div-reg = <0xe0 0 9>;
 157                                                         reg = <0x48>;
 158                                                 };
 159
 160                                                 mainclk: mainclk@4c {
 161                                                         #clock-cells = <0>;
 162                                                         compatible = "altr,socfpga-perip-clk";
 163                                                         clocks = <&main_pll>;
 164                                                         div-reg = <0xe4 0 9>;
 165                                                         reg = <0x4C>;
 166                                                 };
 167
 168                                                 dbg_base_clk: dbg_base_clk@50 {
 169                                                         #clock-cells = <0>;
 170                                                         compatible = "altr,socfpga-perip-clk";
 171                                                         clocks = <&main_pll>, <&osc1>;
 172                                                         div-reg = <0xe8 0 9>;
 173                                                         reg = <0x50>;
 174                                                 };
 175
 176                                                 main_qspi_clk: main_qspi_clk@54 {
 177                                                         #clock-cells = <0>;
 178                                                         compatible = "altr,socfpga-perip-clk";
 179                                                         clocks = <&main_pll>;
 180                                                         reg = <0x54>;
 181                                                 };
 182
 183                                                 main_nand_sdmmc_clk: main_nand_sdmmc_clk@58 {
 184                                                         #clock-cells = <0>;
 185                                                         compatible = "altr,socfpga-perip-clk";
 186                                                         clocks = <&main_pll>;
 187                                                         reg = <0x58>;
 188                                                 };
 189
 190                                                 cfg_h2f_usr0_clk: cfg_h2f_usr0_clk@5c {
 191                                                         #clock-cells = <0>;
 192                                                         compatible = "altr,socfpga-perip-clk";
 193                                                         clocks = <&main_pll>;
 194                                                         reg = <0x5C>;
 195                                                 };
 196                                         };
 197
 198                                         periph_pll: periph_pll@80 {
 199                                                 #address-cells = <1>;
 200                                                 #size-cells = <0>;
 201                                                 #clock-cells = <0>;
 202                                                 compatible = "altr,socfpga-pll-clock";
 203                                                 clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>;
 204                                                 reg = <0x80>;
 205
 206                                                 emac0_clk: emac0_clk@88 {
 207                                                         #clock-cells = <0>;
 208                                                         compatible = "altr,socfpga-perip-clk";
 209                                                         clocks = <&periph_pll>;
 210                                                         reg = <0x88>;
 211                                                 };
 212
 213                                                 emac1_clk: emac1_clk@8c {
 214                                                         #clock-cells = <0>;
 215                                                         compatible = "altr,socfpga-perip-clk";
 216                                                         clocks = <&periph_pll>;
 217                                                         reg = <0x8C>;
 218                                                 };
 219
 220                                                 per_qspi_clk: per_qsi_clk@90 {
 221                                                         #clock-cells = <0>;
 222                                                         compatible = "altr,socfpga-perip-clk";
 223                                                         clocks = <&periph_pll>;
 224                                                         reg = <0x90>;
 225                                                 };
 226
 227                                                 per_nand_mmc_clk: per_nand_mmc_clk@94 {
 228                                                         #clock-cells = <0>;
 229                                                         compatible = "altr,socfpga-perip-clk";
 230                                                         clocks = <&periph_pll>;
 231                                                         reg = <0x94>;
 232                                                 };
 233
 234                                                 per_base_clk: per_base_clk@98 {
 235                                                         #clock-cells = <0>;
 236                                                         compatible = "altr,socfpga-perip-clk";
 237                                                         clocks = <&periph_pll>;
 238                                                         reg = <0x98>;
 239                                                 };
 240
 241                                                 h2f_usr1_clk: h2f_usr1_clk@9c {
 242                                                         #clock-cells = <0>;
 243                                                         compatible = "altr,socfpga-perip-clk";
 244                                                         clocks = <&periph_pll>;
 245                                                         reg = <0x9C>;
 246                                                 };
 247                                         };
 248
 249                                         sdram_pll: sdram_pll@c0 {
 250                                                 #address-cells = <1>;
 251                                                 #size-cells = <0>;
 252                                                 #clock-cells = <0>;
 253                                                 compatible = "altr,socfpga-pll-clock";
 254                                                 clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>;
 255                                                 reg = <0xC0>;
 256
 257                                                 ddr_dqs_clk: ddr_dqs_clk@c8 {
 258                                                         #clock-cells = <0>;
 259                                                         compatible = "altr,socfpga-perip-clk";
 260                                                         clocks = <&sdram_pll>;
 261                                                         reg = <0xC8>;
 262                                                 };
 263
 264                                                 ddr_2x_dqs_clk: ddr_2x_dqs_clk@cc {
 265                                                         #clock-cells = <0>;
 266                                                         compatible = "altr,socfpga-perip-clk";
 267                                                         clocks = <&sdram_pll>;
 268                                                         reg = <0xCC>;
 269                                                 };
 270
 271                                                 ddr_dq_clk: ddr_dq_clk@d0 {
 272                                                         #clock-cells = <0>;
 273                                                         compatible = "altr,socfpga-perip-clk";
 274                                                         clocks = <&sdram_pll>;
 275                                                         reg = <0xD0>;
 276                                                 };
 277
 278                                                 h2f_usr2_clk: h2f_usr2_clk@d4 {
 279                                                         #clock-cells = <0>;
 280                                                         compatible = "altr,socfpga-perip-clk";
 281                                                         clocks = <&sdram_pll>;
 282                                                         reg = <0xD4>;
 283                                                 };
 284                                         };
 285
 286                                         mpu_periph_clk: mpu_periph_clk {
 287                                                 #clock-cells = <0>;
 288                                                 compatible = "altr,socfpga-perip-clk";
 289                                                 clocks = <&mpuclk>;
 290                                                 fixed-divider = <4>;
 291                                         };
 292
 293                                         mpu_l2_ram_clk: mpu_l2_ram_clk {
 294                                                 #clock-cells = <0>;
 295                                                 compatible = "altr,socfpga-perip-clk";
 296                                                 clocks = <&mpuclk>;
 297                                                 fixed-divider = <2>;
 298                                         };
 299
 300                                         l4_main_clk: l4_main_clk {
 301                                                 #clock-cells = <0>;
 302                                                 compatible = "altr,socfpga-gate-clk";
 303                                                 clocks = <&mainclk>;
 304                                                 clk-gate = <0x60 0>;
 305                                         };
 306
 307                                         l3_main_clk: l3_main_clk {
 308                                                 #clock-cells = <0>;
 309                                                 compatible = "altr,socfpga-perip-clk";
 310                                                 clocks = <&mainclk>;
 311                                                 fixed-divider = <1>;
 312                                         };
 313
 314                                         l3_mp_clk: l3_mp_clk {
 315                                                 #clock-cells = <0>;
 316                                                 compatible = "altr,socfpga-gate-clk";
 317                                                 clocks = <&mainclk>;
 318                                                 div-reg = <0x64 0 2>;
 319                                                 clk-gate = <0x60 1>;
 320                                         };
 321
 322                                         l3_sp_clk: l3_sp_clk {
 323                                                 #clock-cells = <0>;
 324                                                 compatible = "altr,socfpga-gate-clk";
 325                                                 clocks = <&l3_mp_clk>;
 326                                                 div-reg = <0x64 2 2>;
 327                                         };
 328
 329                                         l4_mp_clk: l4_mp_clk {
 330                                                 #clock-cells = <0>;
 331                                                 compatible = "altr,socfpga-gate-clk";
 332                                                 clocks = <&mainclk>, <&per_base_clk>;
 333                                                 div-reg = <0x64 4 3>;
 334                                                 clk-gate = <0x60 2>;
 335                                         };
 336
 337                                         l4_sp_clk: l4_sp_clk {
 338                                                 #clock-cells = <0>;
 339                                                 compatible = "altr,socfpga-gate-clk";
 340                                                 clocks = <&mainclk>, <&per_base_clk>;
 341                                                 div-reg = <0x64 7 3>;
 342                                                 clk-gate = <0x60 3>;
 343                                         };
 344
 345                                         dbg_at_clk: dbg_at_clk {
 346                                                 #clock-cells = <0>;
 347                                                 compatible = "altr,socfpga-gate-clk";
 348                                                 clocks = <&dbg_base_clk>;
 349                                                 div-reg = <0x68 0 2>;
 350                                                 clk-gate = <0x60 4>;
 351                                         };
 352
 353                                         dbg_clk: dbg_clk {
 354                                                 #clock-cells = <0>;
 355                                                 compatible = "altr,socfpga-gate-clk";
 356                                                 clocks = <&dbg_at_clk>;
 357                                                 div-reg = <0x68 2 2>;
 358                                                 clk-gate = <0x60 5>;
 359                                         };
 360
 361                                         dbg_trace_clk: dbg_trace_clk {
 362                                                 #clock-cells = <0>;
 363                                                 compatible = "altr,socfpga-gate-clk";
 364                                                 clocks = <&dbg_base_clk>;
 365                                                 div-reg = <0x6C 0 3>;
 366                                                 clk-gate = <0x60 6>;
 367                                         };
 368
 369                                         dbg_timer_clk: dbg_timer_clk {
 370                                                 #clock-cells = <0>;
 371                                                 compatible = "altr,socfpga-gate-clk";
 372                                                 clocks = <&dbg_base_clk>;
 373                                                 clk-gate = <0x60 7>;
 374                                         };
 375
 376                                         cfg_clk: cfg_clk {
 377                                                 #clock-cells = <0>;
 378                                                 compatible = "altr,socfpga-gate-clk";
 379                                                 clocks = <&cfg_h2f_usr0_clk>;
 380                                                 clk-gate = <0x60 8>;
 381                                         };
 382
 383                                         h2f_user0_clk: h2f_user0_clk {
 384                                                 #clock-cells = <0>;
 385                                                 compatible = "altr,socfpga-gate-clk";
 386                                                 clocks = <&cfg_h2f_usr0_clk>;
 387                                                 clk-gate = <0x60 9>;
 388                                         };
 389
 390                                         emac_0_clk: emac_0_clk {
 391                                                 #clock-cells = <0>;
 392                                                 compatible = "altr,socfpga-gate-clk";
 393                                                 clocks = <&emac0_clk>;
 394                                                 clk-gate = <0xa0 0>;
 395                                         };
 396
 397                                         emac_1_clk: emac_1_clk {
 398                                                 #clock-cells = <0>;
 399                                                 compatible = "altr,socfpga-gate-clk";
 400                                                 clocks = <&emac1_clk>;
 401                                                 clk-gate = <0xa0 1>;
 402                                         };
 403
 404                                         usb_mp_clk: usb_mp_clk {
 405                                                 #clock-cells = <0>;
 406                                                 compatible = "altr,socfpga-gate-clk";
 407                                                 clocks = <&per_base_clk>;
 408                                                 clk-gate = <0xa0 2>;
 409                                                 div-reg = <0xa4 0 3>;
 410                                         };
 411
 412                                         spi_m_clk: spi_m_clk {
 413                                                 #clock-cells = <0>;
 414                                                 compatible = "altr,socfpga-gate-clk";
 415                                                 clocks = <&per_base_clk>;
 416                                                 clk-gate = <0xa0 3>;
 417                                                 div-reg = <0xa4 3 3>;
 418                                         };
 419
 420                                         can0_clk: can0_clk {
 421                                                 #clock-cells = <0>;
 422                                                 compatible = "altr,socfpga-gate-clk";
 423                                                 clocks = <&per_base_clk>;
 424                                                 clk-gate = <0xa0 4>;
 425                                                 div-reg = <0xa4 6 3>;
 426                                         };
 427
 428                                         can1_clk: can1_clk {
 429                                                 #clock-cells = <0>;
 430                                                 compatible = "altr,socfpga-gate-clk";
 431                                                 clocks = <&per_base_clk>;
 432                                                 clk-gate = <0xa0 5>;
 433                                                 div-reg = <0xa4 9 3>;
 434                                         };
 435
 436                                         gpio_db_clk: gpio_db_clk {
 437                                                 #clock-cells = <0>;
 438                                                 compatible = "altr,socfpga-gate-clk";
 439                                                 clocks = <&per_base_clk>;
 440                                                 clk-gate = <0xa0 6>;
 441                                                 div-reg = <0xa8 0 24>;
 442                                         };
 443
 444                                         h2f_user1_clk: h2f_user1_clk {
 445                                                 #clock-cells = <0>;
 446                                                 compatible = "altr,socfpga-gate-clk";
 447                                                 clocks = <&h2f_usr1_clk>;
 448                                                 clk-gate = <0xa0 7>;
 449                                         };
 450
 451                                         sdmmc_clk: sdmmc_clk {
 452                                                 #clock-cells = <0>;
 453                                                 compatible = "altr,socfpga-gate-clk";
 454                                                 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
 455                                                 clk-gate = <0xa0 8>;
 456                                                 clk-phase = <0 135>;
 457                                         };
 458
 459                                         sdmmc_clk_divided: sdmmc_clk_divided {
 460                                                 #clock-cells = <0>;
 461                                                 compatible = "altr,socfpga-gate-clk";
 462                                                 clocks = <&sdmmc_clk>;
 463                                                 clk-gate = <0xa0 8>;
 464                                                 fixed-divider = <4>;
 465                                         };
 466
 467                                         nand_x_clk: nand_x_clk {
 468                                                 #clock-cells = <0>;
 469                                                 compatible = "altr,socfpga-gate-clk";
 470                                                 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
 471                                                 clk-gate = <0xa0 9>;
 472                                         };
 473
 474                                         nand_ecc_clk: nand_ecc_clk {
 475                                                 #clock-cells = <0>;
 476                                                 compatible = "altr,socfpga-gate-clk";
 477                                                 clocks = <&nand_x_clk>;
 478                                                 clk-gate = <0xa0 9>;
 479                                         };
 480
 481                                         nand_clk: nand_clk {
 482                                                 #clock-cells = <0>;
 483                                                 compatible = "altr,socfpga-gate-clk";
 484                                                 clocks = <&nand_x_clk>;
 485                                                 clk-gate = <0xa0 10>;
 486                                                 fixed-divider = <4>;
 487                                         };
 488
 489                                         qspi_clk: qspi_clk {
 490                                                 #clock-cells = <0>;
 491                                                 compatible = "altr,socfpga-gate-clk";
 492                                                 clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;
 493                                                 clk-gate = <0xa0 11>;
 494                                         };
 495
 496                                         ddr_dqs_clk_gate: ddr_dqs_clk_gate {
 497                                                 #clock-cells = <0>;
 498                                                 compatible = "altr,socfpga-gate-clk";
 499                                                 clocks = <&ddr_dqs_clk>;
 500                                                 clk-gate = <0xd8 0>;
 501                                         };
 502
 503                                         ddr_2x_dqs_clk_gate: ddr_2x_dqs_clk_gate {
 504                                                 #clock-cells = <0>;
 505                                                 compatible = "altr,socfpga-gate-clk";
 506                                                 clocks = <&ddr_2x_dqs_clk>;
 507                                                 clk-gate = <0xd8 1>;
 508                                         };
 509
 510                                         ddr_dq_clk_gate: ddr_dq_clk_gate {
 511                                                 #clock-cells = <0>;
 512                                                 compatible = "altr,socfpga-gate-clk";
 513                                                 clocks = <&ddr_dq_clk>;
 514                                                 clk-gate = <0xd8 2>;
 515                                         };
 516
 517                                         h2f_user2_clk: h2f_user2_clk {
 518                                                 #clock-cells = <0>;
 519                                                 compatible = "altr,socfpga-gate-clk";
 520                                                 clocks = <&h2f_usr2_clk>;
 521                                                 clk-gate = <0xd8 3>;
 522                                         };
 523
 524                                 };
 525                 };
 526
 527                 fpga_bridge0: fpga_bridge@ff400000 {
 528                         compatible = "altr,socfpga-lwhps2fpga-bridge";
 529                         reg = <0xff400000 0x100000>;
 530                         resets = <&rst LWHPS2FPGA_RESET>;
 531                         clocks = <&l4_main_clk>;
 532                         status = "disabled";
 533                 };
 534
 535                 fpga_bridge1: fpga_bridge@ff500000 {
 536                         compatible = "altr,socfpga-hps2fpga-bridge";
 537                         reg = <0xff500000 0x10000>;
 538                         resets = <&rst HPS2FPGA_RESET>;
 539                         clocks = <&l4_main_clk>;
 540                         status = "disabled";
 541                 };
 542
 543                 fpga_bridge2: fpga-bridge@ff600000 {
 544                         compatible = "altr,socfpga-fpga2hps-bridge";
 545                         reg = <0xff600000 0x100000>;
 546                         resets = <&rst FPGA2HPS_RESET>;
 547                         clocks = <&l4_main_clk>;
 548                         status = "disabled";
 549                 };
 550
 551                 fpga_bridge3: fpga-bridge@ffc25080 {
 552                         compatible = "altr,socfpga-fpga2sdram-bridge";
 553                         reg = <0xffc25080 0x4>;
 554                         status = "disabled";
 555                 };
 556
 557                 fpgamgr0: fpgamgr@ff706000 {
 558                         compatible = "altr,socfpga-fpga-mgr";
 559                         reg = <0xff706000 0x1000
 560                                0xffb90000 0x4>;
 561                         interrupts = <0 175 4>;
 562                 };
 563
 564                 gmac0: ethernet@ff700000 {
 565                         compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
 566                         altr,sysmgr-syscon = <&sysmgr 0x60 0>;
 567                         reg = <0xff700000 0x2000>;
 568                         interrupts = <0 115 4>;
 569                         interrupt-names = "macirq";
 570                         mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
 571                         clocks = <&emac_0_clk>;
 572                         clock-names = "stmmaceth";
 573                         resets = <&rst EMAC0_RESET>;
 574                         reset-names = "stmmaceth";
 575                         snps,multicast-filter-bins = <256>;
 576                         snps,perfect-filter-entries = <128>;
 577                         tx-fifo-depth = <4096>;
 578                         rx-fifo-depth = <4096>;
 579                         status = "disabled";
 580                 };
 581
 582                 gmac1: ethernet@ff702000 {
 583                         compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
 584                         altr,sysmgr-syscon = <&sysmgr 0x60 2>;
 585                         reg = <0xff702000 0x2000>;
 586                         interrupts = <0 120 4>;
 587                         interrupt-names = "macirq";
 588                         mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
 589                         clocks = <&emac_1_clk>;
 590                         clock-names = "stmmaceth";
 591                         resets = <&rst EMAC1_RESET>;
 592                         reset-names = "stmmaceth";
 593                         snps,multicast-filter-bins = <256>;
 594                         snps,perfect-filter-entries = <128>;
 595                         tx-fifo-depth = <4096>;
 596                         rx-fifo-depth = <4096>;
 597                         status = "disabled";
 598                 };
 599
 600                 gpio0: gpio@ff708000 {
 601                         #address-cells = <1>;
 602                         #size-cells = <0>;
 603                         compatible = "snps,dw-apb-gpio";
 604                         reg = <0xff708000 0x1000>;
 605                         clocks = <&l4_mp_clk>;
 606                         resets = <&rst GPIO0_RESET>;
 607                         status = "disabled";
 608
 609                         porta: gpio-controller@0 {
 610                                 compatible = "snps,dw-apb-gpio-port";
 611                                 gpio-controller;
 612                                 #gpio-cells = <2>;
 613                                 snps,nr-gpios = <29>;
 614                                 reg = <0>;
 615                                 interrupt-controller;
 616                                 #interrupt-cells = <2>;
 617                                 interrupts = <0 164 4>;
 618                         };
 619                 };
 620
 621                 gpio1: gpio@ff709000 {
 622                         #address-cells = <1>;
 623                         #size-cells = <0>;
 624                         compatible = "snps,dw-apb-gpio";
 625                         reg = <0xff709000 0x1000>;
 626                         clocks = <&l4_mp_clk>;
 627                         resets = <&rst GPIO1_RESET>;
 628                         status = "disabled";
 629
 630                         portb: gpio-controller@0 {
 631                                 compatible = "snps,dw-apb-gpio-port";
 632                                 gpio-controller;
 633                                 #gpio-cells = <2>;
 634                                 snps,nr-gpios = <29>;
 635                                 reg = <0>;
 636                                 interrupt-controller;
 637                                 #interrupt-cells = <2>;
 638                                 interrupts = <0 165 4>;
 639                         };
 640                 };
 641
 642                 gpio2: gpio@ff70a000 {
 643                         #address-cells = <1>;
 644                         #size-cells = <0>;
 645                         compatible = "snps,dw-apb-gpio";
 646                         reg = <0xff70a000 0x1000>;
 647                         clocks = <&l4_mp_clk>;
 648                         resets = <&rst GPIO2_RESET>;
 649                         status = "disabled";
 650
 651                         portc: gpio-controller@0 {
 652                                 compatible = "snps,dw-apb-gpio-port";
 653                                 gpio-controller;
 654                                 #gpio-cells = <2>;
 655                                 snps,nr-gpios = <27>;
 656                                 reg = <0>;
 657                                 interrupt-controller;
 658                                 #interrupt-cells = <2>;
 659                                 interrupts = <0 166 4>;
 660                         };
 661                 };
 662
 663                 i2c0: i2c@ffc04000 {
 664                         #address-cells = <1>;
 665                         #size-cells = <0>;
 666                         compatible = "snps,designware-i2c";
 667                         reg = <0xffc04000 0x1000>;
 668                         resets = <&rst I2C0_RESET>;
 669                         clocks = <&l4_sp_clk>;
 670                         interrupts = <0 158 0x4>;
 671                         status = "disabled";
 672                 };
 673
 674                 i2c1: i2c@ffc05000 {
 675                         #address-cells = <1>;
 676                         #size-cells = <0>;
 677                         compatible = "snps,designware-i2c";
 678                         reg = <0xffc05000 0x1000>;
 679                         resets = <&rst I2C1_RESET>;
 680                         clocks = <&l4_sp_clk>;
 681                         interrupts = <0 159 0x4>;
 682                         status = "disabled";
 683                 };
 684
 685                 i2c2: i2c@ffc06000 {
 686                         #address-cells = <1>;
 687                         #size-cells = <0>;
 688                         compatible = "snps,designware-i2c";
 689                         reg = <0xffc06000 0x1000>;
 690                         resets = <&rst I2C2_RESET>;
 691                         clocks = <&l4_sp_clk>;
 692                         interrupts = <0 160 0x4>;
 693                         status = "disabled";
 694                 };
 695
 696                 i2c3: i2c@ffc07000 {
 697                         #address-cells = <1>;
 698                         #size-cells = <0>;
 699                         compatible = "snps,designware-i2c";
 700                         reg = <0xffc07000 0x1000>;
 701                         resets = <&rst I2C3_RESET>;
 702                         clocks = <&l4_sp_clk>;
 703                         interrupts = <0 161 0x4>;
 704                         status = "disabled";
 705                 };
 706
 707                 eccmgr: eccmgr {
 708                         compatible = "altr,socfpga-ecc-manager";
 709                         #address-cells = <1>;
 710                         #size-cells = <1>;
 711                         ranges;
 712
 713                         l2-ecc@ffd08140 {
 714                                 compatible = "altr,socfpga-l2-ecc";
 715                                 reg = <0xffd08140 0x4>;
 716                                 interrupts = <0 36 1>, <0 37 1>;
 717                         };
 718
 719                         ocram-ecc@ffd08144 {
 720                                 compatible = "altr,socfpga-ocram-ecc";
 721                                 reg = <0xffd08144 0x4>;
 722                                 iram = <&ocram>;
 723                                 interrupts = <0 178 1>, <0 179 1>;
 724                         };
 725                 };
 726
 727                 L2: cache-controller@fffef000 {
 728                         compatible = "arm,pl310-cache";
 729                         reg = <0xfffef000 0x1000>;
 730                         interrupts = <0 38 0x04>;
 731                         cache-unified;
 732                         cache-level = <2>;
 733                         arm,tag-latency = <1 1 1>;
 734                         arm,data-latency = <2 1 1>;
 735                         prefetch-data = <1>;
 736                         prefetch-instr = <1>;
 737                         arm,shared-override;
 738                         arm,double-linefill = <1>;
 739                         arm,double-linefill-incr = <0>;
 740                         arm,double-linefill-wrap = <1>;
 741                         arm,prefetch-drop = <0>;
 742                         arm,prefetch-offset = <7>;
 743                 };
 744
 745                 l3regs@0xff800000 {
 746                         compatible = "altr,l3regs", "syscon";
 747                         reg = <0xff800000 0x1000>;
 748                 };
 749
 750                 mmc: dwmmc0@ff704000 {
 751                         compatible = "altr,socfpga-dw-mshc";
 752                         reg = <0xff704000 0x1000>;
 753                         interrupts = <0 139 4>;
 754                         fifo-depth = <0x400>;
 755                         #address-cells = <1>;
 756                         #size-cells = <0>;
 757                         clocks = <&l4_mp_clk>, <&sdmmc_clk_divided>;
 758                         clock-names = "biu", "ciu";
 759                         resets = <&rst SDMMC_RESET>;
 760                         status = "disabled";
 761                 };
 762
 763                 nand0: nand@ff900000 {
 764                         #address-cells = <0x1>;
 765                         #size-cells = <0x0>;
 766                         compatible = "altr,socfpga-denali-nand";
 767                         reg = <0xff900000 0x100000>,
 768                               <0xffb80000 0x10000>;
 769                         reg-names = "nand_data", "denali_reg";
 770                         interrupts = <0x0 0x90 0x4>;
 771                         clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;
 772                         clock-names = "nand", "nand_x", "ecc";
 773                         resets = <&rst NAND_RESET>;
 774                         status = "disabled";
 775                 };
 776
 777                 ocram: sram@ffff0000 {
 778                         compatible = "mmio-sram";
 779                         reg = <0xffff0000 0x10000>;
 780                 };
 781
 782                 qspi: spi@ff705000 {
 783                         compatible = "intel,socfpga-qspi", "cdns,qspi-nor";
 784                         #address-cells = <1>;
 785                         #size-cells = <0>;
 786                         reg = <0xff705000 0x1000>,
 787                               <0xffa00000 0x1000>;
 788                         interrupts = <0 151 4>;
 789                         cdns,fifo-depth = <128>;
 790                         cdns,fifo-width = <4>;
 791                         cdns,trigger-address = <0x00000000>;
 792                         clocks = <&qspi_clk>;
 793                         resets = <&rst QSPI_RESET>;
 794                         status = "disabled";
 795                 };
 796
 797                 rst: rstmgr@ffd05000 {
 798                         #reset-cells = <1>;
 799                         compatible = "altr,rst-mgr";
 800                         reg = <0xffd05000 0x1000>;
 801                         altr,modrst-offset = <0x10>;
 802                 };
 803
 804                 scu: snoop-control-unit@fffec000 {
 805                         compatible = "arm,cortex-a9-scu";
 806                         reg = <0xfffec000 0x100>;
 807                 };
 808
 809                 sdr: sdr@ffc25000 {
 810                         compatible = "altr,sdr-ctl", "syscon";
 811                         reg = <0xffc25000 0x1000>;
 812                         resets = <&rst SDR_RESET>;
 813                 };
 814
 815                 sdramedac {
 816                         compatible = "altr,sdram-edac";
 817                         altr,sdr-syscon = <&sdr>;
 818                         interrupts = <0 39 4>;
 819                 };
 820
 821                 spi0: spi@fff00000 {
 822                         compatible = "snps,dw-apb-ssi";
 823                         #address-cells = <1>;
 824                         #size-cells = <0>;
 825                         reg = <0xfff00000 0x1000>;
 826                         interrupts = <0 154 4>;
 827                         num-cs = <4>;
 828                         clocks = <&spi_m_clk>;
 829                         resets = <&rst SPIM0_RESET>;
 830                         reset-names = "spi";
 831                         status = "disabled";
 832                 };
 833
 834                 spi1: spi@fff01000 {
 835                         compatible = "snps,dw-apb-ssi";
 836                         #address-cells = <1>;
 837                         #size-cells = <0>;
 838                         reg = <0xfff01000 0x1000>;
 839                         interrupts = <0 155 4>;
 840                         num-cs = <4>;
 841                         clocks = <&spi_m_clk>;
 842                         resets = <&rst SPIM1_RESET>;
 843                         reset-names = "spi";
 844                         status = "disabled";
 845                 };
 846
 847                 sysmgr: sysmgr@ffd08000 {
 848                         compatible = "altr,sys-mgr", "syscon";
 849                         reg = <0xffd08000 0x4000>;
 850                 };
 851
 852                 /* Local timer */
 853                 timer@fffec600 {
 854                         compatible = "arm,cortex-a9-twd-timer";
 855                         reg = <0xfffec600 0x100>;
 856                         interrupts = <1 13 0xf01>;
 857                         clocks = <&mpu_periph_clk>;
 858                 };
 859
 860                 timer0: timer0@ffc08000 {
 861                         compatible = "snps,dw-apb-timer";
 862                         interrupts = <0 167 4>;
 863                         reg = <0xffc08000 0x1000>;
 864                         clocks = <&l4_sp_clk>;
 865                         clock-names = "timer";
 866                         resets = <&rst SPTIMER0_RESET>;
 867                         reset-names = "timer";
 868                 };
 869
 870                 timer1: timer1@ffc09000 {
 871                         compatible = "snps,dw-apb-timer";
 872                         interrupts = <0 168 4>;
 873                         reg = <0xffc09000 0x1000>;
 874                         clocks = <&l4_sp_clk>;
 875                         clock-names = "timer";
 876                         resets = <&rst SPTIMER1_RESET>;
 877                         reset-names = "timer";
 878                 };
 879
 880                 timer2: timer2@ffd00000 {
 881                         compatible = "snps,dw-apb-timer";
 882                         interrupts = <0 169 4>;
 883                         reg = <0xffd00000 0x1000>;
 884                         clocks = <&osc1>;
 885                         clock-names = "timer";
 886                         resets = <&rst OSC1TIMER0_RESET>;
 887                         reset-names = "timer";
 888                 };
 889
 890                 timer3: timer3@ffd01000 {
 891                         compatible = "snps,dw-apb-timer";
 892                         interrupts = <0 170 4>;
 893                         reg = <0xffd01000 0x1000>;
 894                         clocks = <&osc1>;
 895                         clock-names = "timer";
 896                         resets = <&rst OSC1TIMER1_RESET>;
 897                         reset-names = "timer";
 898                 };
 899
 900                 uart0: serial0@ffc02000 {
 901                         compatible = "snps,dw-apb-uart";
 902                         reg = <0xffc02000 0x1000>;
 903                         interrupts = <0 162 4>;
 904                         reg-shift = <2>;
 905                         reg-io-width = <4>;
 906                         clocks = <&l4_sp_clk>;
 907                         dmas = <&pdma 28>,
 908                                <&pdma 29>;
 909                         dma-names = "tx", "rx";
 910                         resets = <&rst UART0_RESET>;
 911                 };
 912
 913                 uart1: serial1@ffc03000 {
 914                         compatible = "snps,dw-apb-uart";
 915                         reg = <0xffc03000 0x1000>;
 916                         interrupts = <0 163 4>;
 917                         reg-shift = <2>;
 918                         reg-io-width = <4>;
 919                         clocks = <&l4_sp_clk>;
 920                         dmas = <&pdma 30>,
 921                                <&pdma 31>;
 922                         dma-names = "tx", "rx";
 923                         resets = <&rst UART1_RESET>;
 924                 };
 925
 926                 usbphy0: usbphy {
 927                         #phy-cells = <0>;
 928                         compatible = "usb-nop-xceiv";
 929                         status = "okay";
 930                 };
 931
 932                 usb0: usb@ffb00000 {
 933                         compatible = "snps,dwc2";
 934                         reg = <0xffb00000 0xffff>;
 935                         interrupts = <0 125 4>;
 936                         clocks = <&usb_mp_clk>;
 937                         clock-names = "otg";
 938                         resets = <&rst USB0_RESET>;
 939                         reset-names = "dwc2";
 940                         phys = <&usbphy0>;
 941                         phy-names = "usb2-phy";
 942                         status = "disabled";
 943                 };
 944
 945                 usb1: usb@ffb40000 {
 946                         compatible = "snps,dwc2";
 947                         reg = <0xffb40000 0xffff>;
 948                         interrupts = <0 128 4>;
 949                         clocks = <&usb_mp_clk>;
 950                         clock-names = "otg";
 951                         resets = <&rst USB1_RESET>;
 952                         reset-names = "dwc2";
 953                         phys = <&usbphy0>;
 954                         phy-names = "usb2-phy";
 955                         status = "disabled";
 956                 };
 957
 958                 watchdog0: watchdog@ffd02000 {
 959                         compatible = "snps,dw-wdt";
 960                         reg = <0xffd02000 0x1000>;
 961                         interrupts = <0 171 4>;
 962                         clocks = <&osc1>;
 963                         resets = <&rst L4WD0_RESET>;
 964                         status = "disabled";
 965                 };
 966
 967                 watchdog1: watchdog@ffd03000 {
 968                         compatible = "snps,dw-wdt";
 969                         reg = <0xffd03000 0x1000>;
 970                         interrupts = <0 172 4>;
 971                         clocks = <&osc1>;
 972                         resets = <&rst L4WD1_RESET>;
 973                         status = "disabled";
 974                 };
 975         };
 976 };