2 * Device Tree Source for the SH73A0 SoC
4 * Copyright (C) 2012 Renesas Solutions Corp.
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
11 /include/ "skeleton.dtsi"
13 #include <dt-bindings/clock/sh73a0-clock.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/interrupt-controller/irq.h>
18 compatible = "renesas,sh73a0";
19 interrupt-parent = <&gic>;
27 compatible = "arm,cortex-a9";
29 clock-frequency = <1196000000>;
30 power-domains = <&pd_a2sl>;
31 next-level-cache = <&L2>;
35 compatible = "arm,cortex-a9";
37 clock-frequency = <1196000000>;
38 power-domains = <&pd_a2sl>;
39 next-level-cache = <&L2>;
44 compatible = "arm,cortex-a9-twd-timer";
45 reg = <0xf0000600 0x20>;
46 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
50 gic: interrupt-controller@f0001000 {
51 compatible = "arm,cortex-a9-gic";
52 #interrupt-cells = <3>;
54 reg = <0xf0001000 0x1000>,
58 L2: cache-controller@f0100000 {
59 compatible = "arm,pl310-cache";
60 reg = <0xf0100000 0x1000>;
61 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
62 power-domains = <&pd_a3sm>;
63 arm,data-latency = <3 3 3>;
64 arm,tag-latency = <2 2 2>;
70 sbsc2: memory-controller@fb400000 {
71 compatible = "renesas,sbsc-sh73a0";
72 reg = <0xfb400000 0x400>;
73 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
74 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
75 interrupt-names = "sec", "temp";
76 power-domains = <&pd_a4bc1>;
79 sbsc1: memory-controller@fe400000 {
80 compatible = "renesas,sbsc-sh73a0";
81 reg = <0xfe400000 0x400>;
82 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
83 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
84 interrupt-names = "sec", "temp";
85 power-domains = <&pd_a4bc0>;
89 compatible = "arm,cortex-a9-pmu";
90 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
91 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
92 interrupt-affinity = <&cpu0>, <&cpu1>;
95 cmt1: timer@e6138000 {
96 compatible = "renesas,cmt-48-sh73a0", "renesas,cmt-48";
97 reg = <0xe6138000 0x200>;
98 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
99 clocks = <&mstp3_clks SH73A0_CLK_CMT1>;
101 power-domains = <&pd_c5>;
103 renesas,channels-mask = <0x3f>;
108 irqpin0: interrupt-controller@e6900000 {
109 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
110 #interrupt-cells = <2>;
111 interrupt-controller;
112 reg = <0xe6900000 4>,
117 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
118 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
119 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
120 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH
121 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH
122 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH
123 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH
124 GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
125 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
126 power-domains = <&pd_a4s>;
130 irqpin1: interrupt-controller@e6900004 {
131 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
132 #interrupt-cells = <2>;
133 interrupt-controller;
134 reg = <0xe6900004 4>,
139 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH
140 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH
141 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH
142 GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH
143 GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH
144 GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH
145 GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH
146 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
147 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
148 power-domains = <&pd_a4s>;
152 irqpin2: interrupt-controller@e6900008 {
153 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
154 #interrupt-cells = <2>;
155 interrupt-controller;
156 reg = <0xe6900008 4>,
161 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH
162 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
163 GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH
164 GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH
165 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH
166 GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH
167 GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH
168 GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
169 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
170 power-domains = <&pd_a4s>;
174 irqpin3: interrupt-controller@e690000c {
175 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
176 #interrupt-cells = <2>;
177 interrupt-controller;
178 reg = <0xe690000c 4>,
183 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH
184 GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH
185 GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH
186 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH
187 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH
188 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH
189 GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH
190 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
191 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
192 power-domains = <&pd_a4s>;
197 #address-cells = <1>;
199 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
200 reg = <0xe6820000 0x425>;
201 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH
202 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH
203 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH
204 GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
205 clocks = <&mstp1_clks SH73A0_CLK_IIC0>;
206 power-domains = <&pd_a3sp>;
211 #address-cells = <1>;
213 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
214 reg = <0xe6822000 0x425>;
215 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH
216 GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH
217 GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH
218 GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
219 clocks = <&mstp3_clks SH73A0_CLK_IIC1>;
220 power-domains = <&pd_a3sp>;
225 #address-cells = <1>;
227 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
228 reg = <0xe6824000 0x425>;
229 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH
230 GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH
231 GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH
232 GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
233 clocks = <&mstp0_clks SH73A0_CLK_IIC2>;
234 power-domains = <&pd_a3sp>;
239 #address-cells = <1>;
241 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
242 reg = <0xe6826000 0x425>;
243 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH
244 GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH
245 GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH
246 GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
247 clocks = <&mstp4_clks SH73A0_CLK_IIC3>;
248 power-domains = <&pd_a3sp>;
253 #address-cells = <1>;
255 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
256 reg = <0xe6828000 0x425>;
257 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH
258 GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH
259 GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH
260 GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
261 clocks = <&mstp4_clks SH73A0_CLK_IIC4>;
262 power-domains = <&pd_c5>;
266 mmcif: mmc@e6bd0000 {
267 compatible = "renesas,sh-mmcif";
268 reg = <0xe6bd0000 0x100>;
269 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH
270 GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
271 clocks = <&mstp3_clks SH73A0_CLK_MMCIF0>;
272 power-domains = <&pd_a3sp>;
277 msiof0: spi@e6e20000 {
278 compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof";
279 reg = <0xe6e20000 0x0064>;
280 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
281 clocks = <&mstp0_clks SH73A0_CLK_MSIOF0>;
282 power-domains = <&pd_a3sp>;
283 #address-cells = <1>;
288 msiof1: spi@e6e10000 {
289 compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof";
290 reg = <0xe6e10000 0x0064>;
291 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
292 clocks = <&mstp2_clks SH73A0_CLK_MSIOF1>;
293 power-domains = <&pd_a3sp>;
294 #address-cells = <1>;
299 msiof2: spi@e6e00000 {
300 compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof";
301 reg = <0xe6e00000 0x0064>;
302 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
303 clocks = <&mstp2_clks SH73A0_CLK_MSIOF2>;
304 power-domains = <&pd_a3sp>;
305 #address-cells = <1>;
310 msiof3: spi@e6c90000 {
311 compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof";
312 reg = <0xe6c90000 0x0064>;
313 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
314 clocks = <&mstp2_clks SH73A0_CLK_MSIOF3>;
315 power-domains = <&pd_a3sp>;
316 #address-cells = <1>;
322 compatible = "renesas,sdhi-sh73a0";
323 reg = <0xee100000 0x100>;
324 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH
325 GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH
326 GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
327 clocks = <&mstp3_clks SH73A0_CLK_SDHI0>;
328 power-domains = <&pd_a3sp>;
333 /* SDHI1 and SDHI2 have no CD pins, no need for CD IRQ */
335 compatible = "renesas,sdhi-sh73a0";
336 reg = <0xee120000 0x100>;
337 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH
338 GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
339 clocks = <&mstp3_clks SH73A0_CLK_SDHI1>;
340 power-domains = <&pd_a3sp>;
341 toshiba,mmc-wrprotect-disable;
347 compatible = "renesas,sdhi-sh73a0";
348 reg = <0xee140000 0x100>;
349 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH
350 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
351 clocks = <&mstp3_clks SH73A0_CLK_SDHI2>;
352 power-domains = <&pd_a3sp>;
353 toshiba,mmc-wrprotect-disable;
358 scifa0: serial@e6c40000 {
359 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
360 reg = <0xe6c40000 0x100>;
361 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
362 clocks = <&mstp2_clks SH73A0_CLK_SCIFA0>;
364 power-domains = <&pd_a3sp>;
368 scifa1: serial@e6c50000 {
369 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
370 reg = <0xe6c50000 0x100>;
371 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
372 clocks = <&mstp2_clks SH73A0_CLK_SCIFA1>;
374 power-domains = <&pd_a3sp>;
378 scifa2: serial@e6c60000 {
379 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
380 reg = <0xe6c60000 0x100>;
381 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
382 clocks = <&mstp2_clks SH73A0_CLK_SCIFA2>;
384 power-domains = <&pd_a3sp>;
388 scifa3: serial@e6c70000 {
389 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
390 reg = <0xe6c70000 0x100>;
391 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
392 clocks = <&mstp2_clks SH73A0_CLK_SCIFA3>;
394 power-domains = <&pd_a3sp>;
398 scifa4: serial@e6c80000 {
399 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
400 reg = <0xe6c80000 0x100>;
401 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
402 clocks = <&mstp2_clks SH73A0_CLK_SCIFA4>;
404 power-domains = <&pd_a3sp>;
408 scifa5: serial@e6cb0000 {
409 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
410 reg = <0xe6cb0000 0x100>;
411 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
412 clocks = <&mstp2_clks SH73A0_CLK_SCIFA5>;
414 power-domains = <&pd_a3sp>;
418 scifa6: serial@e6cc0000 {
419 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
420 reg = <0xe6cc0000 0x100>;
421 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
422 clocks = <&mstp3_clks SH73A0_CLK_SCIFA6>;
424 power-domains = <&pd_a3sp>;
428 scifa7: serial@e6cd0000 {
429 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
430 reg = <0xe6cd0000 0x100>;
431 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
432 clocks = <&mstp2_clks SH73A0_CLK_SCIFA7>;
434 power-domains = <&pd_a3sp>;
438 scifb: serial@e6c30000 {
439 compatible = "renesas,scifb-sh73a0", "renesas,scifb";
440 reg = <0xe6c30000 0x100>;
441 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
442 clocks = <&mstp2_clks SH73A0_CLK_SCIFB>;
444 power-domains = <&pd_a3sp>;
449 compatible = "renesas,pfc-sh73a0";
450 reg = <0xe6050000 0x8000>,
455 <&pfc 0 0 119>, <&pfc 128 128 37>, <&pfc 192 192 91>,
457 interrupts-extended =
458 <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>,
459 <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>,
460 <&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>,
461 <&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>,
462 <&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>,
463 <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,
464 <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>,
465 <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>;
466 power-domains = <&pd_c5>;
469 sysc: system-controller@e6180000 {
470 compatible = "renesas,sysc-sh73a0", "renesas,sysc-rmobile";
471 reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>;
475 #address-cells = <1>;
477 #power-domain-cells = <0>;
481 #power-domain-cells = <0>;
486 #power-domain-cells = <0>;
491 #power-domain-cells = <0>;
496 #power-domain-cells = <0>;
501 #power-domain-cells = <0>;
506 #power-domain-cells = <0>;
511 #address-cells = <1>;
513 #power-domain-cells = <0>;
517 #power-domain-cells = <0>;
522 #power-domain-cells = <0>;
528 #address-cells = <1>;
530 #power-domain-cells = <0>;
534 #address-cells = <1>;
536 #power-domain-cells = <0>;
540 #address-cells = <1>;
542 #power-domain-cells = <0>;
549 #address-cells = <1>;
551 #power-domain-cells = <0>;
555 #power-domain-cells = <0>;
560 #power-domain-cells = <0>;
565 #address-cells = <1>;
567 #power-domain-cells = <0>;
571 #power-domain-cells = <0>;
579 sh_fsi2: sound@ec230000 {
580 #sound-dai-cells = <1>;
581 compatible = "renesas,fsi2-sh73a0", "renesas,sh_fsi2";
582 reg = <0xec230000 0x400>;
583 interrupts = <GIC_SPI 146 0x4>;
584 power-domains = <&pd_a4mp>;
589 compatible = "renesas,bsc-sh73a0", "renesas,bsc",
591 #address-cells = <1>;
593 ranges = <0 0 0x20000000>;
594 reg = <0xfec10000 0x400>;
595 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
597 power-domains = <&pd_a4s>;
601 #address-cells = <1>;
605 /* External root clocks */
607 compatible = "fixed-clock";
609 clock-frequency = <32768>;
612 compatible = "fixed-clock";
614 clock-frequency = <26000000>;
617 compatible = "fixed-clock";
621 compatible = "fixed-clock";
625 compatible = "fixed-clock";
627 clock-frequency = <0>;
630 compatible = "fixed-clock";
632 clock-frequency = <0>;
635 /* Special CPG clocks */
636 cpg_clocks: cpg_clocks@e6150000 {
637 compatible = "renesas,sh73a0-cpg-clocks";
638 reg = <0xe6150000 0x10000>;
639 clocks = <&extal1_clk>, <&extal2_clk>;
641 clock-output-names = "main", "pll0", "pll1", "pll2",
642 "pll3", "dsi0phy", "dsi1phy",
643 "zg", "m3", "b", "m1", "m2",
647 /* Variable factor clocks (DIV6) */
648 vclk1_clk: vclk1@e6150008 {
649 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
650 reg = <0xe6150008 4>;
651 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
652 <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>,
653 <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
657 vclk2_clk: vclk2@e615000c {
658 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
659 reg = <0xe615000c 4>;
660 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
661 <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>,
662 <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
666 vclk3_clk: vclk3@e615001c {
667 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
668 reg = <0xe615001c 4>;
669 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
670 <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>,
671 <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
675 zb_clk: zb_clk@e6150010 {
676 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
677 reg = <0xe6150010 4>;
678 clocks = <&pll1_div2_clk>, <0>,
679 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
681 clock-output-names = "zb";
683 flctl_clk: flctlck@e6150014 {
684 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
685 reg = <0xe6150014 4>;
686 clocks = <&pll1_div2_clk>, <0>,
687 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
690 sdhi0_clk: sdhi0ck@e6150074 {
691 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
692 reg = <0xe6150074 4>;
693 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
694 <&pll1_div13_clk>, <0>;
697 sdhi1_clk: sdhi1ck@e6150078 {
698 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
699 reg = <0xe6150078 4>;
700 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
701 <&pll1_div13_clk>, <0>;
704 sdhi2_clk: sdhi2ck@e615007c {
705 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
706 reg = <0xe615007c 4>;
707 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
708 <&pll1_div13_clk>, <0>;
711 fsia_clk: fsia@e6150018 {
712 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
713 reg = <0xe6150018 4>;
714 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
715 <&fsiack_clk>, <&fsiack_clk>;
718 fsib_clk: fsib@e6150090 {
719 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
720 reg = <0xe6150090 4>;
721 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
722 <&fsibck_clk>, <&fsibck_clk>;
725 sub_clk: sub@e6150080 {
726 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
727 reg = <0xe6150080 4>;
728 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
729 <&extal2_clk>, <&extal2_clk>;
732 spua_clk: spua@e6150084 {
733 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
734 reg = <0xe6150084 4>;
735 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
736 <&extal2_clk>, <&extal2_clk>;
739 spuv_clk: spuv@e6150094 {
740 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
741 reg = <0xe6150094 4>;
742 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
743 <&extal2_clk>, <&extal2_clk>;
746 msu_clk: msu@e6150088 {
747 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
748 reg = <0xe6150088 4>;
749 clocks = <&pll1_div2_clk>, <0>,
750 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
753 hsi_clk: hsi@e615008c {
754 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
755 reg = <0xe615008c 4>;
756 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
757 <&pll1_div7_clk>, <0>;
760 mfg1_clk: mfg1@e6150098 {
761 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
762 reg = <0xe6150098 4>;
763 clocks = <&pll1_div2_clk>, <0>,
764 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
767 mfg2_clk: mfg2@e615009c {
768 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
769 reg = <0xe615009c 4>;
770 clocks = <&pll1_div2_clk>, <0>,
771 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
774 dsit_clk: dsit@e6150060 {
775 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
776 reg = <0xe6150060 4>;
777 clocks = <&pll1_div2_clk>, <0>,
778 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
781 dsi0p_clk: dsi0pck@e6150064 {
782 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
783 reg = <0xe6150064 4>;
784 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
785 <&cpg_clocks SH73A0_CLK_MAIN>, <&extal2_clk>,
786 <&extcki_clk>, <0>, <0>, <0>;
790 /* Fixed factor clocks */
791 main_div2_clk: main_div2 {
792 compatible = "fixed-factor-clock";
793 clocks = <&cpg_clocks SH73A0_CLK_MAIN>;
798 pll1_div2_clk: pll1_div2 {
799 compatible = "fixed-factor-clock";
800 clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
805 pll1_div7_clk: pll1_div7 {
806 compatible = "fixed-factor-clock";
807 clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
812 pll1_div13_clk: pll1_div13 {
813 compatible = "fixed-factor-clock";
814 clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
820 compatible = "fixed-factor-clock";
821 clocks = <&cpg_clocks SH73A0_CLK_Z>;
828 mstp0_clks: mstp0_clks@e6150130 {
829 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
830 reg = <0xe6150130 4>, <0xe6150030 4>;
831 clocks = <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>;
834 SH73A0_CLK_IIC2 SH73A0_CLK_MSIOF0
839 mstp1_clks: mstp1_clks@e6150134 {
840 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
841 reg = <0xe6150134 4>, <0xe6150038 4>;
842 clocks = <&cpg_clocks SH73A0_CLK_B>,
843 <&cpg_clocks SH73A0_CLK_B>,
844 <&cpg_clocks SH73A0_CLK_B>,
845 <&cpg_clocks SH73A0_CLK_B>,
846 <&sub_clk>, <&cpg_clocks SH73A0_CLK_B>,
847 <&cpg_clocks SH73A0_CLK_HP>,
848 <&cpg_clocks SH73A0_CLK_ZG>,
849 <&cpg_clocks SH73A0_CLK_B>;
852 SH73A0_CLK_CEU1 SH73A0_CLK_CSI2_RX1
853 SH73A0_CLK_CEU0 SH73A0_CLK_CSI2_RX0
854 SH73A0_CLK_TMU0 SH73A0_CLK_DSITX0
855 SH73A0_CLK_IIC0 SH73A0_CLK_SGX
859 "ceu1", "csi2_rx1", "ceu0", "csi2_rx0",
860 "tmu0", "dsitx0", "iic0", "sgx", "lcdc0";
862 mstp2_clks: mstp2_clks@e6150138 {
863 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
864 reg = <0xe6150138 4>, <0xe6150040 4>;
865 clocks = <&sub_clk>, <&cpg_clocks SH73A0_CLK_HP>,
866 <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>,
867 <&sub_clk>, <&sub_clk>, <&sub_clk>,
868 <&sub_clk>, <&sub_clk>, <&sub_clk>,
869 <&sub_clk>, <&sub_clk>, <&sub_clk>;
872 SH73A0_CLK_SCIFA7 SH73A0_CLK_SY_DMAC
873 SH73A0_CLK_MP_DMAC SH73A0_CLK_MSIOF3
874 SH73A0_CLK_MSIOF1 SH73A0_CLK_SCIFA5
875 SH73A0_CLK_SCIFB SH73A0_CLK_MSIOF2
876 SH73A0_CLK_SCIFA0 SH73A0_CLK_SCIFA1
877 SH73A0_CLK_SCIFA2 SH73A0_CLK_SCIFA3
881 "scifa7", "sy_dmac", "mp_dmac", "msiof3",
882 "msiof1", "scifa5", "scifb", "msiof2",
883 "scifa0", "scifa1", "scifa2", "scifa3",
886 mstp3_clks: mstp3_clks@e615013c {
887 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
888 reg = <0xe615013c 4>, <0xe6150048 4>;
889 clocks = <&sub_clk>, <&extalr_clk>,
890 <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>,
891 <&cpg_clocks SH73A0_CLK_HP>,
892 <&cpg_clocks SH73A0_CLK_HP>, <&flctl_clk>,
893 <&sdhi0_clk>, <&sdhi1_clk>,
894 <&cpg_clocks SH73A0_CLK_HP>, <&sdhi2_clk>,
895 <&main_div2_clk>, <&main_div2_clk>,
896 <&main_div2_clk>, <&main_div2_clk>,
900 SH73A0_CLK_SCIFA6 SH73A0_CLK_CMT1
901 SH73A0_CLK_FSI SH73A0_CLK_IRDA
902 SH73A0_CLK_IIC1 SH73A0_CLK_USB SH73A0_CLK_FLCTL
903 SH73A0_CLK_SDHI0 SH73A0_CLK_SDHI1
904 SH73A0_CLK_MMCIF0 SH73A0_CLK_SDHI2
905 SH73A0_CLK_TPU0 SH73A0_CLK_TPU1
906 SH73A0_CLK_TPU2 SH73A0_CLK_TPU3
910 "scifa6", "cmt1", "fsi", "irda", "iic1",
911 "usb", "flctl", "sdhi0", "sdhi1", "mmcif0", "sdhi2",
912 "tpu0", "tpu1", "tpu2", "tpu3", "tpu4";
914 mstp4_clks: mstp4_clks@e6150140 {
915 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
916 reg = <0xe6150140 4>, <0xe615004c 4>;
917 clocks = <&cpg_clocks SH73A0_CLK_HP>,
918 <&cpg_clocks SH73A0_CLK_HP>, <&extalr_clk>;
921 SH73A0_CLK_IIC3 SH73A0_CLK_IIC4
925 "iic3", "iic4", "keysc";
927 mstp5_clks: mstp5_clks@e6150144 {
928 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
929 reg = <0xe6150144 4>, <0xe615003c 4>;
930 clocks = <&cpg_clocks SH73A0_CLK_HP>;