2 * sama5d2.dtsi - Device Tree Include file for SAMA5D2 family SoC
4 * Copyright (C) 2015 Atmel,
5 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com>
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
12 * a) This file is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
17 * This file is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
24 * b) Permission is hereby granted, free of charge, to any person
25 * obtaining a copy of this software and associated documentation
26 * files (the "Software"), to deal in the Software without
27 * restriction, including without limitation the rights to use,
28 * copy, modify, merge, publish, distribute, sublicense, and/or
29 * sell copies of the Software, and to permit persons to whom the
30 * Software is furnished to do so, subject to the following
33 * The above copyright notice and this permission notice shall be
34 * included in all copies or substantial portions of the Software.
36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 * OTHER DEALINGS IN THE SOFTWARE.
46 #include "skeleton.dtsi"
47 #include <dt-bindings/dma/at91.h>
48 #include <dt-bindings/interrupt-controller/irq.h>
49 #include <dt-bindings/clock/at91.h>
52 model = "Atmel SAMA5D2 family SoC";
53 compatible = "atmel,sama5d2";
54 interrupt-parent = <&aic>;
69 compatible = "arm,cortex-a5";
71 next-level-cache = <&L2>;
76 compatible = "arm,cortex-a5-pmu";
77 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 0>;
81 compatible = "arm,coresight-etb10", "arm,primecell";
82 reg = <0x740000 0x1000>;
85 clock-names = "apb_pclk";
90 remote-endpoint = <&etm_out>;
96 compatible = "arm,coresight-etm3x", "arm,primecell";
97 reg = <0x73C000 0x1000>;
100 clock-names = "apb_pclk";
104 remote-endpoint = <&etb_in>;
110 reg = <0x20000000 0x20000000>;
114 slow_xtal: slow_xtal {
115 compatible = "fixed-clock";
117 clock-frequency = <0>;
120 main_xtal: main_xtal {
121 compatible = "fixed-clock";
123 clock-frequency = <0>;
127 ns_sram: sram@00200000 {
128 compatible = "mmio-sram";
129 reg = <0x00200000 0x20000>;
133 compatible = "simple-bus";
134 #address-cells = <1>;
138 usb0: gadget@00300000 {
139 #address-cells = <1>;
141 compatible = "atmel,sama5d3-udc";
142 reg = <0x00300000 0x100000
144 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 2>;
145 clocks = <&udphs_clk>, <&utmi>;
146 clock-names = "pclk", "hclk";
151 atmel,fifo-size = <64>;
152 atmel,nb-banks = <1>;
157 atmel,fifo-size = <1024>;
158 atmel,nb-banks = <3>;
165 atmel,fifo-size = <1024>;
166 atmel,nb-banks = <3>;
173 atmel,fifo-size = <1024>;
174 atmel,nb-banks = <2>;
181 atmel,fifo-size = <1024>;
182 atmel,nb-banks = <2>;
189 atmel,fifo-size = <1024>;
190 atmel,nb-banks = <2>;
197 atmel,fifo-size = <1024>;
198 atmel,nb-banks = <2>;
205 atmel,fifo-size = <1024>;
206 atmel,nb-banks = <2>;
213 atmel,fifo-size = <1024>;
214 atmel,nb-banks = <2>;
220 atmel,fifo-size = <1024>;
221 atmel,nb-banks = <2>;
227 atmel,fifo-size = <1024>;
228 atmel,nb-banks = <2>;
234 atmel,fifo-size = <1024>;
235 atmel,nb-banks = <2>;
241 atmel,fifo-size = <1024>;
242 atmel,nb-banks = <2>;
248 atmel,fifo-size = <1024>;
249 atmel,nb-banks = <2>;
255 atmel,fifo-size = <1024>;
256 atmel,nb-banks = <2>;
262 atmel,fifo-size = <1024>;
263 atmel,nb-banks = <2>;
268 usb1: ohci@00400000 {
269 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
270 reg = <0x00400000 0x100000>;
271 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>;
272 clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
273 clock-names = "ohci_clk", "hclk", "uhpck";
277 usb2: ehci@00500000 {
278 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
279 reg = <0x00500000 0x100000>;
280 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>;
281 clocks = <&utmi>, <&uhphs_clk>;
282 clock-names = "usb_clk", "ehci_clk";
286 L2: cache-controller@00a00000 {
287 compatible = "arm,pl310-cache";
288 reg = <0x00a00000 0x1000>;
289 interrupts = <63 IRQ_TYPE_LEVEL_HIGH 4>;
294 nand0: nand@80000000 {
295 compatible = "atmel,sama5d2-nand";
296 #address-cells = <1>;
299 reg = < /* EBI CS3 */
300 0x80000000 0x08000000
302 0xf8014070 0x00000490
303 /* SMC PMECC Error Location regs */
304 0xf8014500 0x00000200
305 /* ROM Galois tables */
306 0x00040000 0x00018000
308 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 6>;
309 atmel,nand-addr-offset = <21>;
310 atmel,nand-cmd-offset = <22>;
313 atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
317 compatible = "atmel,sama5d3-nfc";
318 #address-cells = <1>;
320 reg = < /* NFC Command Registers */
321 0xc0000000 0x08000000
323 0xf8014000 0x00000070
325 0x00100000 0x00100000
327 clocks = <&hsmc_clk>;
332 sdmmc0: sdio-host@a0000000 {
333 compatible = "atmel,sama5d2-sdhci";
334 reg = <0xa0000000 0x300>;
335 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
336 clocks = <&sdmmc0_hclk>, <&sdmmc0_gclk>, <&main>;
337 clock-names = "hclock", "multclk", "baseclk";
341 sdmmc1: sdio-host@b0000000 {
342 compatible = "atmel,sama5d2-sdhci";
343 reg = <0xb0000000 0x300>;
344 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 0>;
345 clocks = <&sdmmc1_hclk>, <&sdmmc1_gclk>, <&main>;
346 clock-names = "hclock", "multclk", "baseclk";
351 compatible = "simple-bus";
352 #address-cells = <1>;
356 hlcdc: hlcdc@f0000000 {
357 compatible = "atmel,sama5d2-hlcdc";
358 reg = <0xf0000000 0x2000>;
359 interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>;
360 clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
361 clock-names = "periph_clk","sys_clk", "slow_clk";
364 hlcdc-display-controller {
365 compatible = "atmel,hlcdc-display-controller";
366 #address-cells = <1>;
370 #address-cells = <1>;
376 hlcdc_pwm: hlcdc-pwm {
377 compatible = "atmel,hlcdc-pwm";
382 ramc0: ramc@f000c000 {
383 compatible = "atmel,sama5d3-ddramc";
384 reg = <0xf000c000 0x200>;
385 clocks = <&ddrck>, <&mpddr_clk>;
386 clock-names = "ddrck", "mpddr";
389 dma0: dma-controller@f0010000 {
390 compatible = "atmel,sama5d4-dma";
391 reg = <0xf0010000 0x1000>;
392 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>;
394 clocks = <&dma0_clk>;
395 clock-names = "dma_clk";
399 compatible = "atmel,sama5d2-pmc", "syscon";
400 reg = <0xf0014000 0x160>;
401 interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>;
402 interrupt-controller;
403 #address-cells = <1>;
405 #interrupt-cells = <1>;
407 main_rc_osc: main_rc_osc {
408 compatible = "atmel,at91sam9x5-clk-main-rc-osc";
410 interrupt-parent = <&pmc>;
411 interrupts = <AT91_PMC_MOSCRCS>;
412 clock-frequency = <12000000>;
413 clock-accuracy = <100000000>;
417 compatible = "atmel,at91rm9200-clk-main-osc";
419 interrupt-parent = <&pmc>;
420 interrupts = <AT91_PMC_MOSCS>;
421 clocks = <&main_xtal>;
425 compatible = "atmel,at91sam9x5-clk-main";
427 interrupt-parent = <&pmc>;
428 interrupts = <AT91_PMC_MOSCSELS>;
429 clocks = <&main_rc_osc &main_osc>;
433 compatible = "atmel,sama5d3-clk-pll";
435 interrupt-parent = <&pmc>;
436 interrupts = <AT91_PMC_LOCKA>;
439 atmel,clk-input-range = <12000000 12000000>;
440 #atmel,pll-clk-output-range-cells = <4>;
441 atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>;
445 compatible = "atmel,at91sam9x5-clk-plldiv";
451 compatible = "atmel,at91sam9x5-clk-utmi";
453 interrupt-parent = <&pmc>;
454 interrupts = <AT91_PMC_LOCKU>;
459 compatible = "atmel,at91sam9x5-clk-master";
461 interrupt-parent = <&pmc>;
462 interrupts = <AT91_PMC_MCKRDY>;
463 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
464 atmel,clk-output-range = <124000000 166000000>;
465 atmel,clk-divisors = <1 2 4 3>;
470 compatible = "atmel,sama5d4-clk-h32mx";
475 compatible = "atmel,at91sam9x5-clk-usb";
477 clocks = <&plladiv>, <&utmi>;
481 compatible = "atmel,at91sam9x5-clk-programmable";
482 #address-cells = <1>;
484 interrupt-parent = <&pmc>;
485 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
490 interrupts = <AT91_PMC_PCKRDY(0)>;
496 interrupts = <AT91_PMC_PCKRDY(1)>;
502 interrupts = <AT91_PMC_PCKRDY(2)>;
507 compatible = "atmel,at91rm9200-clk-system";
508 #address-cells = <1>;
561 compatible = "atmel,at91sam9x5-clk-peripheral";
562 #address-cells = <1>;
566 macb0_clk: macb0_clk {
569 atmel,clk-output-range = <0 83000000>;
575 atmel,clk-output-range = <0 83000000>;
578 matrix1_clk: matrix1_clk {
591 atmel,clk-output-range = <0 83000000>;
597 atmel,clk-output-range = <0 83000000>;
603 atmel,clk-output-range = <0 83000000>;
609 atmel,clk-output-range = <0 83000000>;
615 atmel,clk-output-range = <0 83000000>;
621 atmel,clk-output-range = <0 83000000>;
624 uart0_clk: uart0_clk {
627 atmel,clk-output-range = <0 83000000>;
630 uart1_clk: uart1_clk {
633 atmel,clk-output-range = <0 83000000>;
636 uart2_clk: uart2_clk {
639 atmel,clk-output-range = <0 83000000>;
642 uart3_clk: uart3_clk {
645 atmel,clk-output-range = <0 83000000>;
648 uart4_clk: uart4_clk {
651 atmel,clk-output-range = <0 83000000>;
657 atmel,clk-output-range = <0 83000000>;
663 atmel,clk-output-range = <0 83000000>;
669 atmel,clk-output-range = <0 83000000>;
675 atmel,clk-output-range = <0 83000000>;
681 atmel,clk-output-range = <0 83000000>;
687 atmel,clk-output-range = <0 83000000>;
693 atmel,clk-output-range = <0 83000000>;
699 atmel,clk-output-range = <0 83000000>;
702 uhphs_clk: uhphs_clk {
705 atmel,clk-output-range = <0 83000000>;
708 udphs_clk: udphs_clk {
711 atmel,clk-output-range = <0 83000000>;
717 atmel,clk-output-range = <0 83000000>;
723 atmel,clk-output-range = <0 83000000>;
729 atmel,clk-output-range = <0 83000000>;
732 pdmic_clk: pdmic_clk {
735 atmel,clk-output-range = <0 83000000>;
741 atmel,clk-output-range = <0 83000000>;
747 atmel,clk-output-range = <0 83000000>;
750 classd_clk: classd_clk {
753 atmel,clk-output-range = <0 83000000>;
758 compatible = "atmel,at91sam9x5-clk-peripheral";
759 #address-cells = <1>;
788 mpddr_clk: mpddr_clk {
793 matrix0_clk: matrix0_clk {
798 sdmmc0_hclk: sdmmc0_hclk {
803 sdmmc1_hclk: sdmmc1_hclk {
818 qspi0_clk: qspi0_clk {
823 qspi1_clk: qspi1_clk {
830 compatible = "atmel,sama5d2-clk-generated";
831 #address-cells = <1>;
833 interrupt-parent = <&pmc>;
834 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
836 sdmmc0_gclk: sdmmc0_gclk {
841 sdmmc1_gclk: sdmmc1_gclk {
846 tcb0_gclk: tcb0_gclk {
849 atmel,clk-output-range = <0 83000000>;
852 tcb1_gclk: tcb1_gclk {
855 atmel,clk-output-range = <0 83000000>;
861 atmel,clk-output-range = <0 83000000>;
864 pdmic_gclk: pdmic_gclk {
869 i2s0_gclk: i2s0_gclk {
874 i2s1_gclk: i2s1_gclk {
882 compatible = "atmel,at91sam9g46-sha";
883 reg = <0xf0028000 0x100>;
884 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
886 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
887 AT91_XDMAC_DT_PERID(30))>;
890 clock-names = "sha_clk";
895 compatible = "atmel,at91sam9g46-aes";
896 reg = <0xf002c000 0x100>;
897 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>;
899 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
900 AT91_XDMAC_DT_PERID(26))>,
902 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
903 AT91_XDMAC_DT_PERID(27))>;
904 dma-names = "tx", "rx";
906 clock-names = "aes_clk";
911 compatible = "atmel,at91rm9200-spi";
912 reg = <0xf8000000 0x100>;
913 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>;
915 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
916 AT91_XDMAC_DT_PERID(6))>,
918 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
919 AT91_XDMAC_DT_PERID(7))>;
920 dma-names = "tx", "rx";
921 clocks = <&spi0_clk>;
922 clock-names = "spi_clk";
923 atmel,fifo-size = <16>;
924 #address-cells = <1>;
929 macb0: ethernet@f8008000 {
930 compatible = "atmel,sama5d2-gem";
931 reg = <0xf8008000 0x1000>;
932 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 0 */
933 66 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 1 */
934 67 IRQ_TYPE_LEVEL_HIGH 3>; /* Queue 2 */
935 #address-cells = <1>;
937 clocks = <&macb0_clk>, <&macb0_clk>;
938 clock-names = "hclk", "pclk";
942 tcb0: timer@f800c000 {
943 compatible = "atmel,at91sam9x5-tcb";
944 reg = <0xf800c000 0x100>;
945 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;
946 clocks = <&tcb0_clk>, <&clk32k>;
947 clock-names = "t0_clk", "slow_clk";
950 tcb1: timer@f8010000 {
951 compatible = "atmel,at91sam9x5-tcb";
952 reg = <0xf8010000 0x100>;
953 interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
954 clocks = <&tcb1_clk>, <&clk32k>;
955 clock-names = "t0_clk", "slow_clk";
958 pdmic: pdmic@f8018000 {
959 compatible = "atmel,sama5d2-pdmic";
960 reg = <0xf8018000 0x124>;
961 interrupts = <48 IRQ_TYPE_LEVEL_HIGH 7>;
963 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
964 | AT91_XDMAC_DT_PERID(50))>;
966 clocks = <&pdmic_clk>, <&pdmic_gclk>;
967 clock-names = "pclk", "gclk";
971 uart0: serial@f801c000 {
972 compatible = "atmel,at91sam9260-usart";
973 reg = <0xf801c000 0x100>;
974 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 7>;
976 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
977 AT91_XDMAC_DT_PERID(35))>,
979 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
980 AT91_XDMAC_DT_PERID(36))>;
981 dma-names = "tx", "rx";
982 clocks = <&uart0_clk>;
983 clock-names = "usart";
987 uart1: serial@f8020000 {
988 compatible = "atmel,at91sam9260-usart";
989 reg = <0xf8020000 0x100>;
990 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 7>;
992 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
993 AT91_XDMAC_DT_PERID(37))>,
995 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
996 AT91_XDMAC_DT_PERID(38))>;
997 dma-names = "tx", "rx";
998 clocks = <&uart1_clk>;
999 clock-names = "usart";
1000 status = "disabled";
1003 uart2: serial@f8024000 {
1004 compatible = "atmel,at91sam9260-usart";
1005 reg = <0xf8024000 0x100>;
1006 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 7>;
1008 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1009 AT91_XDMAC_DT_PERID(39))>,
1011 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1012 AT91_XDMAC_DT_PERID(40))>;
1013 dma-names = "tx", "rx";
1014 clocks = <&uart2_clk>;
1015 clock-names = "usart";
1016 status = "disabled";
1019 i2c0: i2c@f8028000 {
1020 compatible = "atmel,sama5d2-i2c";
1021 reg = <0xf8028000 0x100>;
1022 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 7>;
1024 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1025 AT91_XDMAC_DT_PERID(0))>,
1027 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1028 AT91_XDMAC_DT_PERID(1))>;
1029 dma-names = "tx", "rx";
1030 #address-cells = <1>;
1032 clocks = <&twi0_clk>;
1033 status = "disabled";
1037 compatible = "atmel,sama5d2-sfr", "syscon";
1038 reg = <0xf8030000 0x98>;
1041 flx0: flexcom@f8034000 {
1042 compatible = "atmel,sama5d2-flexcom";
1043 reg = <0xf8034000 0x200>;
1044 clocks = <&flx0_clk>;
1045 #address-cells = <1>;
1047 ranges = <0x0 0xf8034000 0x800>;
1048 status = "disabled";
1051 flx1: flexcom@f8038000 {
1052 compatible = "atmel,sama5d2-flexcom";
1053 reg = <0xf8038000 0x200>;
1054 clocks = <&flx1_clk>;
1055 #address-cells = <1>;
1057 ranges = <0x0 0xf8038000 0x800>;
1058 status = "disabled";
1062 compatible = "atmel,sama5d3-rstc";
1063 reg = <0xf8048000 0x10>;
1068 compatible = "atmel,sama5d2-shdwc";
1069 reg = <0xf8048010 0x10>;
1071 #address-cells = <1>;
1073 atmel,wakeup-rtc-timer;
1076 pit: timer@f8048030 {
1077 compatible = "atmel,at91sam9260-pit";
1078 reg = <0xf8048030 0x10>;
1079 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
1084 compatible = "atmel,sama5d4-wdt";
1085 reg = <0xf8048040 0x10>;
1086 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>;
1088 status = "disabled";
1092 compatible = "atmel,at91sam9x5-sckc";
1093 reg = <0xf8048050 0x4>;
1095 slow_rc_osc: slow_rc_osc {
1096 compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
1098 clock-frequency = <32768>;
1099 clock-accuracy = <250000000>;
1100 atmel,startup-time-usec = <75>;
1103 slow_osc: slow_osc {
1104 compatible = "atmel,at91sam9x5-clk-slow-osc";
1106 clocks = <&slow_xtal>;
1107 atmel,startup-time-usec = <1200000>;
1111 compatible = "atmel,at91sam9x5-clk-slow";
1113 clocks = <&slow_rc_osc &slow_osc>;
1118 compatible = "atmel,at91rm9200-rtc";
1119 reg = <0xf80480b0 0x30>;
1120 interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>;
1124 spi1: spi@fc000000 {
1125 compatible = "atmel,at91rm9200-spi";
1126 reg = <0xfc000000 0x100>;
1127 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>;
1129 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1130 AT91_XDMAC_DT_PERID(8))>,
1132 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1133 AT91_XDMAC_DT_PERID(9))>;
1134 dma-names = "tx", "rx";
1135 clocks = <&spi1_clk>;
1136 clock-names = "spi_clk";
1137 atmel,fifo-size = <16>;
1138 #address-cells = <1>;
1140 status = "disabled";
1143 uart3: serial@fc008000 {
1144 compatible = "atmel,at91sam9260-usart";
1145 reg = <0xfc008000 0x100>;
1146 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 7>;
1148 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1149 AT91_XDMAC_DT_PERID(41))>,
1151 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1152 AT91_XDMAC_DT_PERID(42))>;
1153 dma-names = "tx", "rx";
1154 clocks = <&uart3_clk>;
1155 clock-names = "usart";
1156 status = "disabled";
1159 uart4: serial@fc00c000 {
1160 compatible = "atmel,at91sam9260-usart";
1161 reg = <0xfc00c000 0x100>;
1163 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1164 AT91_XDMAC_DT_PERID(43))>,
1166 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1167 AT91_XDMAC_DT_PERID(44))>;
1168 dma-names = "tx", "rx";
1169 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 7>;
1170 clocks = <&uart4_clk>;
1171 clock-names = "usart";
1172 status = "disabled";
1175 flx2: flexcom@fc010000 {
1176 compatible = "atmel,sama5d2-flexcom";
1177 reg = <0xfc010000 0x200>;
1178 clocks = <&flx2_clk>;
1179 #address-cells = <1>;
1181 ranges = <0x0 0xfc010000 0x800>;
1182 status = "disabled";
1185 flx3: flexcom@fc014000 {
1186 compatible = "atmel,sama5d2-flexcom";
1187 reg = <0xfc014000 0x200>;
1188 clocks = <&flx3_clk>;
1189 #address-cells = <1>;
1191 ranges = <0x0 0xfc014000 0x800>;
1192 status = "disabled";
1195 flx4: flexcom@fc018000 {
1196 compatible = "atmel,sama5d2-flexcom";
1197 reg = <0xfc018000 0x200>;
1198 clocks = <&flx4_clk>;
1199 #address-cells = <1>;
1201 ranges = <0x0 0xfc018000 0x800>;
1202 status = "disabled";
1206 compatible = "atmel,at91sam9g45-trng";
1207 reg = <0xfc01c000 0x100>;
1208 interrupts = <47 IRQ_TYPE_LEVEL_HIGH 0>;
1209 clocks = <&trng_clk>;
1212 aic: interrupt-controller@fc020000 {
1213 #interrupt-cells = <3>;
1214 compatible = "atmel,sama5d2-aic";
1215 interrupt-controller;
1216 reg = <0xfc020000 0x200>;
1217 atmel,external-irqs = <49>;
1220 i2c1: i2c@fc028000 {
1221 compatible = "atmel,sama5d2-i2c";
1222 reg = <0xfc028000 0x100>;
1223 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 7>;
1225 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1226 AT91_XDMAC_DT_PERID(2))>,
1228 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1229 AT91_XDMAC_DT_PERID(3))>;
1230 dma-names = "tx", "rx";
1231 #address-cells = <1>;
1233 clocks = <&twi1_clk>;
1234 status = "disabled";
1238 compatible = "atmel,sama5d2-adc";
1239 reg = <0xfc030000 0x100>;
1240 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 7>;
1241 clocks = <&adc_clk>;
1242 clock-names = "adc_clk";
1243 atmel,min-sample-rate-hz = <200000>;
1244 atmel,max-sample-rate-hz = <20000000>;
1245 atmel,startup-time-ms = <4>;
1246 status = "disabled";
1249 pioA: pinctrl@fc038000 {
1250 compatible = "atmel,sama5d2-pinctrl";
1251 reg = <0xfc038000 0x600>;
1252 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 7>,
1253 <68 IRQ_TYPE_LEVEL_HIGH 7>,
1254 <69 IRQ_TYPE_LEVEL_HIGH 7>,
1255 <70 IRQ_TYPE_LEVEL_HIGH 7>;
1256 interrupt-controller;
1257 #interrupt-cells = <2>;
1260 clocks = <&pioA_clk>;
1264 compatible = "atmel,at91sam9g46-tdes";
1265 reg = <0xfc044000 0x100>;
1266 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
1268 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1269 AT91_XDMAC_DT_PERID(28))>,
1271 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1272 AT91_XDMAC_DT_PERID(29))>;
1273 dma-names = "tx", "rx";
1274 clocks = <&tdes_clk>;
1275 clock-names = "tdes_clk";
1280 compatible = "atmel,sama5d2-chipid";
1281 reg = <0xfc069000 0x8>;