1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2013 MundoReader S.L.
4 * Author: Heiko Stuebner <heiko@sntech.de>
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/soc/rockchip,boot-mode.h>
15 interrupt-parent = <&gic>;
33 compatible = "fixed-clock";
34 clock-frequency = <24000000>;
36 clock-output-names = "xin24m";
40 compatible = "arm,mali-400";
41 reg = <0x10090000 0x10000>;
42 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
43 clock-names = "bus", "core";
44 assigned-clocks = <&cru ACLK_GPU>;
45 assigned-clock-rates = <100000000>;
46 resets = <&cru SRST_GPU>;
50 vpu: video-codec@10104000 {
51 compatible = "rockchip,rk3066-vpu";
52 reg = <0x10104000 0x800>;
53 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
54 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
55 interrupt-names = "vepu", "vdpu";
56 clocks = <&cru ACLK_VDPU>, <&cru HCLK_VDPU>,
57 <&cru ACLK_VEPU>, <&cru HCLK_VEPU>;
58 clock-names = "aclk_vdpu", "hclk_vdpu",
59 "aclk_vepu", "hclk_vepu";
62 L2: cache-controller@10138000 {
63 compatible = "arm,pl310-cache";
64 reg = <0x10138000 0x1000>;
70 compatible = "arm,cortex-a9-scu";
71 reg = <0x1013c000 0x100>;
74 global_timer: global-timer@1013c200 {
75 compatible = "arm,cortex-a9-global-timer";
76 reg = <0x1013c200 0x20>;
77 interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
78 clocks = <&cru CORE_PERI>;
80 /* The clock source and the sched_clock provided by the arm_global_timer
81 * on Rockchip rk3066a/rk3188 are quite unstable because their rates
82 * depend on the CPU frequency.
83 * Keep the arm_global_timer disabled in order to have the
84 * DW_APB_TIMER (rk3066a) or ROCKCHIP_TIMER (rk3188) selected by default.
88 local_timer: local-timer@1013c600 {
89 compatible = "arm,cortex-a9-twd-timer";
90 reg = <0x1013c600 0x20>;
91 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
92 clocks = <&cru CORE_PERI>;
95 gic: interrupt-controller@1013d000 {
96 compatible = "arm,cortex-a9-gic";
98 #interrupt-cells = <3>;
99 reg = <0x1013d000 0x1000>,
103 uart0: serial@10124000 {
104 compatible = "snps,dw-apb-uart";
105 reg = <0x10124000 0x400>;
106 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
109 clock-names = "baudclk", "apb_pclk";
110 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
114 uart1: serial@10126000 {
115 compatible = "snps,dw-apb-uart";
116 reg = <0x10126000 0x400>;
117 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
120 clock-names = "baudclk", "apb_pclk";
121 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
125 qos_gpu: qos@1012d000 {
126 compatible = "rockchip,rk3066-qos", "syscon";
127 reg = <0x1012d000 0x20>;
130 qos_vpu: qos@1012e000 {
131 compatible = "rockchip,rk3066-qos", "syscon";
132 reg = <0x1012e000 0x20>;
135 qos_lcdc0: qos@1012f000 {
136 compatible = "rockchip,rk3066-qos", "syscon";
137 reg = <0x1012f000 0x20>;
140 qos_cif0: qos@1012f080 {
141 compatible = "rockchip,rk3066-qos", "syscon";
142 reg = <0x1012f080 0x20>;
145 qos_ipp: qos@1012f100 {
146 compatible = "rockchip,rk3066-qos", "syscon";
147 reg = <0x1012f100 0x20>;
150 qos_lcdc1: qos@1012f180 {
151 compatible = "rockchip,rk3066-qos", "syscon";
152 reg = <0x1012f180 0x20>;
155 qos_cif1: qos@1012f200 {
156 compatible = "rockchip,rk3066-qos", "syscon";
157 reg = <0x1012f200 0x20>;
160 qos_rga: qos@1012f280 {
161 compatible = "rockchip,rk3066-qos", "syscon";
162 reg = <0x1012f280 0x20>;
165 usb_otg: usb@10180000 {
166 compatible = "rockchip,rk3066-usb", "snps,dwc2";
167 reg = <0x10180000 0x40000>;
168 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
169 clocks = <&cru HCLK_OTG0>;
172 g-np-tx-fifo-size = <16>;
173 g-rx-fifo-size = <275>;
174 g-tx-fifo-size = <256 128 128 64 64 32>;
176 phy-names = "usb2-phy";
180 usb_host: usb@101c0000 {
181 compatible = "snps,dwc2";
182 reg = <0x101c0000 0x40000>;
183 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
184 clocks = <&cru HCLK_OTG1>;
188 phy-names = "usb2-phy";
192 emac: ethernet@10204000 {
193 compatible = "snps,arc-emac";
194 reg = <0x10204000 0x3c>;
195 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
197 rockchip,grf = <&grf>;
199 clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>;
200 clock-names = "hclk", "macref";
208 compatible = "rockchip,rk2928-dw-mshc";
209 reg = <0x10214000 0x1000>;
210 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
211 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
212 clock-names = "biu", "ciu";
216 resets = <&cru SRST_SDMMC>;
217 reset-names = "reset";
222 compatible = "rockchip,rk2928-dw-mshc";
223 reg = <0x10218000 0x1000>;
224 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
225 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>;
226 clock-names = "biu", "ciu";
230 resets = <&cru SRST_SDIO>;
231 reset-names = "reset";
236 compatible = "rockchip,rk2928-dw-mshc";
237 reg = <0x1021c000 0x1000>;
238 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
239 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
240 clock-names = "biu", "ciu";
244 resets = <&cru SRST_EMMC>;
245 reset-names = "reset";
249 nfc: nand-controller@10500000 {
250 compatible = "rockchip,rk2928-nfc";
251 reg = <0x10500000 0x4000>;
252 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
253 clocks = <&cru HCLK_NANDC0>;
259 compatible = "rockchip,rk3066-pmu", "syscon", "simple-mfd";
260 reg = <0x20004000 0x100>;
263 compatible = "syscon-reboot-mode";
265 mode-normal = <BOOT_NORMAL>;
266 mode-recovery = <BOOT_RECOVERY>;
267 mode-bootloader = <BOOT_FASTBOOT>;
268 mode-loader = <BOOT_BL_DOWNLOAD>;
273 compatible = "syscon", "simple-mfd";
274 reg = <0x20008000 0x200>;
277 dmac1_s: dma-controller@20018000 {
278 compatible = "arm,pl330", "arm,primecell";
279 reg = <0x20018000 0x4000>;
280 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
281 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
283 arm,pl330-broken-no-flushp;
284 arm,pl330-periph-burst;
285 clocks = <&cru ACLK_DMA1>;
286 clock-names = "apb_pclk";
289 dmac1_ns: dma-controller@2001c000 {
290 compatible = "arm,pl330", "arm,primecell";
291 reg = <0x2001c000 0x4000>;
292 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
293 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
295 arm,pl330-broken-no-flushp;
296 arm,pl330-periph-burst;
297 clocks = <&cru ACLK_DMA1>;
298 clock-names = "apb_pclk";
303 compatible = "rockchip,rk3066-i2c";
304 reg = <0x2002d000 0x1000>;
305 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
306 #address-cells = <1>;
309 rockchip,grf = <&grf>;
312 clocks = <&cru PCLK_I2C0>;
318 compatible = "rockchip,rk3066-i2c";
319 reg = <0x2002f000 0x1000>;
320 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
321 #address-cells = <1>;
324 rockchip,grf = <&grf>;
326 clocks = <&cru PCLK_I2C1>;
333 compatible = "rockchip,rk2928-pwm";
334 reg = <0x20030000 0x10>;
336 clocks = <&cru PCLK_PWM01>;
341 compatible = "rockchip,rk2928-pwm";
342 reg = <0x20030010 0x10>;
344 clocks = <&cru PCLK_PWM01>;
348 wdt: watchdog@2004c000 {
349 compatible = "snps,dw-wdt";
350 reg = <0x2004c000 0x100>;
351 clocks = <&cru PCLK_WDT>;
352 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
357 compatible = "rockchip,rk2928-pwm";
358 reg = <0x20050020 0x10>;
360 clocks = <&cru PCLK_PWM23>;
365 compatible = "rockchip,rk2928-pwm";
366 reg = <0x20050030 0x10>;
368 clocks = <&cru PCLK_PWM23>;
373 compatible = "rockchip,rk3066-i2c";
374 reg = <0x20056000 0x1000>;
375 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
376 #address-cells = <1>;
379 rockchip,grf = <&grf>;
381 clocks = <&cru PCLK_I2C2>;
388 compatible = "rockchip,rk3066-i2c";
389 reg = <0x2005a000 0x1000>;
390 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
391 #address-cells = <1>;
394 rockchip,grf = <&grf>;
396 clocks = <&cru PCLK_I2C3>;
403 compatible = "rockchip,rk3066-i2c";
404 reg = <0x2005e000 0x1000>;
405 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
406 #address-cells = <1>;
409 rockchip,grf = <&grf>;
411 clocks = <&cru PCLK_I2C4>;
417 uart2: serial@20064000 {
418 compatible = "snps,dw-apb-uart";
419 reg = <0x20064000 0x400>;
420 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
423 clock-names = "baudclk", "apb_pclk";
424 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
428 uart3: serial@20068000 {
429 compatible = "snps,dw-apb-uart";
430 reg = <0x20068000 0x400>;
431 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
434 clock-names = "baudclk", "apb_pclk";
435 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
439 saradc: saradc@2006c000 {
440 compatible = "rockchip,saradc";
441 reg = <0x2006c000 0x100>;
442 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
443 #io-channel-cells = <1>;
444 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
445 clock-names = "saradc", "apb_pclk";
446 resets = <&cru SRST_SARADC>;
447 reset-names = "saradc-apb";
452 compatible = "rockchip,rk3066-spi";
453 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
454 clock-names = "spiclk", "apb_pclk";
455 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
456 reg = <0x20070000 0x1000>;
457 #address-cells = <1>;
459 dmas = <&dmac2 10>, <&dmac2 11>;
460 dma-names = "tx", "rx";
465 compatible = "rockchip,rk3066-spi";
466 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
467 clock-names = "spiclk", "apb_pclk";
468 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
469 reg = <0x20074000 0x1000>;
470 #address-cells = <1>;
472 dmas = <&dmac2 12>, <&dmac2 13>;
473 dma-names = "tx", "rx";
477 dmac2: dma-controller@20078000 {
478 compatible = "arm,pl330", "arm,primecell";
479 reg = <0x20078000 0x4000>;
480 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
481 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
483 arm,pl330-broken-no-flushp;
484 arm,pl330-periph-burst;
485 clocks = <&cru ACLK_DMA2>;
486 clock-names = "apb_pclk";