1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2013 MundoReader S.L.
4 * Author: Heiko Stuebner <heiko@sntech.de>
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/soc/rockchip,boot-mode.h>
15 interrupt-parent = <&gic>;
36 compatible = "simple-bus";
41 dmac1_s: dma-controller@20018000 {
42 compatible = "arm,pl330", "arm,primecell";
43 reg = <0x20018000 0x4000>;
44 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
45 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
47 arm,pl330-broken-no-flushp;
48 clocks = <&cru ACLK_DMA1>;
49 clock-names = "apb_pclk";
52 dmac1_ns: dma-controller@2001c000 {
53 compatible = "arm,pl330", "arm,primecell";
54 reg = <0x2001c000 0x4000>;
55 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
56 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
58 arm,pl330-broken-no-flushp;
59 clocks = <&cru ACLK_DMA1>;
60 clock-names = "apb_pclk";
64 dmac2: dma-controller@20078000 {
65 compatible = "arm,pl330", "arm,primecell";
66 reg = <0x20078000 0x4000>;
67 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
68 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
70 arm,pl330-broken-no-flushp;
71 clocks = <&cru ACLK_DMA2>;
72 clock-names = "apb_pclk";
77 compatible = "fixed-clock";
78 clock-frequency = <24000000>;
80 clock-output-names = "xin24m";
84 compatible = "arm,mali-400";
85 reg = <0x10090000 0x10000>;
86 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
87 clock-names = "bus", "core";
88 assigned-clocks = <&cru ACLK_GPU>;
89 assigned-clock-rates = <100000000>;
90 resets = <&cru SRST_GPU>;
94 L2: l2-cache-controller@10138000 {
95 compatible = "arm,pl310-cache";
96 reg = <0x10138000 0x1000>;
102 compatible = "arm,cortex-a9-scu";
103 reg = <0x1013c000 0x100>;
106 global_timer: global-timer@1013c200 {
107 compatible = "arm,cortex-a9-global-timer";
108 reg = <0x1013c200 0x20>;
109 interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
110 clocks = <&cru CORE_PERI>;
112 /* The clock source and the sched_clock provided by the arm_global_timer
113 * on Rockchip rk3066a/rk3188 are quite unstable because their rates
114 * depend on the CPU frequency.
115 * Keep the arm_global_timer disabled in order to have the
116 * DW_APB_TIMER (rk3066a) or ROCKCHIP_TIMER (rk3188) selected by default.
120 local_timer: local-timer@1013c600 {
121 compatible = "arm,cortex-a9-twd-timer";
122 reg = <0x1013c600 0x20>;
123 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
124 clocks = <&cru CORE_PERI>;
127 gic: interrupt-controller@1013d000 {
128 compatible = "arm,cortex-a9-gic";
129 interrupt-controller;
130 #interrupt-cells = <3>;
131 reg = <0x1013d000 0x1000>,
135 uart0: serial@10124000 {
136 compatible = "snps,dw-apb-uart";
137 reg = <0x10124000 0x400>;
138 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
141 clock-names = "baudclk", "apb_pclk";
142 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
146 uart1: serial@10126000 {
147 compatible = "snps,dw-apb-uart";
148 reg = <0x10126000 0x400>;
149 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
152 clock-names = "baudclk", "apb_pclk";
153 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
157 qos_gpu: qos@1012d000 {
158 compatible = "syscon";
159 reg = <0x1012d000 0x20>;
162 qos_vpu: qos@1012e000 {
163 compatible = "syscon";
164 reg = <0x1012e000 0x20>;
167 qos_lcdc0: qos@1012f000 {
168 compatible = "syscon";
169 reg = <0x1012f000 0x20>;
172 qos_cif0: qos@1012f080 {
173 compatible = "syscon";
174 reg = <0x1012f080 0x20>;
177 qos_ipp: qos@1012f100 {
178 compatible = "syscon";
179 reg = <0x1012f100 0x20>;
182 qos_lcdc1: qos@1012f180 {
183 compatible = "syscon";
184 reg = <0x1012f180 0x20>;
187 qos_cif1: qos@1012f200 {
188 compatible = "syscon";
189 reg = <0x1012f200 0x20>;
192 qos_rga: qos@1012f280 {
193 compatible = "syscon";
194 reg = <0x1012f280 0x20>;
197 usb_otg: usb@10180000 {
198 compatible = "rockchip,rk3066-usb", "snps,dwc2";
199 reg = <0x10180000 0x40000>;
200 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
201 clocks = <&cru HCLK_OTG0>;
204 g-np-tx-fifo-size = <16>;
205 g-rx-fifo-size = <275>;
206 g-tx-fifo-size = <256 128 128 64 64 32>;
208 phy-names = "usb2-phy";
212 usb_host: usb@101c0000 {
213 compatible = "snps,dwc2";
214 reg = <0x101c0000 0x40000>;
215 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
216 clocks = <&cru HCLK_OTG1>;
220 phy-names = "usb2-phy";
224 emac: ethernet@10204000 {
225 compatible = "snps,arc-emac";
226 reg = <0x10204000 0x3c>;
227 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
228 #address-cells = <1>;
231 rockchip,grf = <&grf>;
233 clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>;
234 clock-names = "hclk", "macref";
241 mmc0: dwmmc@10214000 {
242 compatible = "rockchip,rk2928-dw-mshc";
243 reg = <0x10214000 0x1000>;
244 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
245 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
246 clock-names = "biu", "ciu";
250 resets = <&cru SRST_SDMMC>;
251 reset-names = "reset";
255 mmc1: dwmmc@10218000 {
256 compatible = "rockchip,rk2928-dw-mshc";
257 reg = <0x10218000 0x1000>;
258 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
259 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>;
260 clock-names = "biu", "ciu";
264 resets = <&cru SRST_SDIO>;
265 reset-names = "reset";
269 emmc: dwmmc@1021c000 {
270 compatible = "rockchip,rk2928-dw-mshc";
271 reg = <0x1021c000 0x1000>;
272 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
273 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
274 clock-names = "biu", "ciu";
278 resets = <&cru SRST_EMMC>;
279 reset-names = "reset";
284 compatible = "rockchip,rk3066-pmu", "syscon", "simple-mfd";
285 reg = <0x20004000 0x100>;
288 compatible = "syscon-reboot-mode";
290 mode-normal = <BOOT_NORMAL>;
291 mode-recovery = <BOOT_RECOVERY>;
292 mode-bootloader = <BOOT_FASTBOOT>;
293 mode-loader = <BOOT_BL_DOWNLOAD>;
298 compatible = "syscon";
299 reg = <0x20008000 0x200>;
303 compatible = "rockchip,rk3066-i2c";
304 reg = <0x2002d000 0x1000>;
305 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
306 #address-cells = <1>;
309 rockchip,grf = <&grf>;
312 clocks = <&cru PCLK_I2C0>;
318 compatible = "rockchip,rk3066-i2c";
319 reg = <0x2002f000 0x1000>;
320 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
321 #address-cells = <1>;
324 rockchip,grf = <&grf>;
326 clocks = <&cru PCLK_I2C1>;
333 compatible = "rockchip,rk2928-pwm";
334 reg = <0x20030000 0x10>;
336 clocks = <&cru PCLK_PWM01>;
341 compatible = "rockchip,rk2928-pwm";
342 reg = <0x20030010 0x10>;
344 clocks = <&cru PCLK_PWM01>;
348 wdt: watchdog@2004c000 {
349 compatible = "snps,dw-wdt";
350 reg = <0x2004c000 0x100>;
351 clocks = <&cru PCLK_WDT>;
352 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
357 compatible = "rockchip,rk2928-pwm";
358 reg = <0x20050020 0x10>;
360 clocks = <&cru PCLK_PWM23>;
365 compatible = "rockchip,rk2928-pwm";
366 reg = <0x20050030 0x10>;
368 clocks = <&cru PCLK_PWM23>;
373 compatible = "rockchip,rk3066-i2c";
374 reg = <0x20056000 0x1000>;
375 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
376 #address-cells = <1>;
379 rockchip,grf = <&grf>;
381 clocks = <&cru PCLK_I2C2>;
388 compatible = "rockchip,rk3066-i2c";
389 reg = <0x2005a000 0x1000>;
390 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
391 #address-cells = <1>;
394 rockchip,grf = <&grf>;
396 clocks = <&cru PCLK_I2C3>;
403 compatible = "rockchip,rk3066-i2c";
404 reg = <0x2005e000 0x1000>;
405 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
406 #address-cells = <1>;
409 rockchip,grf = <&grf>;
411 clocks = <&cru PCLK_I2C4>;
417 uart2: serial@20064000 {
418 compatible = "snps,dw-apb-uart";
419 reg = <0x20064000 0x400>;
420 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
423 clock-names = "baudclk", "apb_pclk";
424 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
428 uart3: serial@20068000 {
429 compatible = "snps,dw-apb-uart";
430 reg = <0x20068000 0x400>;
431 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
434 clock-names = "baudclk", "apb_pclk";
435 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
439 saradc: saradc@2006c000 {
440 compatible = "rockchip,saradc";
441 reg = <0x2006c000 0x100>;
442 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
443 #io-channel-cells = <1>;
444 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
445 clock-names = "saradc", "apb_pclk";
446 resets = <&cru SRST_SARADC>;
447 reset-names = "saradc-apb";
452 compatible = "rockchip,rk3066-spi";
453 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
454 clock-names = "spiclk", "apb_pclk";
455 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
456 reg = <0x20070000 0x1000>;
457 #address-cells = <1>;
459 dmas = <&dmac2 10>, <&dmac2 11>;
460 dma-names = "tx", "rx";
465 compatible = "rockchip,rk3066-spi";
466 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
467 clock-names = "spiclk", "apb_pclk";
468 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
469 reg = <0x20074000 0x1000>;
470 #address-cells = <1>;
472 dmas = <&dmac2 12>, <&dmac2 13>;
473 dma-names = "tx", "rx";