arch/arm/boot/dts/rk3xxx.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2013 MundoReader S.L.
   4  * Author: Heiko Stuebner <heiko@sntech.de>
   5  */
   6
   7 #include <dt-bindings/interrupt-controller/irq.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/soc/rockchip,boot-mode.h>
  10
  11 / {
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14
  15         interrupt-parent = <&gic>;
  16
  17         aliases {
  18                 ethernet0 = &emac;
  19                 i2c0 = &i2c0;
  20                 i2c1 = &i2c1;
  21                 i2c2 = &i2c2;
  22                 i2c3 = &i2c3;
  23                 i2c4 = &i2c4;
  24                 mshc0 = &emmc;
  25                 mshc1 = &mmc0;
  26                 mshc2 = &mmc1;
  27                 serial0 = &uart0;
  28                 serial1 = &uart1;
  29                 serial2 = &uart2;
  30                 serial3 = &uart3;
  31                 spi0 = &spi0;
  32                 spi1 = &spi1;
  33         };
  34
  35         amba {
  36                 compatible = "simple-bus";
  37                 #address-cells = <1>;
  38                 #size-cells = <1>;
  39                 ranges;
  40
  41                 dmac1_s: dma-controller@20018000 {
  42                         compatible = "arm,pl330", "arm,primecell";
  43                         reg = <0x20018000 0x4000>;
  44                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
  45                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
  46                         #dma-cells = <1>;
  47                         arm,pl330-broken-no-flushp;
  48                         clocks = <&cru ACLK_DMA1>;
  49                         clock-names = "apb_pclk";
  50                 };
  51
  52                 dmac1_ns: dma-controller@2001c000 {
  53                         compatible = "arm,pl330", "arm,primecell";
  54                         reg = <0x2001c000 0x4000>;
  55                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
  56                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
  57                         #dma-cells = <1>;
  58                         arm,pl330-broken-no-flushp;
  59                         clocks = <&cru ACLK_DMA1>;
  60                         clock-names = "apb_pclk";
  61                         status = "disabled";
  62                 };
  63
  64                 dmac2: dma-controller@20078000 {
  65                         compatible = "arm,pl330", "arm,primecell";
  66                         reg = <0x20078000 0x4000>;
  67                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
  68                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
  69                         #dma-cells = <1>;
  70                         arm,pl330-broken-no-flushp;
  71                         clocks = <&cru ACLK_DMA2>;
  72                         clock-names = "apb_pclk";
  73                 };
  74         };
  75
  76         xin24m: oscillator {
  77                 compatible = "fixed-clock";
  78                 clock-frequency = <24000000>;
  79                 #clock-cells = <0>;
  80                 clock-output-names = "xin24m";
  81         };
  82
  83         gpu: gpu@10090000 {
  84                 compatible = "arm,mali-400";
  85                 reg = <0x10090000 0x10000>;
  86                 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
  87                 clock-names = "bus", "core";
  88                 assigned-clocks = <&cru ACLK_GPU>;
  89                 assigned-clock-rates = <100000000>;
  90                 resets = <&cru SRST_GPU>;
  91                 status = "disabled";
  92         };
  93
  94         L2: l2-cache-controller@10138000 {
  95                 compatible = "arm,pl310-cache";
  96                 reg = <0x10138000 0x1000>;
  97                 cache-unified;
  98                 cache-level = <2>;
  99         };
 100
 101         scu@1013c000 {
 102                 compatible = "arm,cortex-a9-scu";
 103                 reg = <0x1013c000 0x100>;
 104         };
 105
 106         global_timer: global-timer@1013c200 {
 107                 compatible = "arm,cortex-a9-global-timer";
 108                 reg = <0x1013c200 0x20>;
 109                 interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
 110                 clocks = <&cru CORE_PERI>;
 111         };
 112
 113         local_timer: local-timer@1013c600 {
 114                 compatible = "arm,cortex-a9-twd-timer";
 115                 reg = <0x1013c600 0x20>;
 116                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
 117                 clocks = <&cru CORE_PERI>;
 118         };
 119
 120         gic: interrupt-controller@1013d000 {
 121                 compatible = "arm,cortex-a9-gic";
 122                 interrupt-controller;
 123                 #interrupt-cells = <3>;
 124                 reg = <0x1013d000 0x1000>,
 125                       <0x1013c100 0x0100>;
 126         };
 127
 128         uart0: serial@10124000 {
 129                 compatible = "snps,dw-apb-uart";
 130                 reg = <0x10124000 0x400>;
 131                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 132                 reg-shift = <2>;
 133                 reg-io-width = <1>;
 134                 clock-names = "baudclk", "apb_pclk";
 135                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 136                 status = "disabled";
 137         };
 138
 139         uart1: serial@10126000 {
 140                 compatible = "snps,dw-apb-uart";
 141                 reg = <0x10126000 0x400>;
 142                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 143                 reg-shift = <2>;
 144                 reg-io-width = <1>;
 145                 clock-names = "baudclk", "apb_pclk";
 146                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 147                 status = "disabled";
 148         };
 149
 150         usb_otg: usb@10180000 {
 151                 compatible = "rockchip,rk3066-usb", "snps,dwc2";
 152                 reg = <0x10180000 0x40000>;
 153                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 154                 clocks = <&cru HCLK_OTG0>;
 155                 clock-names = "otg";
 156                 dr_mode = "otg";
 157                 g-np-tx-fifo-size = <16>;
 158                 g-rx-fifo-size = <275>;
 159                 g-tx-fifo-size = <256 128 128 64 64 32>;
 160                 phys = <&usbphy0>;
 161                 phy-names = "usb2-phy";
 162                 status = "disabled";
 163         };
 164
 165         usb_host: usb@101c0000 {
 166                 compatible = "snps,dwc2";
 167                 reg = <0x101c0000 0x40000>;
 168                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 169                 clocks = <&cru HCLK_OTG1>;
 170                 clock-names = "otg";
 171                 dr_mode = "host";
 172                 phys = <&usbphy1>;
 173                 phy-names = "usb2-phy";
 174                 status = "disabled";
 175         };
 176
 177         emac: ethernet@10204000 {
 178                 compatible = "snps,arc-emac";
 179                 reg = <0x10204000 0x3c>;
 180                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 181                 #address-cells = <1>;
 182                 #size-cells = <0>;
 183
 184                 rockchip,grf = <&grf>;
 185
 186                 clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>;
 187                 clock-names = "hclk", "macref";
 188                 max-speed = <100>;
 189                 phy-mode = "rmii";
 190
 191                 status = "disabled";
 192         };
 193
 194         mmc0: dwmmc@10214000 {
 195                 compatible = "rockchip,rk2928-dw-mshc";
 196                 reg = <0x10214000 0x1000>;
 197                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 198                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 199                 clock-names = "biu", "ciu";
 200                 dmas = <&dmac2 1>;
 201                 dma-names = "rx-tx";
 202                 fifo-depth = <256>;
 203                 resets = <&cru SRST_SDMMC>;
 204                 reset-names = "reset";
 205                 status = "disabled";
 206         };
 207
 208         mmc1: dwmmc@10218000 {
 209                 compatible = "rockchip,rk2928-dw-mshc";
 210                 reg = <0x10218000 0x1000>;
 211                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 212                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>;
 213                 clock-names = "biu", "ciu";
 214                 dmas = <&dmac2 3>;
 215                 dma-names = "rx-tx";
 216                 fifo-depth = <256>;
 217                 resets = <&cru SRST_SDIO>;
 218                 reset-names = "reset";
 219                 status = "disabled";
 220         };
 221
 222         emmc: dwmmc@1021c000 {
 223                 compatible = "rockchip,rk2928-dw-mshc";
 224                 reg = <0x1021c000 0x1000>;
 225                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 226                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
 227                 clock-names = "biu", "ciu";
 228                 dmas = <&dmac2 4>;
 229                 dma-names = "rx-tx";
 230                 fifo-depth = <256>;
 231                 resets = <&cru SRST_EMMC>;
 232                 reset-names = "reset";
 233                 status = "disabled";
 234         };
 235
 236         pmu: pmu@20004000 {
 237                 compatible = "rockchip,rk3066-pmu", "syscon", "simple-mfd";
 238                 reg = <0x20004000 0x100>;
 239
 240                 reboot-mode {
 241                         compatible = "syscon-reboot-mode";
 242                         offset = <0x40>;
 243                         mode-normal = <BOOT_NORMAL>;
 244                         mode-recovery = <BOOT_RECOVERY>;
 245                         mode-bootloader = <BOOT_FASTBOOT>;
 246                         mode-loader = <BOOT_BL_DOWNLOAD>;
 247                 };
 248         };
 249
 250         grf: grf@20008000 {
 251                 compatible = "syscon";
 252                 reg = <0x20008000 0x200>;
 253         };
 254
 255         i2c0: i2c@2002d000 {
 256                 compatible = "rockchip,rk3066-i2c";
 257                 reg = <0x2002d000 0x1000>;
 258                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 259                 #address-cells = <1>;
 260                 #size-cells = <0>;
 261
 262                 rockchip,grf = <&grf>;
 263
 264                 clock-names = "i2c";
 265                 clocks = <&cru PCLK_I2C0>;
 266
 267                 status = "disabled";
 268         };
 269
 270         i2c1: i2c@2002f000 {
 271                 compatible = "rockchip,rk3066-i2c";
 272                 reg = <0x2002f000 0x1000>;
 273                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 274                 #address-cells = <1>;
 275                 #size-cells = <0>;
 276
 277                 rockchip,grf = <&grf>;
 278
 279                 clocks = <&cru PCLK_I2C1>;
 280                 clock-names = "i2c";
 281
 282                 status = "disabled";
 283         };
 284
 285         pwm0: pwm@20030000 {
 286                 compatible = "rockchip,rk2928-pwm";
 287                 reg = <0x20030000 0x10>;
 288                 #pwm-cells = <2>;
 289                 clocks = <&cru PCLK_PWM01>;
 290                 status = "disabled";
 291         };
 292
 293         pwm1: pwm@20030010 {
 294                 compatible = "rockchip,rk2928-pwm";
 295                 reg = <0x20030010 0x10>;
 296                 #pwm-cells = <2>;
 297                 clocks = <&cru PCLK_PWM01>;
 298                 status = "disabled";
 299         };
 300
 301         wdt: watchdog@2004c000 {
 302                 compatible = "snps,dw-wdt";
 303                 reg = <0x2004c000 0x100>;
 304                 clocks = <&cru PCLK_WDT>;
 305                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 306                 status = "disabled";
 307         };
 308
 309         pwm2: pwm@20050020 {
 310                 compatible = "rockchip,rk2928-pwm";
 311                 reg = <0x20050020 0x10>;
 312                 #pwm-cells = <2>;
 313                 clocks = <&cru PCLK_PWM23>;
 314                 status = "disabled";
 315         };
 316
 317         pwm3: pwm@20050030 {
 318                 compatible = "rockchip,rk2928-pwm";
 319                 reg = <0x20050030 0x10>;
 320                 #pwm-cells = <2>;
 321                 clocks = <&cru PCLK_PWM23>;
 322                 status = "disabled";
 323         };
 324
 325         i2c2: i2c@20056000 {
 326                 compatible = "rockchip,rk3066-i2c";
 327                 reg = <0x20056000 0x1000>;
 328                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 329                 #address-cells = <1>;
 330                 #size-cells = <0>;
 331
 332                 rockchip,grf = <&grf>;
 333
 334                 clocks = <&cru PCLK_I2C2>;
 335                 clock-names = "i2c";
 336
 337                 status = "disabled";
 338         };
 339
 340         i2c3: i2c@2005a000 {
 341                 compatible = "rockchip,rk3066-i2c";
 342                 reg = <0x2005a000 0x1000>;
 343                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 344                 #address-cells = <1>;
 345                 #size-cells = <0>;
 346
 347                 rockchip,grf = <&grf>;
 348
 349                 clocks = <&cru PCLK_I2C3>;
 350                 clock-names = "i2c";
 351
 352                 status = "disabled";
 353         };
 354
 355         i2c4: i2c@2005e000 {
 356                 compatible = "rockchip,rk3066-i2c";
 357                 reg = <0x2005e000 0x1000>;
 358                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 359                 #address-cells = <1>;
 360                 #size-cells = <0>;
 361
 362                 rockchip,grf = <&grf>;
 363
 364                 clocks = <&cru PCLK_I2C4>;
 365                 clock-names = "i2c";
 366
 367                 status = "disabled";
 368         };
 369
 370         uart2: serial@20064000 {
 371                 compatible = "snps,dw-apb-uart";
 372                 reg = <0x20064000 0x400>;
 373                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 374                 reg-shift = <2>;
 375                 reg-io-width = <1>;
 376                 clock-names = "baudclk", "apb_pclk";
 377                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 378                 status = "disabled";
 379         };
 380
 381         uart3: serial@20068000 {
 382                 compatible = "snps,dw-apb-uart";
 383                 reg = <0x20068000 0x400>;
 384                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 385                 reg-shift = <2>;
 386                 reg-io-width = <1>;
 387                 clock-names = "baudclk", "apb_pclk";
 388                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 389                 status = "disabled";
 390         };
 391
 392         saradc: saradc@2006c000 {
 393                 compatible = "rockchip,saradc";
 394                 reg = <0x2006c000 0x100>;
 395                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 396                 #io-channel-cells = <1>;
 397                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 398                 clock-names = "saradc", "apb_pclk";
 399                 resets = <&cru SRST_SARADC>;
 400                 reset-names = "saradc-apb";
 401                 status = "disabled";
 402         };
 403
 404         spi0: spi@20070000 {
 405                 compatible = "rockchip,rk3066-spi";
 406                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 407                 clock-names = "spiclk", "apb_pclk";
 408                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 409                 reg = <0x20070000 0x1000>;
 410                 #address-cells = <1>;
 411                 #size-cells = <0>;
 412                 dmas = <&dmac2 10>, <&dmac2 11>;
 413                 dma-names = "tx", "rx";
 414                 status = "disabled";
 415         };
 416
 417         spi1: spi@20074000 {
 418                 compatible = "rockchip,rk3066-spi";
 419                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 420                 clock-names = "spiclk", "apb_pclk";
 421                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 422                 reg = <0x20074000 0x1000>;
 423                 #address-cells = <1>;
 424                 #size-cells = <0>;
 425                 dmas = <&dmac2 12>, <&dmac2 13>;
 426                 dma-names = "tx", "rx";
 427                 status = "disabled";
 428         };
 429 };