arch/arm/boot/dts/rk3xxx.dtsi

   1 /*
   2  * Copyright (c) 2013 MundoReader S.L.
   3  * Author: Heiko Stuebner <heiko@sntech.de>
   4  *
   5  * This file is dual-licensed: you can use it either under the terms
   6  * of the GPL or the X11 license, at your option. Note that this dual
   7  * licensing only applies to this file, and not this project as a
   8  * whole.
   9  *
  10  *  a) This file is free software; you can redistribute it and/or
  11  *     modify it under the terms of the GNU General Public License as
  12  *     published by the Free Software Foundation; either version 2 of the
  13  *     License, or (at your option) any later version.
  14  *
  15  *     This file is distributed in the hope that it will be useful,
  16  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *     GNU General Public License for more details.
  19  *
  20  * Or, alternatively,
  21  *
  22  *  b) Permission is hereby granted, free of charge, to any person
  23  *     obtaining a copy of this software and associated documentation
  24  *     files (the "Software"), to deal in the Software without
  25  *     restriction, including without limitation the rights to use,
  26  *     copy, modify, merge, publish, distribute, sublicense, and/or
  27  *     sell copies of the Software, and to permit persons to whom the
  28  *     Software is furnished to do so, subject to the following
  29  *     conditions:
  30  *
  31  *     The above copyright notice and this permission notice shall be
  32  *     included in all copies or substantial portions of the Software.
  33  *
  34  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  35  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  36  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  37  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  38  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  39  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  40  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  41  *     OTHER DEALINGS IN THE SOFTWARE.
  42  */
  43
  44 #include <dt-bindings/interrupt-controller/irq.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/soc/rockchip,boot-mode.h>
  47
  48 / {
  49         #address-cells = <1>;
  50         #size-cells = <1>;
  51
  52         interrupt-parent = <&gic>;
  53
  54         aliases {
  55                 ethernet0 = &emac;
  56                 i2c0 = &i2c0;
  57                 i2c1 = &i2c1;
  58                 i2c2 = &i2c2;
  59                 i2c3 = &i2c3;
  60                 i2c4 = &i2c4;
  61                 mshc0 = &emmc;
  62                 mshc1 = &mmc0;
  63                 mshc2 = &mmc1;
  64                 serial0 = &uart0;
  65                 serial1 = &uart1;
  66                 serial2 = &uart2;
  67                 serial3 = &uart3;
  68                 spi0 = &spi0;
  69                 spi1 = &spi1;
  70         };
  71
  72         amba {
  73                 compatible = "simple-bus";
  74                 #address-cells = <1>;
  75                 #size-cells = <1>;
  76                 ranges;
  77
  78                 dmac1_s: dma-controller@20018000 {
  79                         compatible = "arm,pl330", "arm,primecell";
  80                         reg = <0x20018000 0x4000>;
  81                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
  82                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
  83                         #dma-cells = <1>;
  84                         arm,pl330-broken-no-flushp;
  85                         clocks = <&cru ACLK_DMA1>;
  86                         clock-names = "apb_pclk";
  87                 };
  88
  89                 dmac1_ns: dma-controller@2001c000 {
  90                         compatible = "arm,pl330", "arm,primecell";
  91                         reg = <0x2001c000 0x4000>;
  92                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
  93                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
  94                         #dma-cells = <1>;
  95                         arm,pl330-broken-no-flushp;
  96                         clocks = <&cru ACLK_DMA1>;
  97                         clock-names = "apb_pclk";
  98                         status = "disabled";
  99                 };
 100
 101                 dmac2: dma-controller@20078000 {
 102                         compatible = "arm,pl330", "arm,primecell";
 103                         reg = <0x20078000 0x4000>;
 104                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 105                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 106                         #dma-cells = <1>;
 107                         arm,pl330-broken-no-flushp;
 108                         clocks = <&cru ACLK_DMA2>;
 109                         clock-names = "apb_pclk";
 110                 };
 111         };
 112
 113         xin24m: oscillator {
 114                 compatible = "fixed-clock";
 115                 clock-frequency = <24000000>;
 116                 #clock-cells = <0>;
 117                 clock-output-names = "xin24m";
 118         };
 119
 120         L2: l2-cache-controller@10138000 {
 121                 compatible = "arm,pl310-cache";
 122                 reg = <0x10138000 0x1000>;
 123                 cache-unified;
 124                 cache-level = <2>;
 125         };
 126
 127         scu@1013c000 {
 128                 compatible = "arm,cortex-a9-scu";
 129                 reg = <0x1013c000 0x100>;
 130         };
 131
 132         global_timer: global-timer@1013c200 {
 133                 compatible = "arm,cortex-a9-global-timer";
 134                 reg = <0x1013c200 0x20>;
 135                 interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
 136                 clocks = <&cru CORE_PERI>;
 137                 status = "disabled";
 138                 /* The clock source and the sched_clock provided by the arm_global_timer
 139                  * on Rockchip rk3066a/rk3188 are quite unstable because their rates
 140                  * depend on the CPU frequency.
 141                  * Keep the arm_global_timer disabled in order to have the
 142                  * DW_APB_TIMER (rk3066a) or ROCKCHIP_TIMER (rk3188) selected by default.
 143                  */
 144         };
 145
 146         local_timer: local-timer@1013c600 {
 147                 compatible = "arm,cortex-a9-twd-timer";
 148                 reg = <0x1013c600 0x20>;
 149                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
 150                 clocks = <&cru CORE_PERI>;
 151         };
 152
 153         gic: interrupt-controller@1013d000 {
 154                 compatible = "arm,cortex-a9-gic";
 155                 interrupt-controller;
 156                 #interrupt-cells = <3>;
 157                 reg = <0x1013d000 0x1000>,
 158                       <0x1013c100 0x0100>;
 159         };
 160
 161         uart0: serial@10124000 {
 162                 compatible = "snps,dw-apb-uart";
 163                 reg = <0x10124000 0x400>;
 164                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 165                 reg-shift = <2>;
 166                 reg-io-width = <1>;
 167                 clock-names = "baudclk", "apb_pclk";
 168                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 169                 status = "disabled";
 170         };
 171
 172         uart1: serial@10126000 {
 173                 compatible = "snps,dw-apb-uart";
 174                 reg = <0x10126000 0x400>;
 175                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 176                 reg-shift = <2>;
 177                 reg-io-width = <1>;
 178                 clock-names = "baudclk", "apb_pclk";
 179                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 180                 status = "disabled";
 181         };
 182
 183         usb_otg: usb@10180000 {
 184                 compatible = "rockchip,rk3066-usb", "snps,dwc2";
 185                 reg = <0x10180000 0x40000>;
 186                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 187                 clocks = <&cru HCLK_OTG0>;
 188                 clock-names = "otg";
 189                 dr_mode = "otg";
 190                 g-np-tx-fifo-size = <16>;
 191                 g-rx-fifo-size = <275>;
 192                 g-tx-fifo-size = <256 128 128 64 64 32>;
 193                 phys = <&usbphy0>;
 194                 phy-names = "usb2-phy";
 195                 status = "disabled";
 196         };
 197
 198         usb_host: usb@101c0000 {
 199                 compatible = "snps,dwc2";
 200                 reg = <0x101c0000 0x40000>;
 201                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 202                 clocks = <&cru HCLK_OTG1>;
 203                 clock-names = "otg";
 204                 dr_mode = "host";
 205                 phys = <&usbphy1>;
 206                 phy-names = "usb2-phy";
 207                 status = "disabled";
 208         };
 209
 210         emac: ethernet@10204000 {
 211                 compatible = "snps,arc-emac";
 212                 reg = <0x10204000 0x3c>;
 213                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 214                 #address-cells = <1>;
 215                 #size-cells = <0>;
 216
 217                 rockchip,grf = <&grf>;
 218
 219                 clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>;
 220                 clock-names = "hclk", "macref";
 221                 max-speed = <100>;
 222                 phy-mode = "rmii";
 223
 224                 status = "disabled";
 225         };
 226
 227         mmc0: dwmmc@10214000 {
 228                 compatible = "rockchip,rk2928-dw-mshc";
 229                 reg = <0x10214000 0x1000>;
 230                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 231                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 232                 clock-names = "biu", "ciu";
 233                 dmas = <&dmac2 1>;
 234                 dma-names = "rx-tx";
 235                 fifo-depth = <256>;
 236                 resets = <&cru SRST_SDMMC>;
 237                 reset-names = "reset";
 238                 status = "disabled";
 239         };
 240
 241         mmc1: dwmmc@10218000 {
 242                 compatible = "rockchip,rk2928-dw-mshc";
 243                 reg = <0x10218000 0x1000>;
 244                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 245                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>;
 246                 clock-names = "biu", "ciu";
 247                 dmas = <&dmac2 3>;
 248                 dma-names = "rx-tx";
 249                 fifo-depth = <256>;
 250                 resets = <&cru SRST_SDIO>;
 251                 reset-names = "reset";
 252                 status = "disabled";
 253         };
 254
 255         emmc: dwmmc@1021c000 {
 256                 compatible = "rockchip,rk2928-dw-mshc";
 257                 reg = <0x1021c000 0x1000>;
 258                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 259                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
 260                 clock-names = "biu", "ciu";
 261                 dmas = <&dmac2 4>;
 262                 dma-names = "rx-tx";
 263                 fifo-depth = <256>;
 264                 resets = <&cru SRST_EMMC>;
 265                 reset-names = "reset";
 266                 status = "disabled";
 267         };
 268
 269         pmu: pmu@20004000 {
 270                 compatible = "rockchip,rk3066-pmu", "syscon", "simple-mfd";
 271                 reg = <0x20004000 0x100>;
 272
 273                 reboot-mode {
 274                         compatible = "syscon-reboot-mode";
 275                         offset = <0x40>;
 276                         mode-normal = <BOOT_NORMAL>;
 277                         mode-recovery = <BOOT_RECOVERY>;
 278                         mode-bootloader = <BOOT_FASTBOOT>;
 279                         mode-loader = <BOOT_BL_DOWNLOAD>;
 280                 };
 281         };
 282
 283         grf: grf@20008000 {
 284                 compatible = "syscon";
 285                 reg = <0x20008000 0x200>;
 286         };
 287
 288         i2c0: i2c@2002d000 {
 289                 compatible = "rockchip,rk3066-i2c";
 290                 reg = <0x2002d000 0x1000>;
 291                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 292                 #address-cells = <1>;
 293                 #size-cells = <0>;
 294
 295                 rockchip,grf = <&grf>;
 296
 297                 clock-names = "i2c";
 298                 clocks = <&cru PCLK_I2C0>;
 299
 300                 status = "disabled";
 301         };
 302
 303         i2c1: i2c@2002f000 {
 304                 compatible = "rockchip,rk3066-i2c";
 305                 reg = <0x2002f000 0x1000>;
 306                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 307                 #address-cells = <1>;
 308                 #size-cells = <0>;
 309
 310                 rockchip,grf = <&grf>;
 311
 312                 clocks = <&cru PCLK_I2C1>;
 313                 clock-names = "i2c";
 314
 315                 status = "disabled";
 316         };
 317
 318         pwm0: pwm@20030000 {
 319                 compatible = "rockchip,rk2928-pwm";
 320                 reg = <0x20030000 0x10>;
 321                 #pwm-cells = <2>;
 322                 clocks = <&cru PCLK_PWM01>;
 323                 status = "disabled";
 324         };
 325
 326         pwm1: pwm@20030010 {
 327                 compatible = "rockchip,rk2928-pwm";
 328                 reg = <0x20030010 0x10>;
 329                 #pwm-cells = <2>;
 330                 clocks = <&cru PCLK_PWM01>;
 331                 status = "disabled";
 332         };
 333
 334         wdt: watchdog@2004c000 {
 335                 compatible = "snps,dw-wdt";
 336                 reg = <0x2004c000 0x100>;
 337                 clocks = <&cru PCLK_WDT>;
 338                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 339                 status = "disabled";
 340         };
 341
 342         pwm2: pwm@20050020 {
 343                 compatible = "rockchip,rk2928-pwm";
 344                 reg = <0x20050020 0x10>;
 345                 #pwm-cells = <2>;
 346                 clocks = <&cru PCLK_PWM23>;
 347                 status = "disabled";
 348         };
 349
 350         pwm3: pwm@20050030 {
 351                 compatible = "rockchip,rk2928-pwm";
 352                 reg = <0x20050030 0x10>;
 353                 #pwm-cells = <2>;
 354                 clocks = <&cru PCLK_PWM23>;
 355                 status = "disabled";
 356         };
 357
 358         i2c2: i2c@20056000 {
 359                 compatible = "rockchip,rk3066-i2c";
 360                 reg = <0x20056000 0x1000>;
 361                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 362                 #address-cells = <1>;
 363                 #size-cells = <0>;
 364
 365                 rockchip,grf = <&grf>;
 366
 367                 clocks = <&cru PCLK_I2C2>;
 368                 clock-names = "i2c";
 369
 370                 status = "disabled";
 371         };
 372
 373         i2c3: i2c@2005a000 {
 374                 compatible = "rockchip,rk3066-i2c";
 375                 reg = <0x2005a000 0x1000>;
 376                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 377                 #address-cells = <1>;
 378                 #size-cells = <0>;
 379
 380                 rockchip,grf = <&grf>;
 381
 382                 clocks = <&cru PCLK_I2C3>;
 383                 clock-names = "i2c";
 384
 385                 status = "disabled";
 386         };
 387
 388         i2c4: i2c@2005e000 {
 389                 compatible = "rockchip,rk3066-i2c";
 390                 reg = <0x2005e000 0x1000>;
 391                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 392                 #address-cells = <1>;
 393                 #size-cells = <0>;
 394
 395                 rockchip,grf = <&grf>;
 396
 397                 clocks = <&cru PCLK_I2C4>;
 398                 clock-names = "i2c";
 399
 400                 status = "disabled";
 401         };
 402
 403         uart2: serial@20064000 {
 404                 compatible = "snps,dw-apb-uart";
 405                 reg = <0x20064000 0x400>;
 406                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 407                 reg-shift = <2>;
 408                 reg-io-width = <1>;
 409                 clock-names = "baudclk", "apb_pclk";
 410                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 411                 status = "disabled";
 412         };
 413
 414         uart3: serial@20068000 {
 415                 compatible = "snps,dw-apb-uart";
 416                 reg = <0x20068000 0x400>;
 417                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 418                 reg-shift = <2>;
 419                 reg-io-width = <1>;
 420                 clock-names = "baudclk", "apb_pclk";
 421                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 422                 status = "disabled";
 423         };
 424
 425         saradc: saradc@2006c000 {
 426                 compatible = "rockchip,saradc";
 427                 reg = <0x2006c000 0x100>;
 428                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 429                 #io-channel-cells = <1>;
 430                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 431                 clock-names = "saradc", "apb_pclk";
 432                 resets = <&cru SRST_SARADC>;
 433                 reset-names = "saradc-apb";
 434                 status = "disabled";
 435         };
 436
 437         spi0: spi@20070000 {
 438                 compatible = "rockchip,rk3066-spi";
 439                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 440                 clock-names = "spiclk", "apb_pclk";
 441                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 442                 reg = <0x20070000 0x1000>;
 443                 #address-cells = <1>;
 444                 #size-cells = <0>;
 445                 dmas = <&dmac2 10>, <&dmac2 11>;
 446                 dma-names = "tx", "rx";
 447                 status = "disabled";
 448         };
 449
 450         spi1: spi@20074000 {
 451                 compatible = "rockchip,rk3066-spi";
 452                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 453                 clock-names = "spiclk", "apb_pclk";
 454                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 455                 reg = <0x20074000 0x1000>;
 456                 #address-cells = <1>;
 457                 #size-cells = <0>;
 458                 dmas = <&dmac2 12>, <&dmac2 13>;
 459                 dma-names = "tx", "rx";
 460                 status = "disabled";
 461         };
 462 };