arch/arm/boot/dts/rk3288.dtsi

   1 /*
   2  * This file is dual-licensed: you can use it either under the terms
   3  * of the GPL or the X11 license, at your option. Note that this dual
   4  * licensing only applies to this file, and not this project as a
   5  * whole.
   6  *
   7  *  a) This file is free software; you can redistribute it and/or
   8  *     modify it under the terms of the GNU General Public License as
   9  *     published by the Free Software Foundation; either version 2 of the
  10  *     License, or (at your option) any later version.
  11  *
  12  *     This file is distributed in the hope that it will be useful,
  13  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *     GNU General Public License for more details.
  16  *
  17  * Or, alternatively,
  18  *
  19  *  b) Permission is hereby granted, free of charge, to any person
  20  *     obtaining a copy of this software and associated documentation
  21  *     files (the "Software"), to deal in the Software without
  22  *     restriction, including without limitation the rights to use,
  23  *     copy, modify, merge, publish, distribute, sublicense, and/or
  24  *     sell copies of the Software, and to permit persons to whom the
  25  *     Software is furnished to do so, subject to the following
  26  *     conditions:
  27  *
  28  *     The above copyright notice and this permission notice shall be
  29  *     included in all copies or substantial portions of the Software.
  30  *
  31  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  32  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  33  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  34  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  35  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  36  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  37  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  38  *     OTHER DEALINGS IN THE SOFTWARE.
  39  */
  40
  41 #include <dt-bindings/gpio/gpio.h>
  42 #include <dt-bindings/interrupt-controller/irq.h>
  43 #include <dt-bindings/interrupt-controller/arm-gic.h>
  44 #include <dt-bindings/pinctrl/rockchip.h>
  45 #include <dt-bindings/clock/rk3288-cru.h>
  46 #include <dt-bindings/power/rk3288-power.h>
  47 #include <dt-bindings/thermal/thermal.h>
  48 #include <dt-bindings/power/rk3288-power.h>
  49 #include <dt-bindings/soc/rockchip,boot-mode.h>
  50
  51 / {
  52         #address-cells = <2>;
  53         #size-cells = <2>;
  54
  55         compatible = "rockchip,rk3288";
  56
  57         interrupt-parent = <&gic>;
  58
  59         aliases {
  60                 ethernet0 = &gmac;
  61                 i2c0 = &i2c0;
  62                 i2c1 = &i2c1;
  63                 i2c2 = &i2c2;
  64                 i2c3 = &i2c3;
  65                 i2c4 = &i2c4;
  66                 i2c5 = &i2c5;
  67                 mshc0 = &emmc;
  68                 mshc1 = &sdmmc;
  69                 mshc2 = &sdio0;
  70                 mshc3 = &sdio1;
  71                 serial0 = &uart0;
  72                 serial1 = &uart1;
  73                 serial2 = &uart2;
  74                 serial3 = &uart3;
  75                 serial4 = &uart4;
  76                 spi0 = &spi0;
  77                 spi1 = &spi1;
  78                 spi2 = &spi2;
  79         };
  80
  81         arm-pmu {
  82                 compatible = "arm,cortex-a12-pmu";
  83                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
  84                              <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
  85                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
  86                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
  87                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  88         };
  89
  90         cpus {
  91                 #address-cells = <1>;
  92                 #size-cells = <0>;
  93                 enable-method = "rockchip,rk3066-smp";
  94                 rockchip,pmu = <&pmu>;
  95
  96                 cpu0: cpu@500 {
  97                         device_type = "cpu";
  98                         compatible = "arm,cortex-a12";
  99                         reg = <0x500>;
 100                         resets = <&cru SRST_CORE0>;
 101                         operating-points = <
 102                                 /* KHz    uV */
 103                                 1608000 1350000
 104                                 1512000 1300000
 105                                 1416000 1200000
 106                                 1200000 1100000
 107                                 1008000 1050000
 108                                  816000 1000000
 109                                  696000  950000
 110                                  600000  900000
 111                                  408000  900000
 112                                  312000  900000
 113                                  216000  900000
 114                                  126000  900000
 115                         >;
 116                         #cooling-cells = <2>; /* min followed by max */
 117                         clock-latency = <40000>;
 118                         clocks = <&cru ARMCLK>;
 119                 };
 120                 cpu1: cpu@501 {
 121                         device_type = "cpu";
 122                         compatible = "arm,cortex-a12";
 123                         reg = <0x501>;
 124                         resets = <&cru SRST_CORE1>;
 125                 };
 126                 cpu2: cpu@502 {
 127                         device_type = "cpu";
 128                         compatible = "arm,cortex-a12";
 129                         reg = <0x502>;
 130                         resets = <&cru SRST_CORE2>;
 131                 };
 132                 cpu3: cpu@503 {
 133                         device_type = "cpu";
 134                         compatible = "arm,cortex-a12";
 135                         reg = <0x503>;
 136                         resets = <&cru SRST_CORE3>;
 137                 };
 138         };
 139
 140         amba {
 141                 compatible = "simple-bus";
 142                 #address-cells = <2>;
 143                 #size-cells = <2>;
 144                 ranges;
 145
 146                 dmac_peri: dma-controller@ff250000 {
 147                         compatible = "arm,pl330", "arm,primecell";
 148                         reg = <0x0 0xff250000 0x0 0x4000>;
 149                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 150                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 151                         #dma-cells = <1>;
 152                         arm,pl330-broken-no-flushp;
 153                         clocks = <&cru ACLK_DMAC2>;
 154                         clock-names = "apb_pclk";
 155                 };
 156
 157                 dmac_bus_ns: dma-controller@ff600000 {
 158                         compatible = "arm,pl330", "arm,primecell";
 159                         reg = <0x0 0xff600000 0x0 0x4000>;
 160                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 161                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 162                         #dma-cells = <1>;
 163                         arm,pl330-broken-no-flushp;
 164                         clocks = <&cru ACLK_DMAC1>;
 165                         clock-names = "apb_pclk";
 166                         status = "disabled";
 167                 };
 168
 169                 dmac_bus_s: dma-controller@ffb20000 {
 170                         compatible = "arm,pl330", "arm,primecell";
 171                         reg = <0x0 0xffb20000 0x0 0x4000>;
 172                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 173                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 174                         #dma-cells = <1>;
 175                         arm,pl330-broken-no-flushp;
 176                         clocks = <&cru ACLK_DMAC1>;
 177                         clock-names = "apb_pclk";
 178                 };
 179         };
 180
 181         reserved-memory {
 182                 #address-cells = <2>;
 183                 #size-cells = <2>;
 184                 ranges;
 185
 186                 /*
 187                  * The rk3288 cannot use the memory area above 0xfe000000
 188                  * for dma operations for some reason. While there is
 189                  * probably a better solution available somewhere, we
 190                  * haven't found it yet and while devices with 2GB of ram
 191                  * are not affected, this issue prevents 4GB from booting.
 192                  * So to make these devices at least bootable, block
 193                  * this area for the time being until the real solution
 194                  * is found.
 195                  */
 196                 dma-unusable@fe000000 {
 197                         reg = <0x0 0xfe000000 0x0 0x1000000>;
 198                 };
 199         };
 200
 201         xin24m: oscillator {
 202                 compatible = "fixed-clock";
 203                 clock-frequency = <24000000>;
 204                 clock-output-names = "xin24m";
 205                 #clock-cells = <0>;
 206         };
 207
 208         timer {
 209                 compatible = "arm,armv7-timer";
 210                 arm,cpu-registers-not-fw-configured;
 211                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 212                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 213                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 214                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 215                 clock-frequency = <24000000>;
 216                 arm,no-tick-in-suspend;
 217         };
 218
 219         timer: timer@ff810000 {
 220                 compatible = "rockchip,rk3288-timer";
 221                 reg = <0x0 0xff810000 0x0 0x20>;
 222                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 223                 clocks = <&cru PCLK_TIMER>, <&xin24m>;
 224                 clock-names = "pclk", "timer";
 225         };
 226
 227         display-subsystem {
 228                 compatible = "rockchip,display-subsystem";
 229                 ports = <&vopl_out>, <&vopb_out>;
 230         };
 231
 232         sdmmc: dwmmc@ff0c0000 {
 233                 compatible = "rockchip,rk3288-dw-mshc";
 234                 max-frequency = <150000000>;
 235                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 236                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 237                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 238                 fifo-depth = <0x100>;
 239                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 240                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 241                 resets = <&cru SRST_MMC0>;
 242                 reset-names = "reset";
 243                 status = "disabled";
 244         };
 245
 246         sdio0: dwmmc@ff0d0000 {
 247                 compatible = "rockchip,rk3288-dw-mshc";
 248                 max-frequency = <150000000>;
 249                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 250                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 251                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 252                 fifo-depth = <0x100>;
 253                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 254                 reg = <0x0 0xff0d0000 0x0 0x4000>;
 255                 resets = <&cru SRST_SDIO0>;
 256                 reset-names = "reset";
 257                 status = "disabled";
 258         };
 259
 260         sdio1: dwmmc@ff0e0000 {
 261                 compatible = "rockchip,rk3288-dw-mshc";
 262                 max-frequency = <150000000>;
 263                 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
 264                          <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
 265                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 266                 fifo-depth = <0x100>;
 267                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 268                 reg = <0x0 0xff0e0000 0x0 0x4000>;
 269                 resets = <&cru SRST_SDIO1>;
 270                 reset-names = "reset";
 271                 status = "disabled";
 272         };
 273
 274         emmc: dwmmc@ff0f0000 {
 275                 compatible = "rockchip,rk3288-dw-mshc";
 276                 max-frequency = <150000000>;
 277                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 278                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 279                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 280                 fifo-depth = <0x100>;
 281                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 282                 reg = <0x0 0xff0f0000 0x0 0x4000>;
 283                 resets = <&cru SRST_EMMC>;
 284                 reset-names = "reset";
 285                 status = "disabled";
 286         };
 287
 288         saradc: saradc@ff100000 {
 289                 compatible = "rockchip,saradc";
 290                 reg = <0x0 0xff100000 0x0 0x100>;
 291                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 292                 #io-channel-cells = <1>;
 293                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 294                 clock-names = "saradc", "apb_pclk";
 295                 resets = <&cru SRST_SARADC>;
 296                 reset-names = "saradc-apb";
 297                 status = "disabled";
 298         };
 299
 300         spi0: spi@ff110000 {
 301                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 302                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 303                 clock-names = "spiclk", "apb_pclk";
 304                 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
 305                 dma-names = "tx", "rx";
 306                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 307                 pinctrl-names = "default";
 308                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 309                 reg = <0x0 0xff110000 0x0 0x1000>;
 310                 #address-cells = <1>;
 311                 #size-cells = <0>;
 312                 status = "disabled";
 313         };
 314
 315         spi1: spi@ff120000 {
 316                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 317                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 318                 clock-names = "spiclk", "apb_pclk";
 319                 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
 320                 dma-names = "tx", "rx";
 321                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 322                 pinctrl-names = "default";
 323                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 324                 reg = <0x0 0xff120000 0x0 0x1000>;
 325                 #address-cells = <1>;
 326                 #size-cells = <0>;
 327                 status = "disabled";
 328         };
 329
 330         spi2: spi@ff130000 {
 331                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 332                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 333                 clock-names = "spiclk", "apb_pclk";
 334                 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
 335                 dma-names = "tx", "rx";
 336                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 337                 pinctrl-names = "default";
 338                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 339                 reg = <0x0 0xff130000 0x0 0x1000>;
 340                 #address-cells = <1>;
 341                 #size-cells = <0>;
 342                 status = "disabled";
 343         };
 344
 345         i2c1: i2c@ff140000 {
 346                 compatible = "rockchip,rk3288-i2c";
 347                 reg = <0x0 0xff140000 0x0 0x1000>;
 348                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 349                 #address-cells = <1>;
 350                 #size-cells = <0>;
 351                 clock-names = "i2c";
 352                 clocks = <&cru PCLK_I2C1>;
 353                 pinctrl-names = "default";
 354                 pinctrl-0 = <&i2c1_xfer>;
 355                 status = "disabled";
 356         };
 357
 358         i2c3: i2c@ff150000 {
 359                 compatible = "rockchip,rk3288-i2c";
 360                 reg = <0x0 0xff150000 0x0 0x1000>;
 361                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 362                 #address-cells = <1>;
 363                 #size-cells = <0>;
 364                 clock-names = "i2c";
 365                 clocks = <&cru PCLK_I2C3>;
 366                 pinctrl-names = "default";
 367                 pinctrl-0 = <&i2c3_xfer>;
 368                 status = "disabled";
 369         };
 370
 371         i2c4: i2c@ff160000 {
 372                 compatible = "rockchip,rk3288-i2c";
 373                 reg = <0x0 0xff160000 0x0 0x1000>;
 374                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 375                 #address-cells = <1>;
 376                 #size-cells = <0>;
 377                 clock-names = "i2c";
 378                 clocks = <&cru PCLK_I2C4>;
 379                 pinctrl-names = "default";
 380                 pinctrl-0 = <&i2c4_xfer>;
 381                 status = "disabled";
 382         };
 383
 384         i2c5: i2c@ff170000 {
 385                 compatible = "rockchip,rk3288-i2c";
 386                 reg = <0x0 0xff170000 0x0 0x1000>;
 387                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 388                 #address-cells = <1>;
 389                 #size-cells = <0>;
 390                 clock-names = "i2c";
 391                 clocks = <&cru PCLK_I2C5>;
 392                 pinctrl-names = "default";
 393                 pinctrl-0 = <&i2c5_xfer>;
 394                 status = "disabled";
 395         };
 396
 397         uart0: serial@ff180000 {
 398                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 399                 reg = <0x0 0xff180000 0x0 0x100>;
 400                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 401                 reg-shift = <2>;
 402                 reg-io-width = <4>;
 403                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 404                 clock-names = "baudclk", "apb_pclk";
 405                 pinctrl-names = "default";
 406                 pinctrl-0 = <&uart0_xfer>;
 407                 status = "disabled";
 408         };
 409
 410         uart1: serial@ff190000 {
 411                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 412                 reg = <0x0 0xff190000 0x0 0x100>;
 413                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 414                 reg-shift = <2>;
 415                 reg-io-width = <4>;
 416                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 417                 clock-names = "baudclk", "apb_pclk";
 418                 pinctrl-names = "default";
 419                 pinctrl-0 = <&uart1_xfer>;
 420                 status = "disabled";
 421         };
 422
 423         uart2: serial@ff690000 {
 424                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 425                 reg = <0x0 0xff690000 0x0 0x100>;
 426                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 427                 reg-shift = <2>;
 428                 reg-io-width = <4>;
 429                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 430                 clock-names = "baudclk", "apb_pclk";
 431                 pinctrl-names = "default";
 432                 pinctrl-0 = <&uart2_xfer>;
 433                 status = "disabled";
 434         };
 435
 436         uart3: serial@ff1b0000 {
 437                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 438                 reg = <0x0 0xff1b0000 0x0 0x100>;
 439                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 440                 reg-shift = <2>;
 441                 reg-io-width = <4>;
 442                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 443                 clock-names = "baudclk", "apb_pclk";
 444                 pinctrl-names = "default";
 445                 pinctrl-0 = <&uart3_xfer>;
 446                 status = "disabled";
 447         };
 448
 449         uart4: serial@ff1c0000 {
 450                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 451                 reg = <0x0 0xff1c0000 0x0 0x100>;
 452                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 453                 reg-shift = <2>;
 454                 reg-io-width = <4>;
 455                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 456                 clock-names = "baudclk", "apb_pclk";
 457                 pinctrl-names = "default";
 458                 pinctrl-0 = <&uart4_xfer>;
 459                 status = "disabled";
 460         };
 461
 462         thermal-zones {
 463                 reserve_thermal: reserve_thermal {
 464                         polling-delay-passive = <1000>; /* milliseconds */
 465                         polling-delay = <5000>; /* milliseconds */
 466
 467                         thermal-sensors = <&tsadc 0>;
 468                 };
 469
 470                 cpu_thermal: cpu_thermal {
 471                         polling-delay-passive = <100>; /* milliseconds */
 472                         polling-delay = <5000>; /* milliseconds */
 473
 474                         thermal-sensors = <&tsadc 1>;
 475
 476                         trips {
 477                                 cpu_alert0: cpu_alert0 {
 478                                         temperature = <70000>; /* millicelsius */
 479                                         hysteresis = <2000>; /* millicelsius */
 480                                         type = "passive";
 481                                 };
 482                                 cpu_alert1: cpu_alert1 {
 483                                         temperature = <75000>; /* millicelsius */
 484                                         hysteresis = <2000>; /* millicelsius */
 485                                         type = "passive";
 486                                 };
 487                                 cpu_crit: cpu_crit {
 488                                         temperature = <90000>; /* millicelsius */
 489                                         hysteresis = <2000>; /* millicelsius */
 490                                         type = "critical";
 491                                 };
 492                         };
 493
 494                         cooling-maps {
 495                                 map0 {
 496                                         trip = <&cpu_alert0>;
 497                                         cooling-device =
 498                                                 <&cpu0 THERMAL_NO_LIMIT 6>;
 499                                 };
 500                                 map1 {
 501                                         trip = <&cpu_alert1>;
 502                                         cooling-device =
 503                                                 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 504                                 };
 505                         };
 506                 };
 507
 508                 gpu_thermal: gpu_thermal {
 509                         polling-delay-passive = <100>; /* milliseconds */
 510                         polling-delay = <5000>; /* milliseconds */
 511
 512                         thermal-sensors = <&tsadc 2>;
 513
 514                         trips {
 515                                 gpu_alert0: gpu_alert0 {
 516                                         temperature = <70000>; /* millicelsius */
 517                                         hysteresis = <2000>; /* millicelsius */
 518                                         type = "passive";
 519                                 };
 520                                 gpu_crit: gpu_crit {
 521                                         temperature = <90000>; /* millicelsius */
 522                                         hysteresis = <2000>; /* millicelsius */
 523                                         type = "critical";
 524                                 };
 525                         };
 526
 527                         cooling-maps {
 528                                 map0 {
 529                                         trip = <&gpu_alert0>;
 530                                         cooling-device =
 531                                                 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 532                                 };
 533                         };
 534                 };
 535         };
 536
 537         tsadc: tsadc@ff280000 {
 538                 compatible = "rockchip,rk3288-tsadc";
 539                 reg = <0x0 0xff280000 0x0 0x100>;
 540                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 541                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 542                 clock-names = "tsadc", "apb_pclk";
 543                 resets = <&cru SRST_TSADC>;
 544                 reset-names = "tsadc-apb";
 545                 pinctrl-names = "init", "default", "sleep";
 546                 pinctrl-0 = <&otp_gpio>;
 547                 pinctrl-1 = <&otp_out>;
 548                 pinctrl-2 = <&otp_gpio>;
 549                 #thermal-sensor-cells = <1>;
 550                 rockchip,hw-tshut-temp = <95000>;
 551                 status = "disabled";
 552         };
 553
 554         gmac: ethernet@ff290000 {
 555                 compatible = "rockchip,rk3288-gmac";
 556                 reg = <0x0 0xff290000 0x0 0x10000>;
 557                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
 558                                 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 559                 interrupt-names = "macirq", "eth_wake_irq";
 560                 rockchip,grf = <&grf>;
 561                 clocks = <&cru SCLK_MAC>,
 562                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 563                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 564                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 565                 clock-names = "stmmaceth",
 566                         "mac_clk_rx", "mac_clk_tx",
 567                         "clk_mac_ref", "clk_mac_refout",
 568                         "aclk_mac", "pclk_mac";
 569                 resets = <&cru SRST_MAC>;
 570                 reset-names = "stmmaceth";
 571                 status = "disabled";
 572         };
 573
 574         usb_host0_ehci: usb@ff500000 {
 575                 compatible = "generic-ehci";
 576                 reg = <0x0 0xff500000 0x0 0x100>;
 577                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 578                 clocks = <&cru HCLK_USBHOST0>;
 579                 clock-names = "usbhost";
 580                 phys = <&usbphy1>;
 581                 phy-names = "usb";
 582                 status = "disabled";
 583         };
 584
 585         /* NOTE: ohci@ff520000 doesn't actually work on hardware */
 586
 587         usb_host1: usb@ff540000 {
 588                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 589                                 "snps,dwc2";
 590                 reg = <0x0 0xff540000 0x0 0x40000>;
 591                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 592                 clocks = <&cru HCLK_USBHOST1>;
 593                 clock-names = "otg";
 594                 dr_mode = "host";
 595                 phys = <&usbphy2>;
 596                 phy-names = "usb2-phy";
 597                 status = "disabled";
 598         };
 599
 600         usb_otg: usb@ff580000 {
 601                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 602                                 "snps,dwc2";
 603                 reg = <0x0 0xff580000 0x0 0x40000>;
 604                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 605                 clocks = <&cru HCLK_OTG0>;
 606                 clock-names = "otg";
 607                 dr_mode = "otg";
 608                 g-np-tx-fifo-size = <16>;
 609                 g-rx-fifo-size = <275>;
 610                 g-tx-fifo-size = <256 128 128 64 64 32>;
 611                 phys = <&usbphy0>;
 612                 phy-names = "usb2-phy";
 613                 status = "disabled";
 614         };
 615
 616         usb_hsic: usb@ff5c0000 {
 617                 compatible = "generic-ehci";
 618                 reg = <0x0 0xff5c0000 0x0 0x100>;
 619                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 620                 clocks = <&cru HCLK_HSIC>;
 621                 clock-names = "usbhost";
 622                 status = "disabled";
 623         };
 624
 625         i2c0: i2c@ff650000 {
 626                 compatible = "rockchip,rk3288-i2c";
 627                 reg = <0x0 0xff650000 0x0 0x1000>;
 628                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 629                 #address-cells = <1>;
 630                 #size-cells = <0>;
 631                 clock-names = "i2c";
 632                 clocks = <&cru PCLK_I2C0>;
 633                 pinctrl-names = "default";
 634                 pinctrl-0 = <&i2c0_xfer>;
 635                 status = "disabled";
 636         };
 637
 638         i2c2: i2c@ff660000 {
 639                 compatible = "rockchip,rk3288-i2c";
 640                 reg = <0x0 0xff660000 0x0 0x1000>;
 641                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 642                 #address-cells = <1>;
 643                 #size-cells = <0>;
 644                 clock-names = "i2c";
 645                 clocks = <&cru PCLK_I2C2>;
 646                 pinctrl-names = "default";
 647                 pinctrl-0 = <&i2c2_xfer>;
 648                 status = "disabled";
 649         };
 650
 651         pwm0: pwm@ff680000 {
 652                 compatible = "rockchip,rk3288-pwm";
 653                 reg = <0x0 0xff680000 0x0 0x10>;
 654                 #pwm-cells = <3>;
 655                 pinctrl-names = "default";
 656                 pinctrl-0 = <&pwm0_pin>;
 657                 clocks = <&cru PCLK_PWM>;
 658                 clock-names = "pwm";
 659                 status = "disabled";
 660         };
 661
 662         pwm1: pwm@ff680010 {
 663                 compatible = "rockchip,rk3288-pwm";
 664                 reg = <0x0 0xff680010 0x0 0x10>;
 665                 #pwm-cells = <3>;
 666                 pinctrl-names = "default";
 667                 pinctrl-0 = <&pwm1_pin>;
 668                 clocks = <&cru PCLK_PWM>;
 669                 clock-names = "pwm";
 670                 status = "disabled";
 671         };
 672
 673         pwm2: pwm@ff680020 {
 674                 compatible = "rockchip,rk3288-pwm";
 675                 reg = <0x0 0xff680020 0x0 0x10>;
 676                 #pwm-cells = <3>;
 677                 pinctrl-names = "default";
 678                 pinctrl-0 = <&pwm2_pin>;
 679                 clocks = <&cru PCLK_PWM>;
 680                 clock-names = "pwm";
 681                 status = "disabled";
 682         };
 683
 684         pwm3: pwm@ff680030 {
 685                 compatible = "rockchip,rk3288-pwm";
 686                 reg = <0x0 0xff680030 0x0 0x10>;
 687                 #pwm-cells = <2>;
 688                 pinctrl-names = "default";
 689                 pinctrl-0 = <&pwm3_pin>;
 690                 clocks = <&cru PCLK_PWM>;
 691                 clock-names = "pwm";
 692                 status = "disabled";
 693         };
 694
 695         bus_intmem@ff700000 {
 696                 compatible = "mmio-sram";
 697                 reg = <0x0 0xff700000 0x0 0x18000>;
 698                 #address-cells = <1>;
 699                 #size-cells = <1>;
 700                 ranges = <0 0x0 0xff700000 0x18000>;
 701                 smp-sram@0 {
 702                         compatible = "rockchip,rk3066-smp-sram";
 703                         reg = <0x00 0x10>;
 704                 };
 705         };
 706
 707         sram@ff720000 {
 708                 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
 709                 reg = <0x0 0xff720000 0x0 0x1000>;
 710         };
 711
 712         pmu: power-management@ff730000 {
 713                 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
 714                 reg = <0x0 0xff730000 0x0 0x100>;
 715
 716                 power: power-controller {
 717                         compatible = "rockchip,rk3288-power-controller";
 718                         #power-domain-cells = <1>;
 719                         #address-cells = <1>;
 720                         #size-cells = <0>;
 721
 722                         assigned-clocks = <&cru SCLK_EDP_24M>;
 723                         assigned-clock-parents = <&xin24m>;
 724
 725                         /*
 726                          * Note: Although SCLK_* are the working clocks
 727                          * of device without including on the NOC, needed for
 728                          * synchronous reset.
 729                          *
 730                          * The clocks on the which NOC:
 731                          * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 732                          * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
 733                          * ACLK_RGA is on ACLK_RGA_NIU.
 734                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 735                          *
 736                          * Which clock are device clocks:
 737                          *      clocks          devices
 738                          *      *_IEP           IEP:Image Enhancement Processor
 739                          *      *_ISP           ISP:Image Signal Processing
 740                          *      *_VIP           VIP:Video Input Processor
 741                          *      *_VOP*          VOP:Visual Output Processor
 742                          *      *_RGA           RGA
 743                          *      *_EDP*          EDP
 744                          *      *_LVDS_*        LVDS
 745                          *      *_HDMI          HDMI
 746                          *      *_MIPI_*        MIPI
 747                          */
 748                         power-domain@RK3288_PD_VIO {
 749                                 reg = <RK3288_PD_VIO>;
 750                                 clocks = <&cru ACLK_IEP>,
 751                                          <&cru ACLK_ISP>,
 752                                          <&cru ACLK_RGA>,
 753                                          <&cru ACLK_VIP>,
 754                                          <&cru ACLK_VOP0>,
 755                                          <&cru ACLK_VOP1>,
 756                                          <&cru DCLK_VOP0>,
 757                                          <&cru DCLK_VOP1>,
 758                                          <&cru HCLK_IEP>,
 759                                          <&cru HCLK_ISP>,
 760                                          <&cru HCLK_RGA>,
 761                                          <&cru HCLK_VIP>,
 762                                          <&cru HCLK_VOP0>,
 763                                          <&cru HCLK_VOP1>,
 764                                          <&cru PCLK_EDP_CTRL>,
 765                                          <&cru PCLK_HDMI_CTRL>,
 766                                          <&cru PCLK_LVDS_PHY>,
 767                                          <&cru PCLK_MIPI_CSI>,
 768                                          <&cru PCLK_MIPI_DSI0>,
 769                                          <&cru PCLK_MIPI_DSI1>,
 770                                          <&cru SCLK_EDP_24M>,
 771                                          <&cru SCLK_EDP>,
 772                                          <&cru SCLK_ISP_JPE>,
 773                                          <&cru SCLK_ISP>,
 774                                          <&cru SCLK_RGA>;
 775                                 pm_qos = <&qos_vio0_iep>,
 776                                          <&qos_vio1_vop>,
 777                                          <&qos_vio1_isp_w0>,
 778                                          <&qos_vio1_isp_w1>,
 779                                          <&qos_vio0_vop>,
 780                                          <&qos_vio0_vip>,
 781                                          <&qos_vio2_rga_r>,
 782                                          <&qos_vio2_rga_w>,
 783                                          <&qos_vio1_isp_r>;
 784                         };
 785
 786                         /*
 787                          * Note: The following 3 are HEVC(H.265) clocks,
 788                          * and on the ACLK_HEVC_NIU (NOC).
 789                          */
 790                         power-domain@RK3288_PD_HEVC {
 791                                 reg = <RK3288_PD_HEVC>;
 792                                 clocks = <&cru ACLK_HEVC>,
 793                                          <&cru SCLK_HEVC_CABAC>,
 794                                          <&cru SCLK_HEVC_CORE>;
 795                                 pm_qos = <&qos_hevc_r>,
 796                                          <&qos_hevc_w>;
 797                         };
 798
 799                         /*
 800                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
 801                          * (video endecoder & decoder) clocks that on the
 802                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
 803                          */
 804                         power-domain@RK3288_PD_VIDEO {
 805                                 reg = <RK3288_PD_VIDEO>;
 806                                 clocks = <&cru ACLK_VCODEC>,
 807                                          <&cru HCLK_VCODEC>;
 808                                 pm_qos = <&qos_video>;
 809                         };
 810
 811                         /*
 812                          * Note: ACLK_GPU is the GPU clock,
 813                          * and on the ACLK_GPU_NIU (NOC).
 814                          */
 815                         power-domain@RK3288_PD_GPU {
 816                                 reg = <RK3288_PD_GPU>;
 817                                 clocks = <&cru ACLK_GPU>;
 818                                 pm_qos = <&qos_gpu_r>,
 819                                          <&qos_gpu_w>;
 820                         };
 821                 };
 822
 823                 reboot-mode {
 824                         compatible = "syscon-reboot-mode";
 825                         offset = <0x94>;
 826                         mode-normal = <BOOT_NORMAL>;
 827                         mode-recovery = <BOOT_RECOVERY>;
 828                         mode-bootloader = <BOOT_FASTBOOT>;
 829                         mode-loader = <BOOT_BL_DOWNLOAD>;
 830                 };
 831         };
 832
 833         sgrf: syscon@ff740000 {
 834                 compatible = "rockchip,rk3288-sgrf", "syscon";
 835                 reg = <0x0 0xff740000 0x0 0x1000>;
 836         };
 837
 838         cru: clock-controller@ff760000 {
 839                 compatible = "rockchip,rk3288-cru";
 840                 reg = <0x0 0xff760000 0x0 0x1000>;
 841                 rockchip,grf = <&grf>;
 842                 #clock-cells = <1>;
 843                 #reset-cells = <1>;
 844                 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 845                                   <&cru PLL_NPLL>, <&cru ACLK_CPU>,
 846                                   <&cru HCLK_CPU>, <&cru PCLK_CPU>,
 847                                   <&cru ACLK_PERI>, <&cru HCLK_PERI>,
 848                                   <&cru PCLK_PERI>;
 849                 assigned-clock-rates = <594000000>, <400000000>,
 850                                        <500000000>, <300000000>,
 851                                        <150000000>, <75000000>,
 852                                        <300000000>, <150000000>,
 853                                        <75000000>;
 854         };
 855
 856         grf: syscon@ff770000 {
 857                 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
 858                 reg = <0x0 0xff770000 0x0 0x1000>;
 859
 860                 edp_phy: edp-phy {
 861                         compatible = "rockchip,rk3288-dp-phy";
 862                         clocks = <&cru SCLK_EDP_24M>;
 863                         clock-names = "24m";
 864                         #phy-cells = <0>;
 865                         status = "disabled";
 866                 };
 867
 868                 io_domains: io-domains {
 869                         compatible = "rockchip,rk3288-io-voltage-domain";
 870                         status = "disabled";
 871                 };
 872
 873                 usbphy: usbphy {
 874                         compatible = "rockchip,rk3288-usb-phy";
 875                         #address-cells = <1>;
 876                         #size-cells = <0>;
 877                         status = "disabled";
 878
 879                         usbphy0: usb-phy@320 {
 880                                 #phy-cells = <0>;
 881                                 reg = <0x320>;
 882                                 clocks = <&cru SCLK_OTGPHY0>;
 883                                 clock-names = "phyclk";
 884                                 #clock-cells = <0>;
 885                         };
 886
 887                         usbphy1: usb-phy@334 {
 888                                 #phy-cells = <0>;
 889                                 reg = <0x334>;
 890                                 clocks = <&cru SCLK_OTGPHY1>;
 891                                 clock-names = "phyclk";
 892                                 #clock-cells = <0>;
 893                         };
 894
 895                         usbphy2: usb-phy@348 {
 896                                 #phy-cells = <0>;
 897                                 reg = <0x348>;
 898                                 clocks = <&cru SCLK_OTGPHY2>;
 899                                 clock-names = "phyclk";
 900                                 #clock-cells = <0>;
 901                         };
 902                 };
 903         };
 904
 905         wdt: watchdog@ff800000 {
 906                 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
 907                 reg = <0x0 0xff800000 0x0 0x100>;
 908                 clocks = <&cru PCLK_WDT>;
 909                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 910                 status = "disabled";
 911         };
 912
 913         spdif: sound@ff8b0000 {
 914                 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
 915                 reg = <0x0 0xff8b0000 0x0 0x10000>;
 916                 #sound-dai-cells = <0>;
 917                 clock-names = "hclk", "mclk";
 918                 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
 919                 dmas = <&dmac_bus_s 3>;
 920                 dma-names = "tx";
 921                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 922                 pinctrl-names = "default";
 923                 pinctrl-0 = <&spdif_tx>;
 924                 rockchip,grf = <&grf>;
 925                 status = "disabled";
 926         };
 927
 928         i2s: i2s@ff890000 {
 929                 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
 930                 reg = <0x0 0xff890000 0x0 0x10000>;
 931                 #sound-dai-cells = <0>;
 932                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 933                 #address-cells = <1>;
 934                 #size-cells = <0>;
 935                 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
 936                 dma-names = "tx", "rx";
 937                 clock-names = "i2s_hclk", "i2s_clk";
 938                 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
 939                 pinctrl-names = "default";
 940                 pinctrl-0 = <&i2s0_bus>;
 941                 rockchip,playback-channels = <8>;
 942                 rockchip,capture-channels = <2>;
 943                 status = "disabled";
 944         };
 945
 946         crypto: crypto@ff8a0000 {
 947                 compatible = "rockchip,rk3288-crypto";
 948                 reg = <0x0 0xff8a0000 0x0 0x4000>;
 949                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 950                 clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>,
 951                          <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>;
 952                 clock-names = "aclk", "hclk", "sclk", "apb_pclk";
 953                 resets = <&cru SRST_CRYPTO>;
 954                 reset-names = "crypto-rst";
 955                 status = "okay";
 956         };
 957
 958         iep_mmu: iommu@ff900800 {
 959                 compatible = "rockchip,iommu";
 960                 reg = <0x0 0xff900800 0x0 0x40>;
 961                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
 962                 interrupt-names = "iep_mmu";
 963                 #iommu-cells = <0>;
 964                 status = "disabled";
 965         };
 966
 967         isp_mmu: iommu@ff914000 {
 968                 compatible = "rockchip,iommu";
 969                 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
 970                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 971                 interrupt-names = "isp_mmu";
 972                 #iommu-cells = <0>;
 973                 rockchip,disable-mmu-reset;
 974                 status = "disabled";
 975         };
 976
 977         vopb: vop@ff930000 {
 978                 compatible = "rockchip,rk3288-vop";
 979                 reg = <0x0 0xff930000 0x0 0x19c>;
 980                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 981                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
 982                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 983                 power-domains = <&power RK3288_PD_VIO>;
 984                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
 985                 reset-names = "axi", "ahb", "dclk";
 986                 iommus = <&vopb_mmu>;
 987                 status = "disabled";
 988
 989                 vopb_out: port {
 990                         #address-cells = <1>;
 991                         #size-cells = <0>;
 992
 993                         vopb_out_hdmi: endpoint@0 {
 994                                 reg = <0>;
 995                                 remote-endpoint = <&hdmi_in_vopb>;
 996                         };
 997
 998                         vopb_out_edp: endpoint@1 {
 999                                 reg = <1>;
1000                                 remote-endpoint = <&edp_in_vopb>;
1001                         };
1002
1003                         vopb_out_mipi: endpoint@2 {
1004                                 reg = <2>;
1005                                 remote-endpoint = <&mipi_in_vopb>;
1006                         };
1007                 };
1008         };
1009
1010         vopb_mmu: iommu@ff930300 {
1011                 compatible = "rockchip,iommu";
1012                 reg = <0x0 0xff930300 0x0 0x100>;
1013                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1014                 interrupt-names = "vopb_mmu";
1015                 power-domains = <&power RK3288_PD_VIO>;
1016                 #iommu-cells = <0>;
1017                 status = "disabled";
1018         };
1019
1020         vopl: vop@ff940000 {
1021                 compatible = "rockchip,rk3288-vop";
1022                 reg = <0x0 0xff940000 0x0 0x19c>;
1023                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1024                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1025                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1026                 power-domains = <&power RK3288_PD_VIO>;
1027                 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
1028                 reset-names = "axi", "ahb", "dclk";
1029                 iommus = <&vopl_mmu>;
1030                 status = "disabled";
1031
1032                 vopl_out: port {
1033                         #address-cells = <1>;
1034                         #size-cells = <0>;
1035
1036                         vopl_out_hdmi: endpoint@0 {
1037                                 reg = <0>;
1038                                 remote-endpoint = <&hdmi_in_vopl>;
1039                         };
1040
1041                         vopl_out_edp: endpoint@1 {
1042                                 reg = <1>;
1043                                 remote-endpoint = <&edp_in_vopl>;
1044                         };
1045
1046                         vopl_out_mipi: endpoint@2 {
1047                                 reg = <2>;
1048                                 remote-endpoint = <&mipi_in_vopl>;
1049                         };
1050                 };
1051         };
1052
1053         vopl_mmu: iommu@ff940300 {
1054                 compatible = "rockchip,iommu";
1055                 reg = <0x0 0xff940300 0x0 0x100>;
1056                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1057                 interrupt-names = "vopl_mmu";
1058                 power-domains = <&power RK3288_PD_VIO>;
1059                 #iommu-cells = <0>;
1060                 status = "disabled";
1061         };
1062
1063         mipi_dsi: mipi@ff960000 {
1064                 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
1065                 reg = <0x0 0xff960000 0x0 0x4000>;
1066                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1067                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
1068                 clock-names = "ref", "pclk";
1069                 power-domains = <&power RK3288_PD_VIO>;
1070                 rockchip,grf = <&grf>;
1071                 #address-cells = <1>;
1072                 #size-cells = <0>;
1073                 status = "disabled";
1074
1075                 ports {
1076                         mipi_in: port {
1077                                 #address-cells = <1>;
1078                                 #size-cells = <0>;
1079                                 mipi_in_vopb: endpoint@0 {
1080                                         reg = <0>;
1081                                         remote-endpoint = <&vopb_out_mipi>;
1082                                 };
1083                                 mipi_in_vopl: endpoint@1 {
1084                                         reg = <1>;
1085                                         remote-endpoint = <&vopl_out_mipi>;
1086                                 };
1087                         };
1088                 };
1089         };
1090
1091         edp: dp@ff970000 {
1092                 compatible = "rockchip,rk3288-dp";
1093                 reg = <0x0 0xff970000 0x0 0x4000>;
1094                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1095                 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1096                 clock-names = "dp", "pclk";
1097                 phys = <&edp_phy>;
1098                 phy-names = "dp";
1099                 power-domains = <&power RK3288_PD_VIO>;
1100                 resets = <&cru SRST_EDP>;
1101                 reset-names = "dp";
1102                 rockchip,grf = <&grf>;
1103                 status = "disabled";
1104
1105                 ports {
1106                         #address-cells = <1>;
1107                         #size-cells = <0>;
1108                         edp_in: port@0 {
1109                                 reg = <0>;
1110                                 #address-cells = <1>;
1111                                 #size-cells = <0>;
1112                                 edp_in_vopb: endpoint@0 {
1113                                         reg = <0>;
1114                                         remote-endpoint = <&vopb_out_edp>;
1115                                 };
1116                                 edp_in_vopl: endpoint@1 {
1117                                         reg = <1>;
1118                                         remote-endpoint = <&vopl_out_edp>;
1119                                 };
1120                         };
1121                 };
1122         };
1123
1124         hdmi: hdmi@ff980000 {
1125                 compatible = "rockchip,rk3288-dw-hdmi";
1126                 reg = <0x0 0xff980000 0x0 0x20000>;
1127                 reg-io-width = <4>;
1128                 #sound-dai-cells = <0>;
1129                 rockchip,grf = <&grf>;
1130                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1131                 clocks = <&cru  PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
1132                 clock-names = "iahb", "isfr";
1133                 power-domains = <&power RK3288_PD_VIO>;
1134                 status = "disabled";
1135
1136                 ports {
1137                         hdmi_in: port {
1138                                 #address-cells = <1>;
1139                                 #size-cells = <0>;
1140                                 hdmi_in_vopb: endpoint@0 {
1141                                         reg = <0>;
1142                                         remote-endpoint = <&vopb_out_hdmi>;
1143                                 };
1144                                 hdmi_in_vopl: endpoint@1 {
1145                                         reg = <1>;
1146                                         remote-endpoint = <&vopl_out_hdmi>;
1147                                 };
1148                         };
1149                 };
1150         };
1151
1152         vpu_mmu: iommu@ff9a0800 {
1153                 compatible = "rockchip,iommu";
1154                 reg = <0x0 0xff9a0800 0x0 0x100>;
1155                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1156                 interrupt-names = "vpu_mmu";
1157                 #iommu-cells = <0>;
1158                 status = "disabled";
1159         };
1160
1161         hevc_mmu: iommu@ff9c0440 {
1162                 compatible = "rockchip,iommu";
1163                 reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>;
1164                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1165                 interrupt-names = "hevc_mmu";
1166                 #iommu-cells = <0>;
1167                 status = "disabled";
1168         };
1169
1170         gpu: gpu@ffa30000 {
1171                 compatible = "rockchip,rk3288-mali", "arm,mali-t760";
1172                 reg = <0x0 0xffa30000 0x0 0x10000>;
1173                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1174                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1175                              <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1176                 interrupt-names = "job", "mmu", "gpu";
1177                 clocks = <&cru ACLK_GPU>;
1178                 operating-points-v2 = <&gpu_opp_table>;
1179                 power-domains = <&power RK3288_PD_GPU>;
1180                 status = "disabled";
1181         };
1182
1183         gpu_opp_table: gpu-opp-table {
1184                 compatible = "operating-points-v2";
1185
1186                 opp-100000000 {
1187                         opp-hz = /bits/ 64 <100000000>;
1188                         opp-microvolt = <950000>;
1189                 };
1190                 opp-200000000 {
1191                         opp-hz = /bits/ 64 <200000000>;
1192                         opp-microvolt = <950000>;
1193                 };
1194                 opp-300000000 {
1195                         opp-hz = /bits/ 64 <300000000>;
1196                         opp-microvolt = <1000000>;
1197                 };
1198                 opp-400000000 {
1199                         opp-hz = /bits/ 64 <400000000>;
1200                         opp-microvolt = <1100000>;
1201                 };
1202                 opp-500000000 {
1203                         opp-hz = /bits/ 64 <500000000>;
1204                         opp-microvolt = <1200000>;
1205                 };
1206                 opp-600000000 {
1207                         opp-hz = /bits/ 64 <600000000>;
1208                         opp-microvolt = <1250000>;
1209                 };
1210         };
1211
1212         qos_gpu_r: qos@ffaa0000 {
1213                 compatible = "syscon";
1214                 reg = <0x0 0xffaa0000 0x0 0x20>;
1215         };
1216
1217         qos_gpu_w: qos@ffaa0080 {
1218                 compatible = "syscon";
1219                 reg = <0x0 0xffaa0080 0x0 0x20>;
1220         };
1221
1222         qos_vio1_vop: qos@ffad0000 {
1223                 compatible = "syscon";
1224                 reg = <0x0 0xffad0000 0x0 0x20>;
1225         };
1226
1227         qos_vio1_isp_w0: qos@ffad0100 {
1228                 compatible = "syscon";
1229                 reg = <0x0 0xffad0100 0x0 0x20>;
1230         };
1231
1232         qos_vio1_isp_w1: qos@ffad0180 {
1233                 compatible = "syscon";
1234                 reg = <0x0 0xffad0180 0x0 0x20>;
1235         };
1236
1237         qos_vio0_vop: qos@ffad0400 {
1238                 compatible = "syscon";
1239                 reg = <0x0 0xffad0400 0x0 0x20>;
1240         };
1241
1242         qos_vio0_vip: qos@ffad0480 {
1243                 compatible = "syscon";
1244                 reg = <0x0 0xffad0480 0x0 0x20>;
1245         };
1246
1247         qos_vio0_iep: qos@ffad0500 {
1248                 compatible = "syscon";
1249                 reg = <0x0 0xffad0500 0x0 0x20>;
1250         };
1251
1252         qos_vio2_rga_r: qos@ffad0800 {
1253                 compatible = "syscon";
1254                 reg = <0x0 0xffad0800 0x0 0x20>;
1255         };
1256
1257         qos_vio2_rga_w: qos@ffad0880 {
1258                 compatible = "syscon";
1259                 reg = <0x0 0xffad0880 0x0 0x20>;
1260         };
1261
1262         qos_vio1_isp_r: qos@ffad0900 {
1263                 compatible = "syscon";
1264                 reg = <0x0 0xffad0900 0x0 0x20>;
1265         };
1266
1267         qos_video: qos@ffae0000 {
1268                 compatible = "syscon";
1269                 reg = <0x0 0xffae0000 0x0 0x20>;
1270         };
1271
1272         qos_hevc_r: qos@ffaf0000 {
1273                 compatible = "syscon";
1274                 reg = <0x0 0xffaf0000 0x0 0x20>;
1275         };
1276
1277         qos_hevc_w: qos@ffaf0080 {
1278                 compatible = "syscon";
1279                 reg = <0x0 0xffaf0080 0x0 0x20>;
1280         };
1281
1282         gic: interrupt-controller@ffc01000 {
1283                 compatible = "arm,gic-400";
1284                 interrupt-controller;
1285                 #interrupt-cells = <3>;
1286                 #address-cells = <0>;
1287
1288                 reg = <0x0 0xffc01000 0x0 0x1000>,
1289                       <0x0 0xffc02000 0x0 0x2000>,
1290                       <0x0 0xffc04000 0x0 0x2000>,
1291                       <0x0 0xffc06000 0x0 0x2000>;
1292                 interrupts = <GIC_PPI 9 0xf04>;
1293         };
1294
1295         efuse: efuse@ffb40000 {
1296                 compatible = "rockchip,rk3288-efuse";
1297                 reg = <0x0 0xffb40000 0x0 0x20>;
1298                 #address-cells = <1>;
1299                 #size-cells = <1>;
1300                 clocks = <&cru PCLK_EFUSE256>;
1301                 clock-names = "pclk_efuse";
1302
1303                 cpu_leakage: cpu_leakage@17 {
1304                         reg = <0x17 0x1>;
1305                 };
1306         };
1307
1308         pinctrl: pinctrl {
1309                 compatible = "rockchip,rk3288-pinctrl";
1310                 rockchip,grf = <&grf>;
1311                 rockchip,pmu = <&pmu>;
1312                 #address-cells = <2>;
1313                 #size-cells = <2>;
1314                 ranges;
1315
1316                 gpio0: gpio0@ff750000 {
1317                         compatible = "rockchip,gpio-bank";
1318                         reg = <0x0 0xff750000 0x0 0x100>;
1319                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1320                         clocks = <&cru PCLK_GPIO0>;
1321
1322                         gpio-controller;
1323                         #gpio-cells = <2>;
1324
1325                         interrupt-controller;
1326                         #interrupt-cells = <2>;
1327                 };
1328
1329                 gpio1: gpio1@ff780000 {
1330                         compatible = "rockchip,gpio-bank";
1331                         reg = <0x0 0xff780000 0x0 0x100>;
1332                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1333                         clocks = <&cru PCLK_GPIO1>;
1334
1335                         gpio-controller;
1336                         #gpio-cells = <2>;
1337
1338                         interrupt-controller;
1339                         #interrupt-cells = <2>;
1340                 };
1341
1342                 gpio2: gpio2@ff790000 {
1343                         compatible = "rockchip,gpio-bank";
1344                         reg = <0x0 0xff790000 0x0 0x100>;
1345                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1346                         clocks = <&cru PCLK_GPIO2>;
1347
1348                         gpio-controller;
1349                         #gpio-cells = <2>;
1350
1351                         interrupt-controller;
1352                         #interrupt-cells = <2>;
1353                 };
1354
1355                 gpio3: gpio3@ff7a0000 {
1356                         compatible = "rockchip,gpio-bank";
1357                         reg = <0x0 0xff7a0000 0x0 0x100>;
1358                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1359                         clocks = <&cru PCLK_GPIO3>;
1360
1361                         gpio-controller;
1362                         #gpio-cells = <2>;
1363
1364                         interrupt-controller;
1365                         #interrupt-cells = <2>;
1366                 };
1367
1368                 gpio4: gpio4@ff7b0000 {
1369                         compatible = "rockchip,gpio-bank";
1370                         reg = <0x0 0xff7b0000 0x0 0x100>;
1371                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1372                         clocks = <&cru PCLK_GPIO4>;
1373
1374                         gpio-controller;
1375                         #gpio-cells = <2>;
1376
1377                         interrupt-controller;
1378                         #interrupt-cells = <2>;
1379                 };
1380
1381                 gpio5: gpio5@ff7c0000 {
1382                         compatible = "rockchip,gpio-bank";
1383                         reg = <0x0 0xff7c0000 0x0 0x100>;
1384                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1385                         clocks = <&cru PCLK_GPIO5>;
1386
1387                         gpio-controller;
1388                         #gpio-cells = <2>;
1389
1390                         interrupt-controller;
1391                         #interrupt-cells = <2>;
1392                 };
1393
1394                 gpio6: gpio6@ff7d0000 {
1395                         compatible = "rockchip,gpio-bank";
1396                         reg = <0x0 0xff7d0000 0x0 0x100>;
1397                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1398                         clocks = <&cru PCLK_GPIO6>;
1399
1400                         gpio-controller;
1401                         #gpio-cells = <2>;
1402
1403                         interrupt-controller;
1404                         #interrupt-cells = <2>;
1405                 };
1406
1407                 gpio7: gpio7@ff7e0000 {
1408                         compatible = "rockchip,gpio-bank";
1409                         reg = <0x0 0xff7e0000 0x0 0x100>;
1410                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1411                         clocks = <&cru PCLK_GPIO7>;
1412
1413                         gpio-controller;
1414                         #gpio-cells = <2>;
1415
1416                         interrupt-controller;
1417                         #interrupt-cells = <2>;
1418                 };
1419
1420                 gpio8: gpio8@ff7f0000 {
1421                         compatible = "rockchip,gpio-bank";
1422                         reg = <0x0 0xff7f0000 0x0 0x100>;
1423                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1424                         clocks = <&cru PCLK_GPIO8>;
1425
1426                         gpio-controller;
1427                         #gpio-cells = <2>;
1428
1429                         interrupt-controller;
1430                         #interrupt-cells = <2>;
1431                 };
1432
1433                 hdmi {
1434                         hdmi_ddc: hdmi-ddc {
1435                                 rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>,
1436                                                 <7 20 RK_FUNC_2 &pcfg_pull_none>;
1437                         };
1438                 };
1439
1440                 pcfg_pull_up: pcfg-pull-up {
1441                         bias-pull-up;
1442                 };
1443
1444                 pcfg_pull_down: pcfg-pull-down {
1445                         bias-pull-down;
1446                 };
1447
1448                 pcfg_pull_none: pcfg-pull-none {
1449                         bias-disable;
1450                 };
1451
1452                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1453                         bias-disable;
1454                         drive-strength = <12>;
1455                 };
1456
1457                 suspend {
1458                         global_pwroff: global-pwroff {
1459                                 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1460                         };
1461
1462                         ddrio_pwroff: ddrio-pwroff {
1463                                 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1464                         };
1465
1466                         ddr0_retention: ddr0-retention {
1467                                 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1468                         };
1469
1470                         ddr1_retention: ddr1-retention {
1471                                 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1472                         };
1473                 };
1474
1475                 edp {
1476                         edp_hpd: edp-hpd {
1477                                 rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>;
1478                         };
1479                 };
1480
1481                 i2c0 {
1482                         i2c0_xfer: i2c0-xfer {
1483                                 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1484                                                 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1485                         };
1486                 };
1487
1488                 i2c1 {
1489                         i2c1_xfer: i2c1-xfer {
1490                                 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1491                                                 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1492                         };
1493                 };
1494
1495                 i2c2 {
1496                         i2c2_xfer: i2c2-xfer {
1497                                 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1498                                                 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1499                         };
1500                 };
1501
1502                 i2c3 {
1503                         i2c3_xfer: i2c3-xfer {
1504                                 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1505                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1506                         };
1507                 };
1508
1509                 i2c4 {
1510                         i2c4_xfer: i2c4-xfer {
1511                                 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1512                                                 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1513                         };
1514                 };
1515
1516                 i2c5 {
1517                         i2c5_xfer: i2c5-xfer {
1518                                 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1519                                                 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1520                         };
1521                 };
1522
1523                 i2s0 {
1524                         i2s0_bus: i2s0-bus {
1525                                 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1526                                                 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1527                                                 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1528                                                 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1529                                                 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1530                                                 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1531                         };
1532                 };
1533
1534                 sdmmc {
1535                         sdmmc_clk: sdmmc-clk {
1536                                 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1537                         };
1538
1539                         sdmmc_cmd: sdmmc-cmd {
1540                                 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1541                         };
1542
1543                         sdmmc_cd: sdmmc-cd {
1544                                 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1545                         };
1546
1547                         sdmmc_bus1: sdmmc-bus1 {
1548                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1549                         };
1550
1551                         sdmmc_bus4: sdmmc-bus4 {
1552                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1553                                                 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1554                                                 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1555                                                 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1556                         };
1557                 };
1558
1559                 sdio0 {
1560                         sdio0_bus1: sdio0-bus1 {
1561                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1562                         };
1563
1564                         sdio0_bus4: sdio0-bus4 {
1565                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1566                                                 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1567                                                 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1568                                                 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1569                         };
1570
1571                         sdio0_cmd: sdio0-cmd {
1572                                 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1573                         };
1574
1575                         sdio0_clk: sdio0-clk {
1576                                 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1577                         };
1578
1579                         sdio0_cd: sdio0-cd {
1580                                 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1581                         };
1582
1583                         sdio0_wp: sdio0-wp {
1584                                 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1585                         };
1586
1587                         sdio0_pwr: sdio0-pwr {
1588                                 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1589                         };
1590
1591                         sdio0_bkpwr: sdio0-bkpwr {
1592                                 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1593                         };
1594
1595                         sdio0_int: sdio0-int {
1596                                 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1597                         };
1598                 };
1599
1600                 sdio1 {
1601                         sdio1_bus1: sdio1-bus1 {
1602                                 rockchip,pins = <3 24 4 &pcfg_pull_up>;
1603                         };
1604
1605                         sdio1_bus4: sdio1-bus4 {
1606                                 rockchip,pins = <3 24 4 &pcfg_pull_up>,
1607                                                 <3 25 4 &pcfg_pull_up>,
1608                                                 <3 26 4 &pcfg_pull_up>,
1609                                                 <3 27 4 &pcfg_pull_up>;
1610                         };
1611
1612                         sdio1_cd: sdio1-cd {
1613                                 rockchip,pins = <3 28 4 &pcfg_pull_up>;
1614                         };
1615
1616                         sdio1_wp: sdio1-wp {
1617                                 rockchip,pins = <3 29 4 &pcfg_pull_up>;
1618                         };
1619
1620                         sdio1_bkpwr: sdio1-bkpwr {
1621                                 rockchip,pins = <3 30 4 &pcfg_pull_up>;
1622                         };
1623
1624                         sdio1_int: sdio1-int {
1625                                 rockchip,pins = <3 31 4 &pcfg_pull_up>;
1626                         };
1627
1628                         sdio1_cmd: sdio1-cmd {
1629                                 rockchip,pins = <4 6 4 &pcfg_pull_up>;
1630                         };
1631
1632                         sdio1_clk: sdio1-clk {
1633                                 rockchip,pins = <4 7 4 &pcfg_pull_none>;
1634                         };
1635
1636                         sdio1_pwr: sdio1-pwr {
1637                                 rockchip,pins = <4 9 4 &pcfg_pull_up>;
1638                         };
1639                 };
1640
1641                 emmc {
1642                         emmc_clk: emmc-clk {
1643                                 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1644                         };
1645
1646                         emmc_cmd: emmc-cmd {
1647                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1648                         };
1649
1650                         emmc_pwr: emmc-pwr {
1651                                 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1652                         };
1653
1654                         emmc_bus1: emmc-bus1 {
1655                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1656                         };
1657
1658                         emmc_bus4: emmc-bus4 {
1659                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1660                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1661                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1662                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1663                         };
1664
1665                         emmc_bus8: emmc-bus8 {
1666                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1667                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1668                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1669                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1670                                                 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1671                                                 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1672                                                 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1673                                                 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1674                         };
1675                 };
1676
1677                 spi0 {
1678                         spi0_clk: spi0-clk {
1679                                 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1680                         };
1681                         spi0_cs0: spi0-cs0 {
1682                                 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1683                         };
1684                         spi0_tx: spi0-tx {
1685                                 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1686                         };
1687                         spi0_rx: spi0-rx {
1688                                 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1689                         };
1690                         spi0_cs1: spi0-cs1 {
1691                                 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1692                         };
1693                 };
1694                 spi1 {
1695                         spi1_clk: spi1-clk {
1696                                 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1697                         };
1698                         spi1_cs0: spi1-cs0 {
1699                                 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1700                         };
1701                         spi1_rx: spi1-rx {
1702                                 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1703                         };
1704                         spi1_tx: spi1-tx {
1705                                 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1706                         };
1707                 };
1708
1709                 spi2 {
1710                         spi2_cs1: spi2-cs1 {
1711                                 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1712                         };
1713                         spi2_clk: spi2-clk {
1714                                 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1715                         };
1716                         spi2_cs0: spi2-cs0 {
1717                                 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1718                         };
1719                         spi2_rx: spi2-rx {
1720                                 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1721                         };
1722                         spi2_tx: spi2-tx {
1723                                 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1724                         };
1725                 };
1726
1727                 uart0 {
1728                         uart0_xfer: uart0-xfer {
1729                                 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1730                                                 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1731                         };
1732
1733                         uart0_cts: uart0-cts {
1734                                 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>;
1735                         };
1736
1737                         uart0_rts: uart0-rts {
1738                                 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1739                         };
1740                 };
1741
1742                 uart1 {
1743                         uart1_xfer: uart1-xfer {
1744                                 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1745                                                 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1746                         };
1747
1748                         uart1_cts: uart1-cts {
1749                                 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>;
1750                         };
1751
1752                         uart1_rts: uart1-rts {
1753                                 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1754                         };
1755                 };
1756
1757                 uart2 {
1758                         uart2_xfer: uart2-xfer {
1759                                 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1760                                                 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1761                         };
1762                         /* no rts / cts for uart2 */
1763                 };
1764
1765                 uart3 {
1766                         uart3_xfer: uart3-xfer {
1767                                 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1768                                                 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1769                         };
1770
1771                         uart3_cts: uart3-cts {
1772                                 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>;
1773                         };
1774
1775                         uart3_rts: uart3-rts {
1776                                 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1777                         };
1778                 };
1779
1780                 uart4 {
1781                         uart4_xfer: uart4-xfer {
1782                                 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1783                                                 <5 13 3 &pcfg_pull_none>;
1784                         };
1785
1786                         uart4_cts: uart4-cts {
1787                                 rockchip,pins = <5 14 3 &pcfg_pull_up>;
1788                         };
1789
1790                         uart4_rts: uart4-rts {
1791                                 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1792                         };
1793                 };
1794
1795                 tsadc {
1796                         otp_gpio: otp-gpio {
1797                                 rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
1798                         };
1799
1800                         otp_out: otp-out {
1801                                 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1802                         };
1803                 };
1804
1805                 pwm0 {
1806                         pwm0_pin: pwm0-pin {
1807                                 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1808                         };
1809                 };
1810
1811                 pwm1 {
1812                         pwm1_pin: pwm1-pin {
1813                                 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1814                         };
1815                 };
1816
1817                 pwm2 {
1818                         pwm2_pin: pwm2-pin {
1819                                 rockchip,pins = <7 22 3 &pcfg_pull_none>;
1820                         };
1821                 };
1822
1823                 pwm3 {
1824                         pwm3_pin: pwm3-pin {
1825                                 rockchip,pins = <7 23 3 &pcfg_pull_none>;
1826                         };
1827                 };
1828
1829                 gmac {
1830                         rgmii_pins: rgmii-pins {
1831                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1832                                                 <3 31 3 &pcfg_pull_none>,
1833                                                 <3 26 3 &pcfg_pull_none>,
1834                                                 <3 27 3 &pcfg_pull_none>,
1835                                                 <3 28 3 &pcfg_pull_none_12ma>,
1836                                                 <3 29 3 &pcfg_pull_none_12ma>,
1837                                                 <3 24 3 &pcfg_pull_none_12ma>,
1838                                                 <3 25 3 &pcfg_pull_none_12ma>,
1839                                                 <4 0 3 &pcfg_pull_none>,
1840                                                 <4 5 3 &pcfg_pull_none>,
1841                                                 <4 6 3 &pcfg_pull_none>,
1842                                                 <4 9 3 &pcfg_pull_none_12ma>,
1843                                                 <4 4 3 &pcfg_pull_none_12ma>,
1844                                                 <4 1 3 &pcfg_pull_none>,
1845                                                 <4 3 3 &pcfg_pull_none>;
1846                         };
1847
1848                         rmii_pins: rmii-pins {
1849                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1850                                                 <3 31 3 &pcfg_pull_none>,
1851                                                 <3 28 3 &pcfg_pull_none>,
1852                                                 <3 29 3 &pcfg_pull_none>,
1853                                                 <4 0 3 &pcfg_pull_none>,
1854                                                 <4 5 3 &pcfg_pull_none>,
1855                                                 <4 4 3 &pcfg_pull_none>,
1856                                                 <4 1 3 &pcfg_pull_none>,
1857                                                 <4 2 3 &pcfg_pull_none>,
1858                                                 <4 3 3 &pcfg_pull_none>;
1859                         };
1860                 };
1861
1862                 spdif {
1863                         spdif_tx: spdif-tx {
1864                                 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;
1865                         };
1866                 };
1867         };
1868 };