1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3288-cru.h>
8 #include <dt-bindings/power/rk3288-power.h>
9 #include <dt-bindings/thermal/thermal.h>
10 #include <dt-bindings/soc/rockchip,boot-mode.h>
16 compatible = "rockchip,rk3288";
18 interrupt-parent = <&gic>;
43 compatible = "arm,cortex-a12-pmu";
44 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
45 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
46 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
47 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
48 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
54 enable-method = "rockchip,rk3066-smp";
55 rockchip,pmu = <&pmu>;
59 compatible = "arm,cortex-a12";
61 resets = <&cru SRST_CORE0>;
62 operating-points-v2 = <&cpu_opp_table>;
63 #cooling-cells = <2>; /* min followed by max */
64 clock-latency = <40000>;
65 clocks = <&cru ARMCLK>;
66 dynamic-power-coefficient = <370>;
70 compatible = "arm,cortex-a12";
72 resets = <&cru SRST_CORE1>;
73 operating-points-v2 = <&cpu_opp_table>;
74 #cooling-cells = <2>; /* min followed by max */
75 clock-latency = <40000>;
76 clocks = <&cru ARMCLK>;
77 dynamic-power-coefficient = <370>;
81 compatible = "arm,cortex-a12";
83 resets = <&cru SRST_CORE2>;
84 operating-points-v2 = <&cpu_opp_table>;
85 #cooling-cells = <2>; /* min followed by max */
86 clock-latency = <40000>;
87 clocks = <&cru ARMCLK>;
88 dynamic-power-coefficient = <370>;
92 compatible = "arm,cortex-a12";
94 resets = <&cru SRST_CORE3>;
95 operating-points-v2 = <&cpu_opp_table>;
96 #cooling-cells = <2>; /* min followed by max */
97 clock-latency = <40000>;
98 clocks = <&cru ARMCLK>;
99 dynamic-power-coefficient = <370>;
103 cpu_opp_table: opp-table-0 {
104 compatible = "operating-points-v2";
108 opp-hz = /bits/ 64 <126000000>;
109 opp-microvolt = <900000>;
112 opp-hz = /bits/ 64 <216000000>;
113 opp-microvolt = <900000>;
116 opp-hz = /bits/ 64 <312000000>;
117 opp-microvolt = <900000>;
120 opp-hz = /bits/ 64 <408000000>;
121 opp-microvolt = <900000>;
124 opp-hz = /bits/ 64 <600000000>;
125 opp-microvolt = <900000>;
128 opp-hz = /bits/ 64 <696000000>;
129 opp-microvolt = <950000>;
132 opp-hz = /bits/ 64 <816000000>;
133 opp-microvolt = <1000000>;
136 opp-hz = /bits/ 64 <1008000000>;
137 opp-microvolt = <1050000>;
140 opp-hz = /bits/ 64 <1200000000>;
141 opp-microvolt = <1100000>;
144 opp-hz = /bits/ 64 <1416000000>;
145 opp-microvolt = <1200000>;
148 opp-hz = /bits/ 64 <1512000000>;
149 opp-microvolt = <1300000>;
152 opp-hz = /bits/ 64 <1608000000>;
153 opp-microvolt = <1350000>;
158 #address-cells = <2>;
163 * The rk3288 cannot use the memory area above 0xfe000000
164 * for dma operations for some reason. While there is
165 * probably a better solution available somewhere, we
166 * haven't found it yet and while devices with 2GB of ram
167 * are not affected, this issue prevents 4GB from booting.
168 * So to make these devices at least bootable, block
169 * this area for the time being until the real solution
172 dma-unusable@fe000000 {
173 reg = <0x0 0xfe000000 0x0 0x1000000>;
178 compatible = "fixed-clock";
179 clock-frequency = <24000000>;
180 clock-output-names = "xin24m";
185 compatible = "arm,armv7-timer";
186 arm,cpu-registers-not-fw-configured;
187 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
188 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
189 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
190 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
191 clock-frequency = <24000000>;
192 arm,no-tick-in-suspend;
195 timer: timer@ff810000 {
196 compatible = "rockchip,rk3288-timer";
197 reg = <0x0 0xff810000 0x0 0x20>;
198 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
199 clocks = <&cru PCLK_TIMER>, <&xin24m>;
200 clock-names = "pclk", "timer";
204 compatible = "rockchip,display-subsystem";
205 ports = <&vopl_out>, <&vopb_out>;
208 sdmmc: mmc@ff0c0000 {
209 compatible = "rockchip,rk3288-dw-mshc";
210 max-frequency = <150000000>;
211 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
212 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
213 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
214 fifo-depth = <0x100>;
215 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
216 reg = <0x0 0xff0c0000 0x0 0x4000>;
217 resets = <&cru SRST_MMC0>;
218 reset-names = "reset";
222 sdio0: mmc@ff0d0000 {
223 compatible = "rockchip,rk3288-dw-mshc";
224 max-frequency = <150000000>;
225 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
226 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
227 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
228 fifo-depth = <0x100>;
229 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
230 reg = <0x0 0xff0d0000 0x0 0x4000>;
231 resets = <&cru SRST_SDIO0>;
232 reset-names = "reset";
236 sdio1: mmc@ff0e0000 {
237 compatible = "rockchip,rk3288-dw-mshc";
238 max-frequency = <150000000>;
239 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
240 <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
241 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
242 fifo-depth = <0x100>;
243 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
244 reg = <0x0 0xff0e0000 0x0 0x4000>;
245 resets = <&cru SRST_SDIO1>;
246 reset-names = "reset";
251 compatible = "rockchip,rk3288-dw-mshc";
252 max-frequency = <150000000>;
253 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
254 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
255 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
256 fifo-depth = <0x100>;
257 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
258 reg = <0x0 0xff0f0000 0x0 0x4000>;
259 resets = <&cru SRST_EMMC>;
260 reset-names = "reset";
264 saradc: saradc@ff100000 {
265 compatible = "rockchip,saradc";
266 reg = <0x0 0xff100000 0x0 0x100>;
267 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
268 #io-channel-cells = <1>;
269 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
270 clock-names = "saradc", "apb_pclk";
271 resets = <&cru SRST_SARADC>;
272 reset-names = "saradc-apb";
277 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
278 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
279 clock-names = "spiclk", "apb_pclk";
280 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
281 dma-names = "tx", "rx";
282 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
283 pinctrl-names = "default";
284 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
285 reg = <0x0 0xff110000 0x0 0x1000>;
286 #address-cells = <1>;
292 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
293 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
294 clock-names = "spiclk", "apb_pclk";
295 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
296 dma-names = "tx", "rx";
297 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
298 pinctrl-names = "default";
299 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
300 reg = <0x0 0xff120000 0x0 0x1000>;
301 #address-cells = <1>;
307 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
308 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
309 clock-names = "spiclk", "apb_pclk";
310 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
311 dma-names = "tx", "rx";
312 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
313 pinctrl-names = "default";
314 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
315 reg = <0x0 0xff130000 0x0 0x1000>;
316 #address-cells = <1>;
322 compatible = "rockchip,rk3288-i2c";
323 reg = <0x0 0xff140000 0x0 0x1000>;
324 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
325 #address-cells = <1>;
328 clocks = <&cru PCLK_I2C1>;
329 pinctrl-names = "default";
330 pinctrl-0 = <&i2c1_xfer>;
335 compatible = "rockchip,rk3288-i2c";
336 reg = <0x0 0xff150000 0x0 0x1000>;
337 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
338 #address-cells = <1>;
341 clocks = <&cru PCLK_I2C3>;
342 pinctrl-names = "default";
343 pinctrl-0 = <&i2c3_xfer>;
348 compatible = "rockchip,rk3288-i2c";
349 reg = <0x0 0xff160000 0x0 0x1000>;
350 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
351 #address-cells = <1>;
354 clocks = <&cru PCLK_I2C4>;
355 pinctrl-names = "default";
356 pinctrl-0 = <&i2c4_xfer>;
361 compatible = "rockchip,rk3288-i2c";
362 reg = <0x0 0xff170000 0x0 0x1000>;
363 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
364 #address-cells = <1>;
367 clocks = <&cru PCLK_I2C5>;
368 pinctrl-names = "default";
369 pinctrl-0 = <&i2c5_xfer>;
373 uart0: serial@ff180000 {
374 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
375 reg = <0x0 0xff180000 0x0 0x100>;
376 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
379 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
380 clock-names = "baudclk", "apb_pclk";
381 dmas = <&dmac_peri 1>, <&dmac_peri 2>;
382 dma-names = "tx", "rx";
383 pinctrl-names = "default";
384 pinctrl-0 = <&uart0_xfer>;
388 uart1: serial@ff190000 {
389 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
390 reg = <0x0 0xff190000 0x0 0x100>;
391 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
394 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
395 clock-names = "baudclk", "apb_pclk";
396 dmas = <&dmac_peri 3>, <&dmac_peri 4>;
397 dma-names = "tx", "rx";
398 pinctrl-names = "default";
399 pinctrl-0 = <&uart1_xfer>;
403 uart2: serial@ff690000 {
404 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
405 reg = <0x0 0xff690000 0x0 0x100>;
406 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
409 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
410 clock-names = "baudclk", "apb_pclk";
411 pinctrl-names = "default";
412 pinctrl-0 = <&uart2_xfer>;
416 uart3: serial@ff1b0000 {
417 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
418 reg = <0x0 0xff1b0000 0x0 0x100>;
419 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
422 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
423 clock-names = "baudclk", "apb_pclk";
424 dmas = <&dmac_peri 7>, <&dmac_peri 8>;
425 dma-names = "tx", "rx";
426 pinctrl-names = "default";
427 pinctrl-0 = <&uart3_xfer>;
431 uart4: serial@ff1c0000 {
432 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
433 reg = <0x0 0xff1c0000 0x0 0x100>;
434 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
437 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
438 clock-names = "baudclk", "apb_pclk";
439 dmas = <&dmac_peri 9>, <&dmac_peri 10>;
440 dma-names = "tx", "rx";
441 pinctrl-names = "default";
442 pinctrl-0 = <&uart4_xfer>;
446 dmac_peri: dma-controller@ff250000 {
447 compatible = "arm,pl330", "arm,primecell";
448 reg = <0x0 0xff250000 0x0 0x4000>;
449 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
450 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
452 arm,pl330-broken-no-flushp;
453 arm,pl330-periph-burst;
454 clocks = <&cru ACLK_DMAC2>;
455 clock-names = "apb_pclk";
459 reserve_thermal: reserve-thermal {
460 polling-delay-passive = <1000>; /* milliseconds */
461 polling-delay = <5000>; /* milliseconds */
463 thermal-sensors = <&tsadc 0>;
466 cpu_thermal: cpu-thermal {
467 polling-delay-passive = <100>; /* milliseconds */
468 polling-delay = <5000>; /* milliseconds */
470 thermal-sensors = <&tsadc 1>;
473 cpu_alert0: cpu_alert0 {
474 temperature = <70000>; /* millicelsius */
475 hysteresis = <2000>; /* millicelsius */
478 cpu_alert1: cpu_alert1 {
479 temperature = <75000>; /* millicelsius */
480 hysteresis = <2000>; /* millicelsius */
484 temperature = <90000>; /* millicelsius */
485 hysteresis = <2000>; /* millicelsius */
492 trip = <&cpu_alert0>;
494 <&cpu0 THERMAL_NO_LIMIT 6>,
495 <&cpu1 THERMAL_NO_LIMIT 6>,
496 <&cpu2 THERMAL_NO_LIMIT 6>,
497 <&cpu3 THERMAL_NO_LIMIT 6>;
500 trip = <&cpu_alert1>;
502 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
503 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
504 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
505 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
510 gpu_thermal: gpu-thermal {
511 polling-delay-passive = <100>; /* milliseconds */
512 polling-delay = <5000>; /* milliseconds */
514 thermal-sensors = <&tsadc 2>;
517 gpu_alert0: gpu_alert0 {
518 temperature = <70000>; /* millicelsius */
519 hysteresis = <2000>; /* millicelsius */
523 temperature = <90000>; /* millicelsius */
524 hysteresis = <2000>; /* millicelsius */
531 trip = <&gpu_alert0>;
533 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
539 tsadc: tsadc@ff280000 {
540 compatible = "rockchip,rk3288-tsadc";
541 reg = <0x0 0xff280000 0x0 0x100>;
542 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
543 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
544 clock-names = "tsadc", "apb_pclk";
545 resets = <&cru SRST_TSADC>;
546 reset-names = "tsadc-apb";
547 pinctrl-names = "init", "default", "sleep";
548 pinctrl-0 = <&otp_pin>;
549 pinctrl-1 = <&otp_out>;
550 pinctrl-2 = <&otp_pin>;
551 #thermal-sensor-cells = <1>;
552 rockchip,grf = <&grf>;
553 rockchip,hw-tshut-temp = <95000>;
557 gmac: ethernet@ff290000 {
558 compatible = "rockchip,rk3288-gmac";
559 reg = <0x0 0xff290000 0x0 0x10000>;
560 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
561 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
562 interrupt-names = "macirq", "eth_wake_irq";
563 rockchip,grf = <&grf>;
564 clocks = <&cru SCLK_MAC>,
565 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
566 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
567 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
568 clock-names = "stmmaceth",
569 "mac_clk_rx", "mac_clk_tx",
570 "clk_mac_ref", "clk_mac_refout",
571 "aclk_mac", "pclk_mac";
572 resets = <&cru SRST_MAC>;
573 reset-names = "stmmaceth";
577 usb_host0_ehci: usb@ff500000 {
578 compatible = "generic-ehci";
579 reg = <0x0 0xff500000 0x0 0x100>;
580 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
581 clocks = <&cru HCLK_USBHOST0>;
587 /* NOTE: doesn't work on RK3288, but was fixed on RK3288W */
588 usb_host0_ohci: usb@ff520000 {
589 compatible = "generic-ohci";
590 reg = <0x0 0xff520000 0x0 0x100>;
591 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
592 clocks = <&cru HCLK_USBHOST0>;
598 usb_host1: usb@ff540000 {
599 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
601 reg = <0x0 0xff540000 0x0 0x40000>;
602 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
603 clocks = <&cru HCLK_USBHOST1>;
607 phy-names = "usb2-phy";
608 snps,reset-phy-on-wake;
612 usb_otg: usb@ff580000 {
613 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
615 reg = <0x0 0xff580000 0x0 0x40000>;
616 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
617 clocks = <&cru HCLK_OTG0>;
620 g-np-tx-fifo-size = <16>;
621 g-rx-fifo-size = <275>;
622 g-tx-fifo-size = <256 128 128 64 64 32>;
624 phy-names = "usb2-phy";
628 usb_hsic: usb@ff5c0000 {
629 compatible = "generic-ehci";
630 reg = <0x0 0xff5c0000 0x0 0x100>;
631 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
632 clocks = <&cru HCLK_HSIC>;
636 dmac_bus_ns: dma-controller@ff600000 {
637 compatible = "arm,pl330", "arm,primecell";
638 reg = <0x0 0xff600000 0x0 0x4000>;
639 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
640 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
642 arm,pl330-broken-no-flushp;
643 arm,pl330-periph-burst;
644 clocks = <&cru ACLK_DMAC1>;
645 clock-names = "apb_pclk";
650 compatible = "rockchip,rk3288-i2c";
651 reg = <0x0 0xff650000 0x0 0x1000>;
652 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
653 #address-cells = <1>;
656 clocks = <&cru PCLK_I2C0>;
657 pinctrl-names = "default";
658 pinctrl-0 = <&i2c0_xfer>;
663 compatible = "rockchip,rk3288-i2c";
664 reg = <0x0 0xff660000 0x0 0x1000>;
665 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
666 #address-cells = <1>;
669 clocks = <&cru PCLK_I2C2>;
670 pinctrl-names = "default";
671 pinctrl-0 = <&i2c2_xfer>;
676 compatible = "rockchip,rk3288-pwm";
677 reg = <0x0 0xff680000 0x0 0x10>;
679 pinctrl-names = "default";
680 pinctrl-0 = <&pwm0_pin>;
681 clocks = <&cru PCLK_RKPWM>;
686 compatible = "rockchip,rk3288-pwm";
687 reg = <0x0 0xff680010 0x0 0x10>;
689 pinctrl-names = "default";
690 pinctrl-0 = <&pwm1_pin>;
691 clocks = <&cru PCLK_RKPWM>;
696 compatible = "rockchip,rk3288-pwm";
697 reg = <0x0 0xff680020 0x0 0x10>;
699 pinctrl-names = "default";
700 pinctrl-0 = <&pwm2_pin>;
701 clocks = <&cru PCLK_RKPWM>;
706 compatible = "rockchip,rk3288-pwm";
707 reg = <0x0 0xff680030 0x0 0x10>;
709 pinctrl-names = "default";
710 pinctrl-0 = <&pwm3_pin>;
711 clocks = <&cru PCLK_RKPWM>;
715 bus_intmem: sram@ff700000 {
716 compatible = "mmio-sram";
717 reg = <0x0 0xff700000 0x0 0x18000>;
718 #address-cells = <1>;
720 ranges = <0 0x0 0xff700000 0x18000>;
722 compatible = "rockchip,rk3066-smp-sram";
727 pmu_sram: sram@ff720000 {
728 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
729 reg = <0x0 0xff720000 0x0 0x1000>;
732 pmu: power-management@ff730000 {
733 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
734 reg = <0x0 0xff730000 0x0 0x100>;
736 power: power-controller {
737 compatible = "rockchip,rk3288-power-controller";
738 #power-domain-cells = <1>;
739 #address-cells = <1>;
742 assigned-clocks = <&cru SCLK_EDP_24M>;
743 assigned-clock-parents = <&xin24m>;
746 * Note: Although SCLK_* are the working clocks
747 * of device without including on the NOC, needed for
750 * The clocks on the which NOC:
751 * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
752 * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
753 * ACLK_RGA is on ACLK_RGA_NIU.
754 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
756 * Which clock are device clocks:
758 * *_IEP IEP:Image Enhancement Processor
759 * *_ISP ISP:Image Signal Processing
760 * *_VIP VIP:Video Input Processor
761 * *_VOP* VOP:Visual Output Processor
768 power-domain@RK3288_PD_VIO {
769 reg = <RK3288_PD_VIO>;
770 clocks = <&cru ACLK_IEP>,
784 <&cru PCLK_EDP_CTRL>,
785 <&cru PCLK_HDMI_CTRL>,
786 <&cru PCLK_LVDS_PHY>,
787 <&cru PCLK_MIPI_CSI>,
788 <&cru PCLK_MIPI_DSI0>,
789 <&cru PCLK_MIPI_DSI1>,
795 pm_qos = <&qos_vio0_iep>,
804 #power-domain-cells = <0>;
808 * Note: The following 3 are HEVC(H.265) clocks,
809 * and on the ACLK_HEVC_NIU (NOC).
811 power-domain@RK3288_PD_HEVC {
812 reg = <RK3288_PD_HEVC>;
813 clocks = <&cru ACLK_HEVC>,
814 <&cru SCLK_HEVC_CABAC>,
815 <&cru SCLK_HEVC_CORE>;
816 pm_qos = <&qos_hevc_r>,
818 #power-domain-cells = <0>;
822 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
823 * (video endecoder & decoder) clocks that on the
824 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
826 power-domain@RK3288_PD_VIDEO {
827 reg = <RK3288_PD_VIDEO>;
828 clocks = <&cru ACLK_VCODEC>,
830 pm_qos = <&qos_video>;
831 #power-domain-cells = <0>;
835 * Note: ACLK_GPU is the GPU clock,
836 * and on the ACLK_GPU_NIU (NOC).
838 power-domain@RK3288_PD_GPU {
839 reg = <RK3288_PD_GPU>;
840 clocks = <&cru ACLK_GPU>;
841 pm_qos = <&qos_gpu_r>,
843 #power-domain-cells = <0>;
848 compatible = "syscon-reboot-mode";
850 mode-normal = <BOOT_NORMAL>;
851 mode-recovery = <BOOT_RECOVERY>;
852 mode-bootloader = <BOOT_FASTBOOT>;
853 mode-loader = <BOOT_BL_DOWNLOAD>;
857 sgrf: syscon@ff740000 {
858 compatible = "rockchip,rk3288-sgrf", "syscon";
859 reg = <0x0 0xff740000 0x0 0x1000>;
862 cru: clock-controller@ff760000 {
863 compatible = "rockchip,rk3288-cru";
864 reg = <0x0 0xff760000 0x0 0x1000>;
866 clock-names = "xin24m";
867 rockchip,grf = <&grf>;
870 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
871 <&cru PLL_NPLL>, <&cru ACLK_CPU>,
872 <&cru HCLK_CPU>, <&cru PCLK_CPU>,
873 <&cru ACLK_PERI>, <&cru HCLK_PERI>,
875 assigned-clock-rates = <594000000>, <400000000>,
876 <500000000>, <300000000>,
877 <150000000>, <75000000>,
878 <300000000>, <150000000>,
882 grf: syscon@ff770000 {
883 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
884 reg = <0x0 0xff770000 0x0 0x1000>;
887 compatible = "rockchip,rk3288-dp-phy";
888 clocks = <&cru SCLK_EDP_24M>;
894 io_domains: io-domains {
895 compatible = "rockchip,rk3288-io-voltage-domain";
900 compatible = "rockchip,rk3288-usb-phy";
901 #address-cells = <1>;
905 usbphy0: usb-phy@320 {
908 clocks = <&cru SCLK_OTGPHY0>;
909 clock-names = "phyclk";
911 resets = <&cru SRST_USBOTG_PHY>;
912 reset-names = "phy-reset";
915 usbphy1: usb-phy@334 {
918 clocks = <&cru SCLK_OTGPHY1>;
919 clock-names = "phyclk";
921 resets = <&cru SRST_USBHOST0_PHY>;
922 reset-names = "phy-reset";
925 usbphy2: usb-phy@348 {
928 clocks = <&cru SCLK_OTGPHY2>;
929 clock-names = "phyclk";
931 resets = <&cru SRST_USBHOST1_PHY>;
932 reset-names = "phy-reset";
937 wdt: watchdog@ff800000 {
938 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
939 reg = <0x0 0xff800000 0x0 0x100>;
940 clocks = <&cru PCLK_WDT>;
941 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
945 spdif: sound@ff88b0000 {
946 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
947 reg = <0x0 0xff8b0000 0x0 0x10000>;
948 #sound-dai-cells = <0>;
949 clocks = <&cru SCLK_SPDIF8CH>, <&cru HCLK_SPDIF8CH>;
950 clock-names = "mclk", "hclk";
951 dmas = <&dmac_bus_s 3>;
953 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
954 pinctrl-names = "default";
955 pinctrl-0 = <&spdif_tx>;
956 rockchip,grf = <&grf>;
961 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
962 reg = <0x0 0xff890000 0x0 0x10000>;
963 #sound-dai-cells = <0>;
964 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
965 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>;
966 clock-names = "i2s_clk", "i2s_hclk";
967 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
968 dma-names = "tx", "rx";
969 pinctrl-names = "default";
970 pinctrl-0 = <&i2s0_bus>;
971 rockchip,playback-channels = <8>;
972 rockchip,capture-channels = <2>;
976 crypto: crypto@ff8a0000 {
977 compatible = "rockchip,rk3288-crypto";
978 reg = <0x0 0xff8a0000 0x0 0x4000>;
979 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
980 clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>,
981 <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>;
982 clock-names = "aclk", "hclk", "sclk", "apb_pclk";
983 resets = <&cru SRST_CRYPTO>;
984 reset-names = "crypto-rst";
987 iep_mmu: iommu@ff900800 {
988 compatible = "rockchip,iommu";
989 reg = <0x0 0xff900800 0x0 0x40>;
990 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
991 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
992 clock-names = "aclk", "iface";
997 isp_mmu: iommu@ff914000 {
998 compatible = "rockchip,iommu";
999 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
1000 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1001 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
1002 clock-names = "aclk", "iface";
1004 rockchip,disable-mmu-reset;
1005 status = "disabled";
1009 compatible = "rockchip,rk3288-rga";
1010 reg = <0x0 0xff920000 0x0 0x180>;
1011 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1012 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
1013 clock-names = "aclk", "hclk", "sclk";
1014 power-domains = <&power RK3288_PD_VIO>;
1015 resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>;
1016 reset-names = "core", "axi", "ahb";
1019 vopb: vop@ff930000 {
1020 compatible = "rockchip,rk3288-vop";
1021 reg = <0x0 0xff930000 0x0 0x19c>, <0x0 0xff931000 0x0 0x1000>;
1022 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1023 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1024 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1025 power-domains = <&power RK3288_PD_VIO>;
1026 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1027 reset-names = "axi", "ahb", "dclk";
1028 iommus = <&vopb_mmu>;
1029 status = "disabled";
1032 #address-cells = <1>;
1035 vopb_out_hdmi: endpoint@0 {
1037 remote-endpoint = <&hdmi_in_vopb>;
1040 vopb_out_edp: endpoint@1 {
1042 remote-endpoint = <&edp_in_vopb>;
1045 vopb_out_mipi: endpoint@2 {
1047 remote-endpoint = <&mipi_in_vopb>;
1050 vopb_out_lvds: endpoint@3 {
1052 remote-endpoint = <&lvds_in_vopb>;
1057 vopb_mmu: iommu@ff930300 {
1058 compatible = "rockchip,iommu";
1059 reg = <0x0 0xff930300 0x0 0x100>;
1060 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1061 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1062 clock-names = "aclk", "iface";
1063 power-domains = <&power RK3288_PD_VIO>;
1065 status = "disabled";
1068 vopl: vop@ff940000 {
1069 compatible = "rockchip,rk3288-vop";
1070 reg = <0x0 0xff940000 0x0 0x19c>, <0x0 0xff941000 0x0 0x1000>;
1071 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1072 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1073 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1074 power-domains = <&power RK3288_PD_VIO>;
1075 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
1076 reset-names = "axi", "ahb", "dclk";
1077 iommus = <&vopl_mmu>;
1078 status = "disabled";
1081 #address-cells = <1>;
1084 vopl_out_hdmi: endpoint@0 {
1086 remote-endpoint = <&hdmi_in_vopl>;
1089 vopl_out_edp: endpoint@1 {
1091 remote-endpoint = <&edp_in_vopl>;
1094 vopl_out_mipi: endpoint@2 {
1096 remote-endpoint = <&mipi_in_vopl>;
1099 vopl_out_lvds: endpoint@3 {
1101 remote-endpoint = <&lvds_in_vopl>;
1106 vopl_mmu: iommu@ff940300 {
1107 compatible = "rockchip,iommu";
1108 reg = <0x0 0xff940300 0x0 0x100>;
1109 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1110 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1111 clock-names = "aclk", "iface";
1112 power-domains = <&power RK3288_PD_VIO>;
1114 status = "disabled";
1117 mipi_dsi: mipi@ff960000 {
1118 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
1119 reg = <0x0 0xff960000 0x0 0x4000>;
1120 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1121 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
1122 clock-names = "ref", "pclk";
1123 power-domains = <&power RK3288_PD_VIO>;
1124 rockchip,grf = <&grf>;
1125 status = "disabled";
1129 #address-cells = <1>;
1131 mipi_in_vopb: endpoint@0 {
1133 remote-endpoint = <&vopb_out_mipi>;
1135 mipi_in_vopl: endpoint@1 {
1137 remote-endpoint = <&vopl_out_mipi>;
1143 lvds: lvds@ff96c000 {
1144 compatible = "rockchip,rk3288-lvds";
1145 reg = <0x0 0xff96c000 0x0 0x4000>;
1146 clocks = <&cru PCLK_LVDS_PHY>;
1147 clock-names = "pclk_lvds";
1148 pinctrl-names = "lcdc";
1149 pinctrl-0 = <&lcdc_ctl>;
1150 power-domains = <&power RK3288_PD_VIO>;
1151 rockchip,grf = <&grf>;
1152 status = "disabled";
1155 #address-cells = <1>;
1161 #address-cells = <1>;
1164 lvds_in_vopb: endpoint@0 {
1166 remote-endpoint = <&vopb_out_lvds>;
1168 lvds_in_vopl: endpoint@1 {
1170 remote-endpoint = <&vopl_out_lvds>;
1177 compatible = "rockchip,rk3288-dp";
1178 reg = <0x0 0xff970000 0x0 0x4000>;
1179 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1180 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1181 clock-names = "dp", "pclk";
1184 resets = <&cru SRST_EDP>;
1186 rockchip,grf = <&grf>;
1187 status = "disabled";
1190 #address-cells = <1>;
1194 #address-cells = <1>;
1196 edp_in_vopb: endpoint@0 {
1198 remote-endpoint = <&vopb_out_edp>;
1200 edp_in_vopl: endpoint@1 {
1202 remote-endpoint = <&vopl_out_edp>;
1208 hdmi: hdmi@ff980000 {
1209 compatible = "rockchip,rk3288-dw-hdmi";
1210 reg = <0x0 0xff980000 0x0 0x20000>;
1212 #sound-dai-cells = <0>;
1213 rockchip,grf = <&grf>;
1214 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1215 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>;
1216 clock-names = "iahb", "isfr", "cec";
1217 power-domains = <&power RK3288_PD_VIO>;
1218 status = "disabled";
1222 #address-cells = <1>;
1224 hdmi_in_vopb: endpoint@0 {
1226 remote-endpoint = <&vopb_out_hdmi>;
1228 hdmi_in_vopl: endpoint@1 {
1230 remote-endpoint = <&vopl_out_hdmi>;
1236 vpu: video-codec@ff9a0000 {
1237 compatible = "rockchip,rk3288-vpu";
1238 reg = <0x0 0xff9a0000 0x0 0x800>;
1239 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1240 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1241 interrupt-names = "vepu", "vdpu";
1242 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1243 clock-names = "aclk", "hclk";
1244 iommus = <&vpu_mmu>;
1245 power-domains = <&power RK3288_PD_VIDEO>;
1248 vpu_mmu: iommu@ff9a0800 {
1249 compatible = "rockchip,iommu";
1250 reg = <0x0 0xff9a0800 0x0 0x100>;
1251 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1252 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1253 clock-names = "aclk", "iface";
1255 power-domains = <&power RK3288_PD_VIDEO>;
1258 hevc_mmu: iommu@ff9c0440 {
1259 compatible = "rockchip,iommu";
1260 reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>;
1261 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1262 clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>;
1263 clock-names = "aclk", "iface";
1265 status = "disabled";
1269 compatible = "rockchip,rk3288-mali", "arm,mali-t760";
1270 reg = <0x0 0xffa30000 0x0 0x10000>;
1271 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1272 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1273 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1274 interrupt-names = "job", "mmu", "gpu";
1275 clocks = <&cru ACLK_GPU>;
1276 operating-points-v2 = <&gpu_opp_table>;
1277 #cooling-cells = <2>; /* min followed by max */
1278 power-domains = <&power RK3288_PD_GPU>;
1279 status = "disabled";
1282 gpu_opp_table: opp-table-1 {
1283 compatible = "operating-points-v2";
1286 opp-hz = /bits/ 64 <100000000>;
1287 opp-microvolt = <950000>;
1290 opp-hz = /bits/ 64 <200000000>;
1291 opp-microvolt = <950000>;
1294 opp-hz = /bits/ 64 <300000000>;
1295 opp-microvolt = <1000000>;
1298 opp-hz = /bits/ 64 <400000000>;
1299 opp-microvolt = <1100000>;
1302 opp-hz = /bits/ 64 <600000000>;
1303 opp-microvolt = <1250000>;
1307 qos_gpu_r: qos@ffaa0000 {
1308 compatible = "rockchip,rk3288-qos", "syscon";
1309 reg = <0x0 0xffaa0000 0x0 0x20>;
1312 qos_gpu_w: qos@ffaa0080 {
1313 compatible = "rockchip,rk3288-qos", "syscon";
1314 reg = <0x0 0xffaa0080 0x0 0x20>;
1317 qos_vio1_vop: qos@ffad0000 {
1318 compatible = "rockchip,rk3288-qos", "syscon";
1319 reg = <0x0 0xffad0000 0x0 0x20>;
1322 qos_vio1_isp_w0: qos@ffad0100 {
1323 compatible = "rockchip,rk3288-qos", "syscon";
1324 reg = <0x0 0xffad0100 0x0 0x20>;
1327 qos_vio1_isp_w1: qos@ffad0180 {
1328 compatible = "rockchip,rk3288-qos", "syscon";
1329 reg = <0x0 0xffad0180 0x0 0x20>;
1332 qos_vio0_vop: qos@ffad0400 {
1333 compatible = "rockchip,rk3288-qos", "syscon";
1334 reg = <0x0 0xffad0400 0x0 0x20>;
1337 qos_vio0_vip: qos@ffad0480 {
1338 compatible = "rockchip,rk3288-qos", "syscon";
1339 reg = <0x0 0xffad0480 0x0 0x20>;
1342 qos_vio0_iep: qos@ffad0500 {
1343 compatible = "rockchip,rk3288-qos", "syscon";
1344 reg = <0x0 0xffad0500 0x0 0x20>;
1347 qos_vio2_rga_r: qos@ffad0800 {
1348 compatible = "rockchip,rk3288-qos", "syscon";
1349 reg = <0x0 0xffad0800 0x0 0x20>;
1352 qos_vio2_rga_w: qos@ffad0880 {
1353 compatible = "rockchip,rk3288-qos", "syscon";
1354 reg = <0x0 0xffad0880 0x0 0x20>;
1357 qos_vio1_isp_r: qos@ffad0900 {
1358 compatible = "rockchip,rk3288-qos", "syscon";
1359 reg = <0x0 0xffad0900 0x0 0x20>;
1362 qos_video: qos@ffae0000 {
1363 compatible = "rockchip,rk3288-qos", "syscon";
1364 reg = <0x0 0xffae0000 0x0 0x20>;
1367 qos_hevc_r: qos@ffaf0000 {
1368 compatible = "rockchip,rk3288-qos", "syscon";
1369 reg = <0x0 0xffaf0000 0x0 0x20>;
1372 qos_hevc_w: qos@ffaf0080 {
1373 compatible = "rockchip,rk3288-qos", "syscon";
1374 reg = <0x0 0xffaf0080 0x0 0x20>;
1377 dmac_bus_s: dma-controller@ffb20000 {
1378 compatible = "arm,pl330", "arm,primecell";
1379 reg = <0x0 0xffb20000 0x0 0x4000>;
1380 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
1381 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1383 arm,pl330-broken-no-flushp;
1384 arm,pl330-periph-burst;
1385 clocks = <&cru ACLK_DMAC1>;
1386 clock-names = "apb_pclk";
1389 efuse: efuse@ffb40000 {
1390 compatible = "rockchip,rk3288-efuse";
1391 reg = <0x0 0xffb40000 0x0 0x20>;
1392 #address-cells = <1>;
1394 clocks = <&cru PCLK_EFUSE256>;
1395 clock-names = "pclk_efuse";
1400 cpu_leakage: cpu_leakage@17 {
1405 gic: interrupt-controller@ffc01000 {
1406 compatible = "arm,gic-400";
1407 interrupt-controller;
1408 #interrupt-cells = <3>;
1409 #address-cells = <0>;
1411 reg = <0x0 0xffc01000 0x0 0x1000>,
1412 <0x0 0xffc02000 0x0 0x2000>,
1413 <0x0 0xffc04000 0x0 0x2000>,
1414 <0x0 0xffc06000 0x0 0x2000>;
1415 interrupts = <GIC_PPI 9 0xf04>;
1419 compatible = "rockchip,rk3288-pinctrl";
1420 rockchip,grf = <&grf>;
1421 rockchip,pmu = <&pmu>;
1422 #address-cells = <2>;
1426 gpio0: gpio@ff750000 {
1427 compatible = "rockchip,gpio-bank";
1428 reg = <0x0 0xff750000 0x0 0x100>;
1429 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1430 clocks = <&cru PCLK_GPIO0>;
1435 interrupt-controller;
1436 #interrupt-cells = <2>;
1439 gpio1: gpio@ff780000 {
1440 compatible = "rockchip,gpio-bank";
1441 reg = <0x0 0xff780000 0x0 0x100>;
1442 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1443 clocks = <&cru PCLK_GPIO1>;
1448 interrupt-controller;
1449 #interrupt-cells = <2>;
1452 gpio2: gpio@ff790000 {
1453 compatible = "rockchip,gpio-bank";
1454 reg = <0x0 0xff790000 0x0 0x100>;
1455 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1456 clocks = <&cru PCLK_GPIO2>;
1461 interrupt-controller;
1462 #interrupt-cells = <2>;
1465 gpio3: gpio@ff7a0000 {
1466 compatible = "rockchip,gpio-bank";
1467 reg = <0x0 0xff7a0000 0x0 0x100>;
1468 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1469 clocks = <&cru PCLK_GPIO3>;
1474 interrupt-controller;
1475 #interrupt-cells = <2>;
1478 gpio4: gpio@ff7b0000 {
1479 compatible = "rockchip,gpio-bank";
1480 reg = <0x0 0xff7b0000 0x0 0x100>;
1481 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1482 clocks = <&cru PCLK_GPIO4>;
1487 interrupt-controller;
1488 #interrupt-cells = <2>;
1491 gpio5: gpio@ff7c0000 {
1492 compatible = "rockchip,gpio-bank";
1493 reg = <0x0 0xff7c0000 0x0 0x100>;
1494 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1495 clocks = <&cru PCLK_GPIO5>;
1500 interrupt-controller;
1501 #interrupt-cells = <2>;
1504 gpio6: gpio@ff7d0000 {
1505 compatible = "rockchip,gpio-bank";
1506 reg = <0x0 0xff7d0000 0x0 0x100>;
1507 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1508 clocks = <&cru PCLK_GPIO6>;
1513 interrupt-controller;
1514 #interrupt-cells = <2>;
1517 gpio7: gpio@ff7e0000 {
1518 compatible = "rockchip,gpio-bank";
1519 reg = <0x0 0xff7e0000 0x0 0x100>;
1520 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1521 clocks = <&cru PCLK_GPIO7>;
1526 interrupt-controller;
1527 #interrupt-cells = <2>;
1530 gpio8: gpio@ff7f0000 {
1531 compatible = "rockchip,gpio-bank";
1532 reg = <0x0 0xff7f0000 0x0 0x100>;
1533 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1534 clocks = <&cru PCLK_GPIO8>;
1539 interrupt-controller;
1540 #interrupt-cells = <2>;
1544 hdmi_cec_c0: hdmi-cec-c0 {
1545 rockchip,pins = <7 RK_PC0 2 &pcfg_pull_none>;
1548 hdmi_cec_c7: hdmi-cec-c7 {
1549 rockchip,pins = <7 RK_PC7 4 &pcfg_pull_none>;
1552 hdmi_ddc: hdmi-ddc {
1553 rockchip,pins = <7 RK_PC3 2 &pcfg_pull_none>,
1554 <7 RK_PC4 2 &pcfg_pull_none>;
1557 hdmi_ddc_unwedge: hdmi-ddc-unwedge {
1558 rockchip,pins = <7 RK_PC3 RK_FUNC_GPIO &pcfg_output_low>,
1559 <7 RK_PC4 2 &pcfg_pull_none>;
1563 pcfg_output_low: pcfg-output-low {
1567 pcfg_pull_up: pcfg-pull-up {
1571 pcfg_pull_down: pcfg-pull-down {
1575 pcfg_pull_none: pcfg-pull-none {
1579 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1581 drive-strength = <12>;
1585 global_pwroff: global-pwroff {
1586 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>;
1589 ddrio_pwroff: ddrio-pwroff {
1590 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>;
1593 ddr0_retention: ddr0-retention {
1594 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_up>;
1597 ddr1_retention: ddr1-retention {
1598 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_up>;
1604 rockchip,pins = <7 RK_PB3 2 &pcfg_pull_down>;
1609 i2c0_xfer: i2c0-xfer {
1610 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>,
1611 <0 RK_PC0 1 &pcfg_pull_none>;
1616 i2c1_xfer: i2c1-xfer {
1617 rockchip,pins = <8 RK_PA4 1 &pcfg_pull_none>,
1618 <8 RK_PA5 1 &pcfg_pull_none>;
1623 i2c2_xfer: i2c2-xfer {
1624 rockchip,pins = <6 RK_PB1 1 &pcfg_pull_none>,
1625 <6 RK_PB2 1 &pcfg_pull_none>;
1630 i2c3_xfer: i2c3-xfer {
1631 rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>,
1632 <2 RK_PC1 1 &pcfg_pull_none>;
1637 i2c4_xfer: i2c4-xfer {
1638 rockchip,pins = <7 RK_PC1 1 &pcfg_pull_none>,
1639 <7 RK_PC2 1 &pcfg_pull_none>;
1644 i2c5_xfer: i2c5-xfer {
1645 rockchip,pins = <7 RK_PC3 1 &pcfg_pull_none>,
1646 <7 RK_PC4 1 &pcfg_pull_none>;
1651 i2s0_bus: i2s0-bus {
1652 rockchip,pins = <6 RK_PA0 1 &pcfg_pull_none>,
1653 <6 RK_PA1 1 &pcfg_pull_none>,
1654 <6 RK_PA2 1 &pcfg_pull_none>,
1655 <6 RK_PA3 1 &pcfg_pull_none>,
1656 <6 RK_PA4 1 &pcfg_pull_none>,
1657 <6 RK_PB0 1 &pcfg_pull_none>;
1662 lcdc_ctl: lcdc-ctl {
1663 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>,
1664 <1 RK_PD1 1 &pcfg_pull_none>,
1665 <1 RK_PD2 1 &pcfg_pull_none>,
1666 <1 RK_PD3 1 &pcfg_pull_none>;
1671 sdmmc_clk: sdmmc-clk {
1672 rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none>;
1675 sdmmc_cmd: sdmmc-cmd {
1676 rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up>;
1679 sdmmc_cd: sdmmc-cd {
1680 rockchip,pins = <6 RK_PC6 1 &pcfg_pull_up>;
1683 sdmmc_bus1: sdmmc-bus1 {
1684 rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up>;
1687 sdmmc_bus4: sdmmc-bus4 {
1688 rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up>,
1689 <6 RK_PC1 1 &pcfg_pull_up>,
1690 <6 RK_PC2 1 &pcfg_pull_up>,
1691 <6 RK_PC3 1 &pcfg_pull_up>;
1696 sdio0_bus1: sdio0-bus1 {
1697 rockchip,pins = <4 RK_PC4 1 &pcfg_pull_up>;
1700 sdio0_bus4: sdio0-bus4 {
1701 rockchip,pins = <4 RK_PC4 1 &pcfg_pull_up>,
1702 <4 RK_PC5 1 &pcfg_pull_up>,
1703 <4 RK_PC6 1 &pcfg_pull_up>,
1704 <4 RK_PC7 1 &pcfg_pull_up>;
1707 sdio0_cmd: sdio0-cmd {
1708 rockchip,pins = <4 RK_PD0 1 &pcfg_pull_up>;
1711 sdio0_clk: sdio0-clk {
1712 rockchip,pins = <4 RK_PD1 1 &pcfg_pull_none>;
1715 sdio0_cd: sdio0-cd {
1716 rockchip,pins = <4 RK_PD2 1 &pcfg_pull_up>;
1719 sdio0_wp: sdio0-wp {
1720 rockchip,pins = <4 RK_PD3 1 &pcfg_pull_up>;
1723 sdio0_pwr: sdio0-pwr {
1724 rockchip,pins = <4 RK_PD4 1 &pcfg_pull_up>;
1727 sdio0_bkpwr: sdio0-bkpwr {
1728 rockchip,pins = <4 RK_PD5 1 &pcfg_pull_up>;
1731 sdio0_int: sdio0-int {
1732 rockchip,pins = <4 RK_PD6 1 &pcfg_pull_up>;
1737 sdio1_bus1: sdio1-bus1 {
1738 rockchip,pins = <3 RK_PD0 4 &pcfg_pull_up>;
1741 sdio1_bus4: sdio1-bus4 {
1742 rockchip,pins = <3 RK_PD0 4 &pcfg_pull_up>,
1743 <3 RK_PD1 4 &pcfg_pull_up>,
1744 <3 RK_PD2 4 &pcfg_pull_up>,
1745 <3 RK_PD3 4 &pcfg_pull_up>;
1748 sdio1_cd: sdio1-cd {
1749 rockchip,pins = <3 RK_PD4 4 &pcfg_pull_up>;
1752 sdio1_wp: sdio1-wp {
1753 rockchip,pins = <3 RK_PD5 4 &pcfg_pull_up>;
1756 sdio1_bkpwr: sdio1-bkpwr {
1757 rockchip,pins = <3 RK_PD6 4 &pcfg_pull_up>;
1760 sdio1_int: sdio1-int {
1761 rockchip,pins = <3 RK_PD7 4 &pcfg_pull_up>;
1764 sdio1_cmd: sdio1-cmd {
1765 rockchip,pins = <4 RK_PA6 4 &pcfg_pull_up>;
1768 sdio1_clk: sdio1-clk {
1769 rockchip,pins = <4 RK_PA7 4 &pcfg_pull_none>;
1772 sdio1_pwr: sdio1-pwr {
1773 rockchip,pins = <4 RK_PB1 4 &pcfg_pull_up>;
1778 emmc_clk: emmc-clk {
1779 rockchip,pins = <3 RK_PC2 2 &pcfg_pull_none>;
1782 emmc_cmd: emmc-cmd {
1783 rockchip,pins = <3 RK_PC0 2 &pcfg_pull_up>;
1786 emmc_pwr: emmc-pwr {
1787 rockchip,pins = <3 RK_PB1 2 &pcfg_pull_up>;
1790 emmc_bus1: emmc-bus1 {
1791 rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>;
1794 emmc_bus4: emmc-bus4 {
1795 rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>,
1796 <3 RK_PA1 2 &pcfg_pull_up>,
1797 <3 RK_PA2 2 &pcfg_pull_up>,
1798 <3 RK_PA3 2 &pcfg_pull_up>;
1801 emmc_bus8: emmc-bus8 {
1802 rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>,
1803 <3 RK_PA1 2 &pcfg_pull_up>,
1804 <3 RK_PA2 2 &pcfg_pull_up>,
1805 <3 RK_PA3 2 &pcfg_pull_up>,
1806 <3 RK_PA4 2 &pcfg_pull_up>,
1807 <3 RK_PA5 2 &pcfg_pull_up>,
1808 <3 RK_PA6 2 &pcfg_pull_up>,
1809 <3 RK_PA7 2 &pcfg_pull_up>;
1814 spi0_clk: spi0-clk {
1815 rockchip,pins = <5 RK_PB4 1 &pcfg_pull_up>;
1817 spi0_cs0: spi0-cs0 {
1818 rockchip,pins = <5 RK_PB5 1 &pcfg_pull_up>;
1821 rockchip,pins = <5 RK_PB6 1 &pcfg_pull_up>;
1824 rockchip,pins = <5 RK_PB7 1 &pcfg_pull_up>;
1826 spi0_cs1: spi0-cs1 {
1827 rockchip,pins = <5 RK_PC0 1 &pcfg_pull_up>;
1831 spi1_clk: spi1-clk {
1832 rockchip,pins = <7 RK_PB4 2 &pcfg_pull_up>;
1834 spi1_cs0: spi1-cs0 {
1835 rockchip,pins = <7 RK_PB5 2 &pcfg_pull_up>;
1838 rockchip,pins = <7 RK_PB6 2 &pcfg_pull_up>;
1841 rockchip,pins = <7 RK_PB7 2 &pcfg_pull_up>;
1846 spi2_cs1: spi2-cs1 {
1847 rockchip,pins = <8 RK_PA3 1 &pcfg_pull_up>;
1849 spi2_clk: spi2-clk {
1850 rockchip,pins = <8 RK_PA6 1 &pcfg_pull_up>;
1852 spi2_cs0: spi2-cs0 {
1853 rockchip,pins = <8 RK_PA7 1 &pcfg_pull_up>;
1856 rockchip,pins = <8 RK_PB0 1 &pcfg_pull_up>;
1859 rockchip,pins = <8 RK_PB1 1 &pcfg_pull_up>;
1864 uart0_xfer: uart0-xfer {
1865 rockchip,pins = <4 RK_PC0 1 &pcfg_pull_up>,
1866 <4 RK_PC1 1 &pcfg_pull_none>;
1869 uart0_cts: uart0-cts {
1870 rockchip,pins = <4 RK_PC2 1 &pcfg_pull_up>;
1873 uart0_rts: uart0-rts {
1874 rockchip,pins = <4 RK_PC3 1 &pcfg_pull_none>;
1879 uart1_xfer: uart1-xfer {
1880 rockchip,pins = <5 RK_PB0 1 &pcfg_pull_up>,
1881 <5 RK_PB1 1 &pcfg_pull_none>;
1884 uart1_cts: uart1-cts {
1885 rockchip,pins = <5 RK_PB2 1 &pcfg_pull_up>;
1888 uart1_rts: uart1-rts {
1889 rockchip,pins = <5 RK_PB3 1 &pcfg_pull_none>;
1894 uart2_xfer: uart2-xfer {
1895 rockchip,pins = <7 RK_PC6 1 &pcfg_pull_up>,
1896 <7 RK_PC7 1 &pcfg_pull_none>;
1898 /* no rts / cts for uart2 */
1902 uart3_xfer: uart3-xfer {
1903 rockchip,pins = <7 RK_PA7 1 &pcfg_pull_up>,
1904 <7 RK_PB0 1 &pcfg_pull_none>;
1907 uart3_cts: uart3-cts {
1908 rockchip,pins = <7 RK_PB1 1 &pcfg_pull_up>;
1911 uart3_rts: uart3-rts {
1912 rockchip,pins = <7 RK_PB2 1 &pcfg_pull_none>;
1917 uart4_xfer: uart4-xfer {
1918 rockchip,pins = <5 RK_PB7 3 &pcfg_pull_up>,
1919 <5 RK_PB6 3 &pcfg_pull_none>;
1922 uart4_cts: uart4-cts {
1923 rockchip,pins = <5 RK_PB4 3 &pcfg_pull_up>;
1926 uart4_rts: uart4-rts {
1927 rockchip,pins = <5 RK_PB5 3 &pcfg_pull_none>;
1933 rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
1937 rockchip,pins = <0 RK_PB2 1 &pcfg_pull_none>;
1942 pwm0_pin: pwm0-pin {
1943 rockchip,pins = <7 RK_PA0 1 &pcfg_pull_none>;
1948 pwm1_pin: pwm1-pin {
1949 rockchip,pins = <7 RK_PA1 1 &pcfg_pull_none>;
1954 pwm2_pin: pwm2-pin {
1955 rockchip,pins = <7 RK_PC6 3 &pcfg_pull_none>;
1960 pwm3_pin: pwm3-pin {
1961 rockchip,pins = <7 RK_PC7 3 &pcfg_pull_none>;
1966 rgmii_pins: rgmii-pins {
1967 rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>,
1968 <3 RK_PD7 3 &pcfg_pull_none>,
1969 <3 RK_PD2 3 &pcfg_pull_none>,
1970 <3 RK_PD3 3 &pcfg_pull_none>,
1971 <3 RK_PD4 3 &pcfg_pull_none_12ma>,
1972 <3 RK_PD5 3 &pcfg_pull_none_12ma>,
1973 <3 RK_PD0 3 &pcfg_pull_none_12ma>,
1974 <3 RK_PD1 3 &pcfg_pull_none_12ma>,
1975 <4 RK_PA0 3 &pcfg_pull_none>,
1976 <4 RK_PA5 3 &pcfg_pull_none>,
1977 <4 RK_PA6 3 &pcfg_pull_none>,
1978 <4 RK_PB1 3 &pcfg_pull_none_12ma>,
1979 <4 RK_PA4 3 &pcfg_pull_none_12ma>,
1980 <4 RK_PA1 3 &pcfg_pull_none>,
1981 <4 RK_PA3 3 &pcfg_pull_none>;
1984 rmii_pins: rmii-pins {
1985 rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>,
1986 <3 RK_PD7 3 &pcfg_pull_none>,
1987 <3 RK_PD4 3 &pcfg_pull_none>,
1988 <3 RK_PD5 3 &pcfg_pull_none>,
1989 <4 RK_PA0 3 &pcfg_pull_none>,
1990 <4 RK_PA5 3 &pcfg_pull_none>,
1991 <4 RK_PA4 3 &pcfg_pull_none>,
1992 <4 RK_PA1 3 &pcfg_pull_none>,
1993 <4 RK_PA2 3 &pcfg_pull_none>,
1994 <4 RK_PA3 3 &pcfg_pull_none>;
1999 spdif_tx: spdif-tx {
2000 rockchip,pins = <6 RK_PB3 1 &pcfg_pull_none>;