arch/arm/boot/dts/rk3288.dtsi

   1 /*
   2  * This file is dual-licensed: you can use it either under the terms
   3  * of the GPL or the X11 license, at your option. Note that this dual
   4  * licensing only applies to this file, and not this project as a
   5  * whole.
   6  *
   7  *  a) This file is free software; you can redistribute it and/or
   8  *     modify it under the terms of the GNU General Public License as
   9  *     published by the Free Software Foundation; either version 2 of the
  10  *     License, or (at your option) any later version.
  11  *
  12  *     This file is distributed in the hope that it will be useful,
  13  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *     GNU General Public License for more details.
  16  *
  17  * Or, alternatively,
  18  *
  19  *  b) Permission is hereby granted, free of charge, to any person
  20  *     obtaining a copy of this software and associated documentation
  21  *     files (the "Software"), to deal in the Software without
  22  *     restriction, including without limitation the rights to use,
  23  *     copy, modify, merge, publish, distribute, sublicense, and/or
  24  *     sell copies of the Software, and to permit persons to whom the
  25  *     Software is furnished to do so, subject to the following
  26  *     conditions:
  27  *
  28  *     The above copyright notice and this permission notice shall be
  29  *     included in all copies or substantial portions of the Software.
  30  *
  31  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  32  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  33  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  34  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  35  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  36  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  37  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  38  *     OTHER DEALINGS IN THE SOFTWARE.
  39  */
  40
  41 #include <dt-bindings/gpio/gpio.h>
  42 #include <dt-bindings/interrupt-controller/irq.h>
  43 #include <dt-bindings/interrupt-controller/arm-gic.h>
  44 #include <dt-bindings/pinctrl/rockchip.h>
  45 #include <dt-bindings/clock/rk3288-cru.h>
  46 #include <dt-bindings/thermal/thermal.h>
  47 #include <dt-bindings/power/rk3288-power.h>
  48 #include <dt-bindings/soc/rockchip,boot-mode.h>
  49 #include "skeleton.dtsi"
  50
  51 / {
  52         compatible = "rockchip,rk3288";
  53
  54         interrupt-parent = <&gic>;
  55
  56         aliases {
  57                 ethernet0 = &gmac;
  58                 i2c0 = &i2c0;
  59                 i2c1 = &i2c1;
  60                 i2c2 = &i2c2;
  61                 i2c3 = &i2c3;
  62                 i2c4 = &i2c4;
  63                 i2c5 = &i2c5;
  64                 mshc0 = &emmc;
  65                 mshc1 = &sdmmc;
  66                 mshc2 = &sdio0;
  67                 mshc3 = &sdio1;
  68                 serial0 = &uart0;
  69                 serial1 = &uart1;
  70                 serial2 = &uart2;
  71                 serial3 = &uart3;
  72                 serial4 = &uart4;
  73                 spi0 = &spi0;
  74                 spi1 = &spi1;
  75                 spi2 = &spi2;
  76         };
  77
  78         arm-pmu {
  79                 compatible = "arm,cortex-a12-pmu";
  80                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
  81                              <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
  82                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
  83                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
  84                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  85         };
  86
  87         cpus {
  88                 #address-cells = <1>;
  89                 #size-cells = <0>;
  90                 enable-method = "rockchip,rk3066-smp";
  91                 rockchip,pmu = <&pmu>;
  92
  93                 cpu0: cpu@500 {
  94                         device_type = "cpu";
  95                         compatible = "arm,cortex-a12";
  96                         reg = <0x500>;
  97                         resets = <&cru SRST_CORE0>;
  98                         operating-points = <
  99                                 /* KHz    uV */
 100                                 1608000 1350000
 101                                 1512000 1300000
 102                                 1416000 1200000
 103                                 1200000 1100000
 104                                 1008000 1050000
 105                                  816000 1000000
 106                                  696000  950000
 107                                  600000  900000
 108                                  408000  900000
 109                                  312000  900000
 110                                  216000  900000
 111                                  126000  900000
 112                         >;
 113                         #cooling-cells = <2>; /* min followed by max */
 114                         clock-latency = <40000>;
 115                         clocks = <&cru ARMCLK>;
 116                 };
 117                 cpu1: cpu@501 {
 118                         device_type = "cpu";
 119                         compatible = "arm,cortex-a12";
 120                         reg = <0x501>;
 121                         resets = <&cru SRST_CORE1>;
 122                 };
 123                 cpu2: cpu@502 {
 124                         device_type = "cpu";
 125                         compatible = "arm,cortex-a12";
 126                         reg = <0x502>;
 127                         resets = <&cru SRST_CORE2>;
 128                 };
 129                 cpu3: cpu@503 {
 130                         device_type = "cpu";
 131                         compatible = "arm,cortex-a12";
 132                         reg = <0x503>;
 133                         resets = <&cru SRST_CORE3>;
 134                 };
 135         };
 136
 137         amba {
 138                 compatible = "simple-bus";
 139                 #address-cells = <1>;
 140                 #size-cells = <1>;
 141                 ranges;
 142
 143                 dmac_peri: dma-controller@ff250000 {
 144                         compatible = "arm,pl330", "arm,primecell";
 145                         reg = <0xff250000 0x4000>;
 146                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 147                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 148                         #dma-cells = <1>;
 149                         arm,pl330-broken-no-flushp;
 150                         clocks = <&cru ACLK_DMAC2>;
 151                         clock-names = "apb_pclk";
 152                 };
 153
 154                 dmac_bus_ns: dma-controller@ff600000 {
 155                         compatible = "arm,pl330", "arm,primecell";
 156                         reg = <0xff600000 0x4000>;
 157                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 158                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 159                         #dma-cells = <1>;
 160                         arm,pl330-broken-no-flushp;
 161                         clocks = <&cru ACLK_DMAC1>;
 162                         clock-names = "apb_pclk";
 163                         status = "disabled";
 164                 };
 165
 166                 dmac_bus_s: dma-controller@ffb20000 {
 167                         compatible = "arm,pl330", "arm,primecell";
 168                         reg = <0xffb20000 0x4000>;
 169                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 170                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 171                         #dma-cells = <1>;
 172                         arm,pl330-broken-no-flushp;
 173                         clocks = <&cru ACLK_DMAC1>;
 174                         clock-names = "apb_pclk";
 175                 };
 176         };
 177
 178         reserved-memory {
 179                 #address-cells = <1>;
 180                 #size-cells = <1>;
 181                 ranges;
 182
 183                 /*
 184                  * The rk3288 cannot use the memory area above 0xfe000000
 185                  * for dma operations for some reason. While there is
 186                  * probably a better solution available somewhere, we
 187                  * haven't found it yet and while devices with 2GB of ram
 188                  * are not affected, this issue prevents 4GB from booting.
 189                  * So to make these devices at least bootable, block
 190                  * this area for the time being until the real solution
 191                  * is found.
 192                  */
 193                 dma-unusable@fe000000 {
 194                         reg = <0xfe000000 0x1000000>;
 195                 };
 196         };
 197
 198         xin24m: oscillator {
 199                 compatible = "fixed-clock";
 200                 clock-frequency = <24000000>;
 201                 clock-output-names = "xin24m";
 202                 #clock-cells = <0>;
 203         };
 204
 205         timer {
 206                 compatible = "arm,armv7-timer";
 207                 arm,cpu-registers-not-fw-configured;
 208                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 209                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 210                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 211                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 212                 clock-frequency = <24000000>;
 213                 arm,no-tick-in-suspend;
 214         };
 215
 216         timer: timer@ff810000 {
 217                 compatible = "rockchip,rk3288-timer";
 218                 reg = <0xff810000 0x20>;
 219                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 220                 clocks = <&xin24m>, <&cru PCLK_TIMER>;
 221                 clock-names = "timer", "pclk";
 222         };
 223
 224         display-subsystem {
 225                 compatible = "rockchip,display-subsystem";
 226                 ports = <&vopl_out>, <&vopb_out>;
 227         };
 228
 229         sdmmc: dwmmc@ff0c0000 {
 230                 compatible = "rockchip,rk3288-dw-mshc";
 231                 clock-freq-min-max = <400000 150000000>;
 232                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 233                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 234                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 235                 fifo-depth = <0x100>;
 236                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 237                 reg = <0xff0c0000 0x4000>;
 238                 status = "disabled";
 239         };
 240
 241         sdio0: dwmmc@ff0d0000 {
 242                 compatible = "rockchip,rk3288-dw-mshc";
 243                 clock-freq-min-max = <400000 150000000>;
 244                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 245                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 246                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 247                 fifo-depth = <0x100>;
 248                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 249                 reg = <0xff0d0000 0x4000>;
 250                 status = "disabled";
 251         };
 252
 253         sdio1: dwmmc@ff0e0000 {
 254                 compatible = "rockchip,rk3288-dw-mshc";
 255                 clock-freq-min-max = <400000 150000000>;
 256                 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
 257                          <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
 258                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 259                 fifo-depth = <0x100>;
 260                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 261                 reg = <0xff0e0000 0x4000>;
 262                 status = "disabled";
 263         };
 264
 265         emmc: dwmmc@ff0f0000 {
 266                 compatible = "rockchip,rk3288-dw-mshc";
 267                 clock-freq-min-max = <400000 150000000>;
 268                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 269                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 270                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 271                 fifo-depth = <0x100>;
 272                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 273                 reg = <0xff0f0000 0x4000>;
 274                 status = "disabled";
 275         };
 276
 277         saradc: saradc@ff100000 {
 278                 compatible = "rockchip,saradc";
 279                 reg = <0xff100000 0x100>;
 280                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 281                 #io-channel-cells = <1>;
 282                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 283                 clock-names = "saradc", "apb_pclk";
 284                 resets = <&cru SRST_SARADC>;
 285                 reset-names = "saradc-apb";
 286                 status = "disabled";
 287         };
 288
 289         spi0: spi@ff110000 {
 290                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 291                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 292                 clock-names = "spiclk", "apb_pclk";
 293                 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
 294                 dma-names = "tx", "rx";
 295                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 296                 pinctrl-names = "default";
 297                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 298                 reg = <0xff110000 0x1000>;
 299                 #address-cells = <1>;
 300                 #size-cells = <0>;
 301                 status = "disabled";
 302         };
 303
 304         spi1: spi@ff120000 {
 305                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 306                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 307                 clock-names = "spiclk", "apb_pclk";
 308                 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
 309                 dma-names = "tx", "rx";
 310                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 311                 pinctrl-names = "default";
 312                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 313                 reg = <0xff120000 0x1000>;
 314                 #address-cells = <1>;
 315                 #size-cells = <0>;
 316                 status = "disabled";
 317         };
 318
 319         spi2: spi@ff130000 {
 320                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 321                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 322                 clock-names = "spiclk", "apb_pclk";
 323                 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
 324                 dma-names = "tx", "rx";
 325                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 326                 pinctrl-names = "default";
 327                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 328                 reg = <0xff130000 0x1000>;
 329                 #address-cells = <1>;
 330                 #size-cells = <0>;
 331                 status = "disabled";
 332         };
 333
 334         i2c1: i2c@ff140000 {
 335                 compatible = "rockchip,rk3288-i2c";
 336                 reg = <0xff140000 0x1000>;
 337                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 338                 #address-cells = <1>;
 339                 #size-cells = <0>;
 340                 clock-names = "i2c";
 341                 clocks = <&cru PCLK_I2C1>;
 342                 pinctrl-names = "default";
 343                 pinctrl-0 = <&i2c1_xfer>;
 344                 status = "disabled";
 345         };
 346
 347         i2c3: i2c@ff150000 {
 348                 compatible = "rockchip,rk3288-i2c";
 349                 reg = <0xff150000 0x1000>;
 350                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 351                 #address-cells = <1>;
 352                 #size-cells = <0>;
 353                 clock-names = "i2c";
 354                 clocks = <&cru PCLK_I2C3>;
 355                 pinctrl-names = "default";
 356                 pinctrl-0 = <&i2c3_xfer>;
 357                 status = "disabled";
 358         };
 359
 360         i2c4: i2c@ff160000 {
 361                 compatible = "rockchip,rk3288-i2c";
 362                 reg = <0xff160000 0x1000>;
 363                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 364                 #address-cells = <1>;
 365                 #size-cells = <0>;
 366                 clock-names = "i2c";
 367                 clocks = <&cru PCLK_I2C4>;
 368                 pinctrl-names = "default";
 369                 pinctrl-0 = <&i2c4_xfer>;
 370                 status = "disabled";
 371         };
 372
 373         i2c5: i2c@ff170000 {
 374                 compatible = "rockchip,rk3288-i2c";
 375                 reg = <0xff170000 0x1000>;
 376                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 377                 #address-cells = <1>;
 378                 #size-cells = <0>;
 379                 clock-names = "i2c";
 380                 clocks = <&cru PCLK_I2C5>;
 381                 pinctrl-names = "default";
 382                 pinctrl-0 = <&i2c5_xfer>;
 383                 status = "disabled";
 384         };
 385
 386         uart0: serial@ff180000 {
 387                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 388                 reg = <0xff180000 0x100>;
 389                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 390                 reg-shift = <2>;
 391                 reg-io-width = <4>;
 392                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 393                 clock-names = "baudclk", "apb_pclk";
 394                 pinctrl-names = "default";
 395                 pinctrl-0 = <&uart0_xfer>;
 396                 status = "disabled";
 397         };
 398
 399         uart1: serial@ff190000 {
 400                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 401                 reg = <0xff190000 0x100>;
 402                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 403                 reg-shift = <2>;
 404                 reg-io-width = <4>;
 405                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 406                 clock-names = "baudclk", "apb_pclk";
 407                 pinctrl-names = "default";
 408                 pinctrl-0 = <&uart1_xfer>;
 409                 status = "disabled";
 410         };
 411
 412         uart2: serial@ff690000 {
 413                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 414                 reg = <0xff690000 0x100>;
 415                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 416                 reg-shift = <2>;
 417                 reg-io-width = <4>;
 418                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 419                 clock-names = "baudclk", "apb_pclk";
 420                 pinctrl-names = "default";
 421                 pinctrl-0 = <&uart2_xfer>;
 422                 status = "disabled";
 423         };
 424
 425         uart3: serial@ff1b0000 {
 426                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 427                 reg = <0xff1b0000 0x100>;
 428                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 429                 reg-shift = <2>;
 430                 reg-io-width = <4>;
 431                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 432                 clock-names = "baudclk", "apb_pclk";
 433                 pinctrl-names = "default";
 434                 pinctrl-0 = <&uart3_xfer>;
 435                 status = "disabled";
 436         };
 437
 438         uart4: serial@ff1c0000 {
 439                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 440                 reg = <0xff1c0000 0x100>;
 441                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 442                 reg-shift = <2>;
 443                 reg-io-width = <4>;
 444                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 445                 clock-names = "baudclk", "apb_pclk";
 446                 pinctrl-names = "default";
 447                 pinctrl-0 = <&uart4_xfer>;
 448                 status = "disabled";
 449         };
 450
 451         thermal-zones {
 452                 reserve_thermal: reserve_thermal {
 453                         polling-delay-passive = <1000>; /* milliseconds */
 454                         polling-delay = <5000>; /* milliseconds */
 455
 456                         thermal-sensors = <&tsadc 0>;
 457                 };
 458
 459                 cpu_thermal: cpu_thermal {
 460                         polling-delay-passive = <100>; /* milliseconds */
 461                         polling-delay = <5000>; /* milliseconds */
 462
 463                         thermal-sensors = <&tsadc 1>;
 464
 465                         trips {
 466                                 cpu_alert0: cpu_alert0 {
 467                                         temperature = <70000>; /* millicelsius */
 468                                         hysteresis = <2000>; /* millicelsius */
 469                                         type = "passive";
 470                                 };
 471                                 cpu_alert1: cpu_alert1 {
 472                                         temperature = <75000>; /* millicelsius */
 473                                         hysteresis = <2000>; /* millicelsius */
 474                                         type = "passive";
 475                                 };
 476                                 cpu_crit: cpu_crit {
 477                                         temperature = <90000>; /* millicelsius */
 478                                         hysteresis = <2000>; /* millicelsius */
 479                                         type = "critical";
 480                                 };
 481                         };
 482
 483                         cooling-maps {
 484                                 map0 {
 485                                         trip = <&cpu_alert0>;
 486                                         cooling-device =
 487                                                 <&cpu0 THERMAL_NO_LIMIT 6>;
 488                                 };
 489                                 map1 {
 490                                         trip = <&cpu_alert1>;
 491                                         cooling-device =
 492                                                 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 493                                 };
 494                         };
 495                 };
 496
 497                 gpu_thermal: gpu_thermal {
 498                         polling-delay-passive = <100>; /* milliseconds */
 499                         polling-delay = <5000>; /* milliseconds */
 500
 501                         thermal-sensors = <&tsadc 2>;
 502
 503                         trips {
 504                                 gpu_alert0: gpu_alert0 {
 505                                         temperature = <70000>; /* millicelsius */
 506                                         hysteresis = <2000>; /* millicelsius */
 507                                         type = "passive";
 508                                 };
 509                                 gpu_crit: gpu_crit {
 510                                         temperature = <90000>; /* millicelsius */
 511                                         hysteresis = <2000>; /* millicelsius */
 512                                         type = "critical";
 513                                 };
 514                         };
 515
 516                         cooling-maps {
 517                                 map0 {
 518                                         trip = <&gpu_alert0>;
 519                                         cooling-device =
 520                                                 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 521                                 };
 522                         };
 523                 };
 524         };
 525
 526         tsadc: tsadc@ff280000 {
 527                 compatible = "rockchip,rk3288-tsadc";
 528                 reg = <0xff280000 0x100>;
 529                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 530                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 531                 clock-names = "tsadc", "apb_pclk";
 532                 resets = <&cru SRST_TSADC>;
 533                 reset-names = "tsadc-apb";
 534                 pinctrl-names = "init", "default", "sleep";
 535                 pinctrl-0 = <&otp_gpio>;
 536                 pinctrl-1 = <&otp_out>;
 537                 pinctrl-2 = <&otp_gpio>;
 538                 #thermal-sensor-cells = <1>;
 539                 rockchip,hw-tshut-temp = <95000>;
 540                 status = "disabled";
 541         };
 542
 543         gmac: ethernet@ff290000 {
 544                 compatible = "rockchip,rk3288-gmac";
 545                 reg = <0xff290000 0x10000>;
 546                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
 547                                 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 548                 interrupt-names = "macirq", "eth_wake_irq";
 549                 rockchip,grf = <&grf>;
 550                 clocks = <&cru SCLK_MAC>,
 551                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 552                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 553                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 554                 clock-names = "stmmaceth",
 555                         "mac_clk_rx", "mac_clk_tx",
 556                         "clk_mac_ref", "clk_mac_refout",
 557                         "aclk_mac", "pclk_mac";
 558                 resets = <&cru SRST_MAC>;
 559                 reset-names = "stmmaceth";
 560                 status = "disabled";
 561         };
 562
 563         usb_host0_ehci: usb@ff500000 {
 564                 compatible = "generic-ehci";
 565                 reg = <0xff500000 0x100>;
 566                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 567                 clocks = <&cru HCLK_USBHOST0>;
 568                 clock-names = "usbhost";
 569                 phys = <&usbphy1>;
 570                 phy-names = "usb";
 571                 status = "disabled";
 572         };
 573
 574         /* NOTE: ohci@ff520000 doesn't actually work on hardware */
 575
 576         usb_host1: usb@ff540000 {
 577                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 578                                 "snps,dwc2";
 579                 reg = <0xff540000 0x40000>;
 580                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 581                 clocks = <&cru HCLK_USBHOST1>;
 582                 clock-names = "otg";
 583                 dr_mode = "host";
 584                 phys = <&usbphy2>;
 585                 phy-names = "usb2-phy";
 586                 status = "disabled";
 587         };
 588
 589         usb_otg: usb@ff580000 {
 590                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 591                                 "snps,dwc2";
 592                 reg = <0xff580000 0x40000>;
 593                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 594                 clocks = <&cru HCLK_OTG0>;
 595                 clock-names = "otg";
 596                 dr_mode = "otg";
 597                 g-np-tx-fifo-size = <16>;
 598                 g-rx-fifo-size = <275>;
 599                 g-tx-fifo-size = <256 128 128 64 64 32>;
 600                 g-use-dma;
 601                 phys = <&usbphy0>;
 602                 phy-names = "usb2-phy";
 603                 status = "disabled";
 604         };
 605
 606         usb_hsic: usb@ff5c0000 {
 607                 compatible = "generic-ehci";
 608                 reg = <0xff5c0000 0x100>;
 609                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 610                 clocks = <&cru HCLK_HSIC>;
 611                 clock-names = "usbhost";
 612                 status = "disabled";
 613         };
 614
 615         i2c0: i2c@ff650000 {
 616                 compatible = "rockchip,rk3288-i2c";
 617                 reg = <0xff650000 0x1000>;
 618                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 619                 #address-cells = <1>;
 620                 #size-cells = <0>;
 621                 clock-names = "i2c";
 622                 clocks = <&cru PCLK_I2C0>;
 623                 pinctrl-names = "default";
 624                 pinctrl-0 = <&i2c0_xfer>;
 625                 status = "disabled";
 626         };
 627
 628         i2c2: i2c@ff660000 {
 629                 compatible = "rockchip,rk3288-i2c";
 630                 reg = <0xff660000 0x1000>;
 631                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 632                 #address-cells = <1>;
 633                 #size-cells = <0>;
 634                 clock-names = "i2c";
 635                 clocks = <&cru PCLK_I2C2>;
 636                 pinctrl-names = "default";
 637                 pinctrl-0 = <&i2c2_xfer>;
 638                 status = "disabled";
 639         };
 640
 641         pwm0: pwm@ff680000 {
 642                 compatible = "rockchip,rk3288-pwm";
 643                 reg = <0xff680000 0x10>;
 644                 #pwm-cells = <3>;
 645                 pinctrl-names = "default";
 646                 pinctrl-0 = <&pwm0_pin>;
 647                 clocks = <&cru PCLK_PWM>;
 648                 clock-names = "pwm";
 649                 status = "disabled";
 650         };
 651
 652         pwm1: pwm@ff680010 {
 653                 compatible = "rockchip,rk3288-pwm";
 654                 reg = <0xff680010 0x10>;
 655                 #pwm-cells = <3>;
 656                 pinctrl-names = "default";
 657                 pinctrl-0 = <&pwm1_pin>;
 658                 clocks = <&cru PCLK_PWM>;
 659                 clock-names = "pwm";
 660                 status = "disabled";
 661         };
 662
 663         pwm2: pwm@ff680020 {
 664                 compatible = "rockchip,rk3288-pwm";
 665                 reg = <0xff680020 0x10>;
 666                 #pwm-cells = <3>;
 667                 pinctrl-names = "default";
 668                 pinctrl-0 = <&pwm2_pin>;
 669                 clocks = <&cru PCLK_PWM>;
 670                 clock-names = "pwm";
 671                 status = "disabled";
 672         };
 673
 674         pwm3: pwm@ff680030 {
 675                 compatible = "rockchip,rk3288-pwm";
 676                 reg = <0xff680030 0x10>;
 677                 #pwm-cells = <2>;
 678                 pinctrl-names = "default";
 679                 pinctrl-0 = <&pwm3_pin>;
 680                 clocks = <&cru PCLK_PWM>;
 681                 clock-names = "pwm";
 682                 status = "disabled";
 683         };
 684
 685         bus_intmem@ff700000 {
 686                 compatible = "mmio-sram";
 687                 reg = <0xff700000 0x18000>;
 688                 #address-cells = <1>;
 689                 #size-cells = <1>;
 690                 ranges = <0 0xff700000 0x18000>;
 691                 smp-sram@0 {
 692                         compatible = "rockchip,rk3066-smp-sram";
 693                         reg = <0x00 0x10>;
 694                 };
 695         };
 696
 697         sram@ff720000 {
 698                 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
 699                 reg = <0xff720000 0x1000>;
 700         };
 701
 702         pmu: power-management@ff730000 {
 703                 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
 704                 reg = <0xff730000 0x100>;
 705
 706                 power: power-controller {
 707                         compatible = "rockchip,rk3288-power-controller";
 708                         #power-domain-cells = <1>;
 709                         #address-cells = <1>;
 710                         #size-cells = <0>;
 711
 712                         assigned-clocks = <&cru SCLK_EDP_24M>;
 713                         assigned-clock-parents = <&xin24m>;
 714
 715                         /*
 716                          * Note: Although SCLK_* are the working clocks
 717                          * of device without including on the NOC, needed for
 718                          * synchronous reset.
 719                          *
 720                          * The clocks on the which NOC:
 721                          * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 722                          * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
 723                          * ACLK_RGA is on ACLK_RGA_NIU.
 724                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 725                          *
 726                          * Which clock are device clocks:
 727                          *      clocks          devices
 728                          *      *_IEP           IEP:Image Enhancement Processor
 729                          *      *_ISP           ISP:Image Signal Processing
 730                          *      *_VIP           VIP:Video Input Processor
 731                          *      *_VOP*          VOP:Visual Output Processor
 732                          *      *_RGA           RGA
 733                          *      *_EDP*          EDP
 734                          *      *_LVDS_*        LVDS
 735                          *      *_HDMI          HDMI
 736                          *      *_MIPI_*        MIPI
 737                          */
 738                         power-domain@RK3288_PD_VIO {
 739                                 reg = <RK3288_PD_VIO>;
 740                                 clocks = <&cru ACLK_IEP>,
 741                                          <&cru ACLK_ISP>,
 742                                          <&cru ACLK_RGA>,
 743                                          <&cru ACLK_VIP>,
 744                                          <&cru ACLK_VOP0>,
 745                                          <&cru ACLK_VOP1>,
 746                                          <&cru DCLK_VOP0>,
 747                                          <&cru DCLK_VOP1>,
 748                                          <&cru HCLK_IEP>,
 749                                          <&cru HCLK_ISP>,
 750                                          <&cru HCLK_RGA>,
 751                                          <&cru HCLK_VIP>,
 752                                          <&cru HCLK_VOP0>,
 753                                          <&cru HCLK_VOP1>,
 754                                          <&cru PCLK_EDP_CTRL>,
 755                                          <&cru PCLK_HDMI_CTRL>,
 756                                          <&cru PCLK_LVDS_PHY>,
 757                                          <&cru PCLK_MIPI_CSI>,
 758                                          <&cru PCLK_MIPI_DSI0>,
 759                                          <&cru PCLK_MIPI_DSI1>,
 760                                          <&cru SCLK_EDP_24M>,
 761                                          <&cru SCLK_EDP>,
 762                                          <&cru SCLK_ISP_JPE>,
 763                                          <&cru SCLK_ISP>,
 764                                          <&cru SCLK_RGA>;
 765                         };
 766
 767                         /*
 768                          * Note: The following 3 are HEVC(H.265) clocks,
 769                          * and on the ACLK_HEVC_NIU (NOC).
 770                          */
 771                         power-domain@RK3288_PD_HEVC {
 772                                 reg = <RK3288_PD_HEVC>;
 773                                 clocks = <&cru ACLK_HEVC>,
 774                                          <&cru SCLK_HEVC_CABAC>,
 775                                          <&cru SCLK_HEVC_CORE>;
 776                         };
 777
 778                         /*
 779                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
 780                          * (video endecoder & decoder) clocks that on the
 781                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
 782                          */
 783                         power-domain@RK3288_PD_VIDEO {
 784                                 reg = <RK3288_PD_VIDEO>;
 785                                 clocks = <&cru ACLK_VCODEC>,
 786                                          <&cru HCLK_VCODEC>;
 787                         };
 788
 789                         /*
 790                          * Note: ACLK_GPU is the GPU clock,
 791                          * and on the ACLK_GPU_NIU (NOC).
 792                          */
 793                         power-domain@RK3288_PD_GPU {
 794                                 reg = <RK3288_PD_GPU>;
 795                                 clocks = <&cru ACLK_GPU>;
 796                         };
 797                 };
 798
 799                 reboot-mode {
 800                         compatible = "syscon-reboot-mode";
 801                         offset = <0x94>;
 802                         mode-normal = <BOOT_NORMAL>;
 803                         mode-recovery = <BOOT_RECOVERY>;
 804                         mode-bootloader = <BOOT_FASTBOOT>;
 805                         mode-loader = <BOOT_BL_DOWNLOAD>;
 806                 };
 807         };
 808
 809         sgrf: syscon@ff740000 {
 810                 compatible = "rockchip,rk3288-sgrf", "syscon";
 811                 reg = <0xff740000 0x1000>;
 812         };
 813
 814         cru: clock-controller@ff760000 {
 815                 compatible = "rockchip,rk3288-cru";
 816                 reg = <0xff760000 0x1000>;
 817                 rockchip,grf = <&grf>;
 818                 #clock-cells = <1>;
 819                 #reset-cells = <1>;
 820                 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 821                                   <&cru PLL_NPLL>, <&cru ACLK_CPU>,
 822                                   <&cru HCLK_CPU>, <&cru PCLK_CPU>,
 823                                   <&cru ACLK_PERI>, <&cru HCLK_PERI>,
 824                                   <&cru PCLK_PERI>;
 825                 assigned-clock-rates = <594000000>, <400000000>,
 826                                        <500000000>, <300000000>,
 827                                        <150000000>, <75000000>,
 828                                        <300000000>, <150000000>,
 829                                        <75000000>;
 830         };
 831
 832         grf: syscon@ff770000 {
 833                 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
 834                 reg = <0xff770000 0x1000>;
 835
 836                 edp_phy: edp-phy {
 837                         compatible = "rockchip,rk3288-dp-phy";
 838                         clocks = <&cru SCLK_EDP_24M>;
 839                         clock-names = "24m";
 840                         #phy-cells = <0>;
 841                         status = "disabled";
 842                 };
 843
 844                 io_domains: io-domains {
 845                         compatible = "rockchip,rk3288-io-voltage-domain";
 846                         status = "disabled";
 847                 };
 848
 849                 usbphy: usbphy {
 850                         compatible = "rockchip,rk3288-usb-phy";
 851                         #address-cells = <1>;
 852                         #size-cells = <0>;
 853                         status = "disabled";
 854
 855                         usbphy0: usb-phy@320 {
 856                                 #phy-cells = <0>;
 857                                 reg = <0x320>;
 858                                 clocks = <&cru SCLK_OTGPHY0>;
 859                                 clock-names = "phyclk";
 860                                 #clock-cells = <0>;
 861                         };
 862
 863                         usbphy1: usb-phy@334 {
 864                                 #phy-cells = <0>;
 865                                 reg = <0x334>;
 866                                 clocks = <&cru SCLK_OTGPHY1>;
 867                                 clock-names = "phyclk";
 868                                 #clock-cells = <0>;
 869                         };
 870
 871                         usbphy2: usb-phy@348 {
 872                                 #phy-cells = <0>;
 873                                 reg = <0x348>;
 874                                 clocks = <&cru SCLK_OTGPHY2>;
 875                                 clock-names = "phyclk";
 876                                 #clock-cells = <0>;
 877                         };
 878                 };
 879         };
 880
 881         wdt: watchdog@ff800000 {
 882                 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
 883                 reg = <0xff800000 0x100>;
 884                 clocks = <&cru PCLK_WDT>;
 885                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 886                 status = "disabled";
 887         };
 888
 889         spdif: sound@ff88b0000 {
 890                 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
 891                 reg = <0xff8b0000 0x10000>;
 892                 #sound-dai-cells = <0>;
 893                 clock-names = "hclk", "mclk";
 894                 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
 895                 dmas = <&dmac_bus_s 3>;
 896                 dma-names = "tx";
 897                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 898                 pinctrl-names = "default";
 899                 pinctrl-0 = <&spdif_tx>;
 900                 rockchip,grf = <&grf>;
 901                 status = "disabled";
 902         };
 903
 904         i2s: i2s@ff890000 {
 905                 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
 906                 reg = <0xff890000 0x10000>;
 907                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 908                 #address-cells = <1>;
 909                 #size-cells = <0>;
 910                 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
 911                 dma-names = "tx", "rx";
 912                 clock-names = "i2s_hclk", "i2s_clk";
 913                 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
 914                 pinctrl-names = "default";
 915                 pinctrl-0 = <&i2s0_bus>;
 916                 rockchip,playback-channels = <8>;
 917                 rockchip,capture-channels = <2>;
 918                 status = "disabled";
 919         };
 920
 921         crypto: crypto@ff8a0000 {
 922                 compatible = "rockchip,rk3288-crypto";
 923                 reg = <0xff8a0000 0x4000>;
 924                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 925                 clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>,
 926                          <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>;
 927                 clock-names = "aclk", "hclk", "sclk", "apb_pclk";
 928                 resets = <&cru SRST_CRYPTO>;
 929                 reset-names = "crypto-rst";
 930                 status = "okay";
 931         };
 932
 933         vopb: vop@ff930000 {
 934                 compatible = "rockchip,rk3288-vop";
 935                 reg = <0xff930000 0x19c>;
 936                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 937                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
 938                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 939                 power-domains = <&power RK3288_PD_VIO>;
 940                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
 941                 reset-names = "axi", "ahb", "dclk";
 942                 iommus = <&vopb_mmu>;
 943                 status = "disabled";
 944
 945                 vopb_out: port {
 946                         #address-cells = <1>;
 947                         #size-cells = <0>;
 948
 949                         vopb_out_hdmi: endpoint@0 {
 950                                 reg = <0>;
 951                                 remote-endpoint = <&hdmi_in_vopb>;
 952                         };
 953
 954                         vopb_out_edp: endpoint@1 {
 955                                 reg = <1>;
 956                                 remote-endpoint = <&edp_in_vopb>;
 957                         };
 958
 959                         vopb_out_mipi: endpoint@2 {
 960                                 reg = <2>;
 961                                 remote-endpoint = <&mipi_in_vopb>;
 962                         };
 963                 };
 964         };
 965
 966         vopb_mmu: iommu@ff930300 {
 967                 compatible = "rockchip,iommu";
 968                 reg = <0xff930300 0x100>;
 969                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 970                 interrupt-names = "vopb_mmu";
 971                 power-domains = <&power RK3288_PD_VIO>;
 972                 #iommu-cells = <0>;
 973                 status = "disabled";
 974         };
 975
 976         vopl: vop@ff940000 {
 977                 compatible = "rockchip,rk3288-vop";
 978                 reg = <0xff940000 0x19c>;
 979                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 980                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
 981                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 982                 power-domains = <&power RK3288_PD_VIO>;
 983                 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
 984                 reset-names = "axi", "ahb", "dclk";
 985                 iommus = <&vopl_mmu>;
 986                 status = "disabled";
 987
 988                 vopl_out: port {
 989                         #address-cells = <1>;
 990                         #size-cells = <0>;
 991
 992                         vopl_out_hdmi: endpoint@0 {
 993                                 reg = <0>;
 994                                 remote-endpoint = <&hdmi_in_vopl>;
 995                         };
 996
 997                         vopl_out_edp: endpoint@1 {
 998                                 reg = <1>;
 999                                 remote-endpoint = <&edp_in_vopl>;
1000                         };
1001
1002                         vopl_out_mipi: endpoint@2 {
1003                                 reg = <2>;
1004                                 remote-endpoint = <&mipi_in_vopl>;
1005                         };
1006                 };
1007         };
1008
1009         vopl_mmu: iommu@ff940300 {
1010                 compatible = "rockchip,iommu";
1011                 reg = <0xff940300 0x100>;
1012                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1013                 interrupt-names = "vopl_mmu";
1014                 power-domains = <&power RK3288_PD_VIO>;
1015                 #iommu-cells = <0>;
1016                 status = "disabled";
1017         };
1018
1019         mipi_dsi: mipi@ff960000 {
1020                 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
1021                 reg = <0xff960000 0x4000>;
1022                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1023                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
1024                 clock-names = "ref", "pclk";
1025                 power-domains = <&power RK3288_PD_VIO>;
1026                 rockchip,grf = <&grf>;
1027                 #address-cells = <1>;
1028                 #size-cells = <0>;
1029                 status = "disabled";
1030
1031                 ports {
1032                         mipi_in: port {
1033                                 #address-cells = <1>;
1034                                 #size-cells = <0>;
1035                                 mipi_in_vopb: endpoint@0 {
1036                                         reg = <0>;
1037                                         remote-endpoint = <&vopb_out_mipi>;
1038                                 };
1039                                 mipi_in_vopl: endpoint@1 {
1040                                         reg = <1>;
1041                                         remote-endpoint = <&vopl_out_mipi>;
1042                                 };
1043                         };
1044                 };
1045         };
1046
1047         edp: dp@ff970000 {
1048                 compatible = "rockchip,rk3288-dp";
1049                 reg = <0xff970000 0x4000>;
1050                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1051                 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1052                 clock-names = "dp", "pclk";
1053                 phys = <&edp_phy>;
1054                 phy-names = "dp";
1055                 resets = <&cru SRST_EDP>;
1056                 reset-names = "dp";
1057                 rockchip,grf = <&grf>;
1058                 status = "disabled";
1059
1060                 ports {
1061                         #address-cells = <1>;
1062                         #size-cells = <0>;
1063                         edp_in: port@0 {
1064                                 reg = <0>;
1065                                 #address-cells = <1>;
1066                                 #size-cells = <0>;
1067                                 edp_in_vopb: endpoint@0 {
1068                                         reg = <0>;
1069                                         remote-endpoint = <&vopb_out_edp>;
1070                                 };
1071                                 edp_in_vopl: endpoint@1 {
1072                                         reg = <1>;
1073                                         remote-endpoint = <&vopl_out_edp>;
1074                                 };
1075                         };
1076                 };
1077         };
1078
1079         hdmi: hdmi@ff980000 {
1080                 compatible = "rockchip,rk3288-dw-hdmi";
1081                 reg = <0xff980000 0x20000>;
1082                 reg-io-width = <4>;
1083                 rockchip,grf = <&grf>;
1084                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1085                 clocks = <&cru  PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
1086                 clock-names = "iahb", "isfr";
1087                 power-domains = <&power RK3288_PD_VIO>;
1088                 status = "disabled";
1089
1090                 ports {
1091                         hdmi_in: port {
1092                                 #address-cells = <1>;
1093                                 #size-cells = <0>;
1094                                 hdmi_in_vopb: endpoint@0 {
1095                                         reg = <0>;
1096                                         remote-endpoint = <&vopb_out_hdmi>;
1097                                 };
1098                                 hdmi_in_vopl: endpoint@1 {
1099                                         reg = <1>;
1100                                         remote-endpoint = <&vopl_out_hdmi>;
1101                                 };
1102                         };
1103                 };
1104         };
1105
1106         gic: interrupt-controller@ffc01000 {
1107                 compatible = "arm,gic-400";
1108                 interrupt-controller;
1109                 #interrupt-cells = <3>;
1110                 #address-cells = <0>;
1111
1112                 reg = <0xffc01000 0x1000>,
1113                       <0xffc02000 0x1000>,
1114                       <0xffc04000 0x2000>,
1115                       <0xffc06000 0x2000>;
1116                 interrupts = <GIC_PPI 9 0xf04>;
1117         };
1118
1119         efuse: efuse@ffb40000 {
1120                 compatible = "rockchip,rockchip-efuse";
1121                 reg = <0xffb40000 0x20>;
1122                 #address-cells = <1>;
1123                 #size-cells = <1>;
1124                 clocks = <&cru PCLK_EFUSE256>;
1125                 clock-names = "pclk_efuse";
1126
1127                 cpu_leakage: cpu_leakage@17 {
1128                         reg = <0x17 0x1>;
1129                 };
1130         };
1131
1132         pinctrl: pinctrl {
1133                 compatible = "rockchip,rk3288-pinctrl";
1134                 rockchip,grf = <&grf>;
1135                 rockchip,pmu = <&pmu>;
1136                 #address-cells = <1>;
1137                 #size-cells = <1>;
1138                 ranges;
1139
1140                 gpio0: gpio0@ff750000 {
1141                         compatible = "rockchip,gpio-bank";
1142                         reg =   <0xff750000 0x100>;
1143                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1144                         clocks = <&cru PCLK_GPIO0>;
1145
1146                         gpio-controller;
1147                         #gpio-cells = <2>;
1148
1149                         interrupt-controller;
1150                         #interrupt-cells = <2>;
1151                 };
1152
1153                 gpio1: gpio1@ff780000 {
1154                         compatible = "rockchip,gpio-bank";
1155                         reg = <0xff780000 0x100>;
1156                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1157                         clocks = <&cru PCLK_GPIO1>;
1158
1159                         gpio-controller;
1160                         #gpio-cells = <2>;
1161
1162                         interrupt-controller;
1163                         #interrupt-cells = <2>;
1164                 };
1165
1166                 gpio2: gpio2@ff790000 {
1167                         compatible = "rockchip,gpio-bank";
1168                         reg = <0xff790000 0x100>;
1169                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1170                         clocks = <&cru PCLK_GPIO2>;
1171
1172                         gpio-controller;
1173                         #gpio-cells = <2>;
1174
1175                         interrupt-controller;
1176                         #interrupt-cells = <2>;
1177                 };
1178
1179                 gpio3: gpio3@ff7a0000 {
1180                         compatible = "rockchip,gpio-bank";
1181                         reg = <0xff7a0000 0x100>;
1182                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1183                         clocks = <&cru PCLK_GPIO3>;
1184
1185                         gpio-controller;
1186                         #gpio-cells = <2>;
1187
1188                         interrupt-controller;
1189                         #interrupt-cells = <2>;
1190                 };
1191
1192                 gpio4: gpio4@ff7b0000 {
1193                         compatible = "rockchip,gpio-bank";
1194                         reg = <0xff7b0000 0x100>;
1195                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1196                         clocks = <&cru PCLK_GPIO4>;
1197
1198                         gpio-controller;
1199                         #gpio-cells = <2>;
1200
1201                         interrupt-controller;
1202                         #interrupt-cells = <2>;
1203                 };
1204
1205                 gpio5: gpio5@ff7c0000 {
1206                         compatible = "rockchip,gpio-bank";
1207                         reg = <0xff7c0000 0x100>;
1208                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1209                         clocks = <&cru PCLK_GPIO5>;
1210
1211                         gpio-controller;
1212                         #gpio-cells = <2>;
1213
1214                         interrupt-controller;
1215                         #interrupt-cells = <2>;
1216                 };
1217
1218                 gpio6: gpio6@ff7d0000 {
1219                         compatible = "rockchip,gpio-bank";
1220                         reg = <0xff7d0000 0x100>;
1221                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1222                         clocks = <&cru PCLK_GPIO6>;
1223
1224                         gpio-controller;
1225                         #gpio-cells = <2>;
1226
1227                         interrupt-controller;
1228                         #interrupt-cells = <2>;
1229                 };
1230
1231                 gpio7: gpio7@ff7e0000 {
1232                         compatible = "rockchip,gpio-bank";
1233                         reg = <0xff7e0000 0x100>;
1234                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1235                         clocks = <&cru PCLK_GPIO7>;
1236
1237                         gpio-controller;
1238                         #gpio-cells = <2>;
1239
1240                         interrupt-controller;
1241                         #interrupt-cells = <2>;
1242                 };
1243
1244                 gpio8: gpio8@ff7f0000 {
1245                         compatible = "rockchip,gpio-bank";
1246                         reg = <0xff7f0000 0x100>;
1247                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1248                         clocks = <&cru PCLK_GPIO8>;
1249
1250                         gpio-controller;
1251                         #gpio-cells = <2>;
1252
1253                         interrupt-controller;
1254                         #interrupt-cells = <2>;
1255                 };
1256
1257                 hdmi {
1258                         hdmi_ddc: hdmi-ddc {
1259                                 rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>,
1260                                                 <7 20 RK_FUNC_2 &pcfg_pull_none>;
1261                         };
1262                 };
1263
1264                 pcfg_pull_up: pcfg-pull-up {
1265                         bias-pull-up;
1266                 };
1267
1268                 pcfg_pull_down: pcfg-pull-down {
1269                         bias-pull-down;
1270                 };
1271
1272                 pcfg_pull_none: pcfg-pull-none {
1273                         bias-disable;
1274                 };
1275
1276                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1277                         bias-disable;
1278                         drive-strength = <12>;
1279                 };
1280
1281                 suspend {
1282                         global_pwroff: global-pwroff {
1283                                 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1284                         };
1285
1286                         ddrio_pwroff: ddrio-pwroff {
1287                                 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1288                         };
1289
1290                         ddr0_retention: ddr0-retention {
1291                                 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1292                         };
1293
1294                         ddr1_retention: ddr1-retention {
1295                                 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1296                         };
1297                 };
1298
1299                 edp {
1300                         edp_hpd: edp-hpd {
1301                                 rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>;
1302                         };
1303                 };
1304
1305                 i2c0 {
1306                         i2c0_xfer: i2c0-xfer {
1307                                 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1308                                                 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1309                         };
1310                 };
1311
1312                 i2c1 {
1313                         i2c1_xfer: i2c1-xfer {
1314                                 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1315                                                 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1316                         };
1317                 };
1318
1319                 i2c2 {
1320                         i2c2_xfer: i2c2-xfer {
1321                                 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1322                                                 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1323                         };
1324                 };
1325
1326                 i2c3 {
1327                         i2c3_xfer: i2c3-xfer {
1328                                 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1329                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1330                         };
1331                 };
1332
1333                 i2c4 {
1334                         i2c4_xfer: i2c4-xfer {
1335                                 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1336                                                 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1337                         };
1338                 };
1339
1340                 i2c5 {
1341                         i2c5_xfer: i2c5-xfer {
1342                                 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1343                                                 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1344                         };
1345                 };
1346
1347                 i2s0 {
1348                         i2s0_bus: i2s0-bus {
1349                                 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1350                                                 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1351                                                 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1352                                                 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1353                                                 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1354                                                 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1355                         };
1356                 };
1357
1358                 sdmmc {
1359                         sdmmc_clk: sdmmc-clk {
1360                                 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1361                         };
1362
1363                         sdmmc_cmd: sdmmc-cmd {
1364                                 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1365                         };
1366
1367                         sdmmc_cd: sdmmc-cd {
1368                                 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1369                         };
1370
1371                         sdmmc_bus1: sdmmc-bus1 {
1372                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1373                         };
1374
1375                         sdmmc_bus4: sdmmc-bus4 {
1376                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1377                                                 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1378                                                 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1379                                                 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1380                         };
1381                 };
1382
1383                 sdio0 {
1384                         sdio0_bus1: sdio0-bus1 {
1385                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1386                         };
1387
1388                         sdio0_bus4: sdio0-bus4 {
1389                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1390                                                 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1391                                                 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1392                                                 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1393                         };
1394
1395                         sdio0_cmd: sdio0-cmd {
1396                                 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1397                         };
1398
1399                         sdio0_clk: sdio0-clk {
1400                                 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1401                         };
1402
1403                         sdio0_cd: sdio0-cd {
1404                                 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1405                         };
1406
1407                         sdio0_wp: sdio0-wp {
1408                                 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1409                         };
1410
1411                         sdio0_pwr: sdio0-pwr {
1412                                 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1413                         };
1414
1415                         sdio0_bkpwr: sdio0-bkpwr {
1416                                 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1417                         };
1418
1419                         sdio0_int: sdio0-int {
1420                                 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1421                         };
1422                 };
1423
1424                 sdio1 {
1425                         sdio1_bus1: sdio1-bus1 {
1426                                 rockchip,pins = <3 24 4 &pcfg_pull_up>;
1427                         };
1428
1429                         sdio1_bus4: sdio1-bus4 {
1430                                 rockchip,pins = <3 24 4 &pcfg_pull_up>,
1431                                                 <3 25 4 &pcfg_pull_up>,
1432                                                 <3 26 4 &pcfg_pull_up>,
1433                                                 <3 27 4 &pcfg_pull_up>;
1434                         };
1435
1436                         sdio1_cd: sdio1-cd {
1437                                 rockchip,pins = <3 28 4 &pcfg_pull_up>;
1438                         };
1439
1440                         sdio1_wp: sdio1-wp {
1441                                 rockchip,pins = <3 29 4 &pcfg_pull_up>;
1442                         };
1443
1444                         sdio1_bkpwr: sdio1-bkpwr {
1445                                 rockchip,pins = <3 30 4 &pcfg_pull_up>;
1446                         };
1447
1448                         sdio1_int: sdio1-int {
1449                                 rockchip,pins = <3 31 4 &pcfg_pull_up>;
1450                         };
1451
1452                         sdio1_cmd: sdio1-cmd {
1453                                 rockchip,pins = <4 6 4 &pcfg_pull_up>;
1454                         };
1455
1456                         sdio1_clk: sdio1-clk {
1457                                 rockchip,pins = <4 7 4 &pcfg_pull_none>;
1458                         };
1459
1460                         sdio1_pwr: sdio1-pwr {
1461                                 rockchip,pins = <4 9 4 &pcfg_pull_up>;
1462                         };
1463                 };
1464
1465                 emmc {
1466                         emmc_clk: emmc-clk {
1467                                 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1468                         };
1469
1470                         emmc_cmd: emmc-cmd {
1471                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1472                         };
1473
1474                         emmc_pwr: emmc-pwr {
1475                                 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1476                         };
1477
1478                         emmc_bus1: emmc-bus1 {
1479                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1480                         };
1481
1482                         emmc_bus4: emmc-bus4 {
1483                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1484                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1485                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1486                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1487                         };
1488
1489                         emmc_bus8: emmc-bus8 {
1490                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1491                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1492                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1493                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1494                                                 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1495                                                 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1496                                                 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1497                                                 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1498                         };
1499                 };
1500
1501                 spi0 {
1502                         spi0_clk: spi0-clk {
1503                                 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1504                         };
1505                         spi0_cs0: spi0-cs0 {
1506                                 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1507                         };
1508                         spi0_tx: spi0-tx {
1509                                 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1510                         };
1511                         spi0_rx: spi0-rx {
1512                                 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1513                         };
1514                         spi0_cs1: spi0-cs1 {
1515                                 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1516                         };
1517                 };
1518                 spi1 {
1519                         spi1_clk: spi1-clk {
1520                                 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1521                         };
1522                         spi1_cs0: spi1-cs0 {
1523                                 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1524                         };
1525                         spi1_rx: spi1-rx {
1526                                 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1527                         };
1528                         spi1_tx: spi1-tx {
1529                                 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1530                         };
1531                 };
1532
1533                 spi2 {
1534                         spi2_cs1: spi2-cs1 {
1535                                 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1536                         };
1537                         spi2_clk: spi2-clk {
1538                                 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1539                         };
1540                         spi2_cs0: spi2-cs0 {
1541                                 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1542                         };
1543                         spi2_rx: spi2-rx {
1544                                 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1545                         };
1546                         spi2_tx: spi2-tx {
1547                                 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1548                         };
1549                 };
1550
1551                 uart0 {
1552                         uart0_xfer: uart0-xfer {
1553                                 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1554                                                 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1555                         };
1556
1557                         uart0_cts: uart0-cts {
1558                                 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>;
1559                         };
1560
1561                         uart0_rts: uart0-rts {
1562                                 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1563                         };
1564                 };
1565
1566                 uart1 {
1567                         uart1_xfer: uart1-xfer {
1568                                 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1569                                                 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1570                         };
1571
1572                         uart1_cts: uart1-cts {
1573                                 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>;
1574                         };
1575
1576                         uart1_rts: uart1-rts {
1577                                 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1578                         };
1579                 };
1580
1581                 uart2 {
1582                         uart2_xfer: uart2-xfer {
1583                                 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1584                                                 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1585                         };
1586                         /* no rts / cts for uart2 */
1587                 };
1588
1589                 uart3 {
1590                         uart3_xfer: uart3-xfer {
1591                                 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1592                                                 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1593                         };
1594
1595                         uart3_cts: uart3-cts {
1596                                 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>;
1597                         };
1598
1599                         uart3_rts: uart3-rts {
1600                                 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1601                         };
1602                 };
1603
1604                 uart4 {
1605                         uart4_xfer: uart4-xfer {
1606                                 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1607                                                 <5 13 3 &pcfg_pull_none>;
1608                         };
1609
1610                         uart4_cts: uart4-cts {
1611                                 rockchip,pins = <5 14 3 &pcfg_pull_up>;
1612                         };
1613
1614                         uart4_rts: uart4-rts {
1615                                 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1616                         };
1617                 };
1618
1619                 tsadc {
1620                         otp_gpio: otp-gpio {
1621                                 rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
1622                         };
1623
1624                         otp_out: otp-out {
1625                                 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1626                         };
1627                 };
1628
1629                 pwm0 {
1630                         pwm0_pin: pwm0-pin {
1631                                 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1632                         };
1633                 };
1634
1635                 pwm1 {
1636                         pwm1_pin: pwm1-pin {
1637                                 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1638                         };
1639                 };
1640
1641                 pwm2 {
1642                         pwm2_pin: pwm2-pin {
1643                                 rockchip,pins = <7 22 3 &pcfg_pull_none>;
1644                         };
1645                 };
1646
1647                 pwm3 {
1648                         pwm3_pin: pwm3-pin {
1649                                 rockchip,pins = <7 23 3 &pcfg_pull_none>;
1650                         };
1651                 };
1652
1653                 gmac {
1654                         rgmii_pins: rgmii-pins {
1655                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1656                                                 <3 31 3 &pcfg_pull_none>,
1657                                                 <3 26 3 &pcfg_pull_none>,
1658                                                 <3 27 3 &pcfg_pull_none>,
1659                                                 <3 28 3 &pcfg_pull_none_12ma>,
1660                                                 <3 29 3 &pcfg_pull_none_12ma>,
1661                                                 <3 24 3 &pcfg_pull_none_12ma>,
1662                                                 <3 25 3 &pcfg_pull_none_12ma>,
1663                                                 <4 0 3 &pcfg_pull_none>,
1664                                                 <4 5 3 &pcfg_pull_none>,
1665                                                 <4 6 3 &pcfg_pull_none>,
1666                                                 <4 9 3 &pcfg_pull_none_12ma>,
1667                                                 <4 4 3 &pcfg_pull_none_12ma>,
1668                                                 <4 1 3 &pcfg_pull_none>,
1669                                                 <4 3 3 &pcfg_pull_none>;
1670                         };
1671
1672                         rmii_pins: rmii-pins {
1673                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1674                                                 <3 31 3 &pcfg_pull_none>,
1675                                                 <3 28 3 &pcfg_pull_none>,
1676                                                 <3 29 3 &pcfg_pull_none>,
1677                                                 <4 0 3 &pcfg_pull_none>,
1678                                                 <4 5 3 &pcfg_pull_none>,
1679                                                 <4 4 3 &pcfg_pull_none>,
1680                                                 <4 1 3 &pcfg_pull_none>,
1681                                                 <4 2 3 &pcfg_pull_none>,
1682                                                 <4 3 3 &pcfg_pull_none>;
1683                         };
1684                 };
1685
1686                 spdif {
1687                         spdif_tx: spdif-tx {
1688                                 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;
1689                         };
1690                 };
1691         };
1692 };