arch/arm/boot/dts/rk3288.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2
   3 #include <dt-bindings/gpio/gpio.h>
   4 #include <dt-bindings/interrupt-controller/irq.h>
   5 #include <dt-bindings/interrupt-controller/arm-gic.h>
   6 #include <dt-bindings/pinctrl/rockchip.h>
   7 #include <dt-bindings/clock/rk3288-cru.h>
   8 #include <dt-bindings/power/rk3288-power.h>
   9 #include <dt-bindings/thermal/thermal.h>
  10 #include <dt-bindings/power/rk3288-power.h>
  11 #include <dt-bindings/soc/rockchip,boot-mode.h>
  12
  13 / {
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16
  17         compatible = "rockchip,rk3288";
  18
  19         interrupt-parent = <&gic>;
  20
  21         aliases {
  22                 ethernet0 = &gmac;
  23                 i2c0 = &i2c0;
  24                 i2c1 = &i2c1;
  25                 i2c2 = &i2c2;
  26                 i2c3 = &i2c3;
  27                 i2c4 = &i2c4;
  28                 i2c5 = &i2c5;
  29                 mshc0 = &emmc;
  30                 mshc1 = &sdmmc;
  31                 mshc2 = &sdio0;
  32                 mshc3 = &sdio1;
  33                 serial0 = &uart0;
  34                 serial1 = &uart1;
  35                 serial2 = &uart2;
  36                 serial3 = &uart3;
  37                 serial4 = &uart4;
  38                 spi0 = &spi0;
  39                 spi1 = &spi1;
  40                 spi2 = &spi2;
  41         };
  42
  43         arm-pmu {
  44                 compatible = "arm,cortex-a12-pmu";
  45                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
  46                              <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
  47                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
  48                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
  49                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  50         };
  51
  52         cpus {
  53                 #address-cells = <1>;
  54                 #size-cells = <0>;
  55                 enable-method = "rockchip,rk3066-smp";
  56                 rockchip,pmu = <&pmu>;
  57
  58                 cpu0: cpu@500 {
  59                         device_type = "cpu";
  60                         compatible = "arm,cortex-a12";
  61                         reg = <0x500>;
  62                         resets = <&cru SRST_CORE0>;
  63                         operating-points-v2 = <&cpu_opp_table>;
  64                         #cooling-cells = <2>; /* min followed by max */
  65                         clock-latency = <40000>;
  66                         clocks = <&cru ARMCLK>;
  67                         dynamic-power-coefficient = <370>;
  68                 };
  69                 cpu1: cpu@501 {
  70                         device_type = "cpu";
  71                         compatible = "arm,cortex-a12";
  72                         reg = <0x501>;
  73                         resets = <&cru SRST_CORE1>;
  74                         operating-points-v2 = <&cpu_opp_table>;
  75                         #cooling-cells = <2>; /* min followed by max */
  76                         clock-latency = <40000>;
  77                         clocks = <&cru ARMCLK>;
  78                         dynamic-power-coefficient = <370>;
  79                 };
  80                 cpu2: cpu@502 {
  81                         device_type = "cpu";
  82                         compatible = "arm,cortex-a12";
  83                         reg = <0x502>;
  84                         resets = <&cru SRST_CORE2>;
  85                         operating-points-v2 = <&cpu_opp_table>;
  86                         #cooling-cells = <2>; /* min followed by max */
  87                         clock-latency = <40000>;
  88                         clocks = <&cru ARMCLK>;
  89                         dynamic-power-coefficient = <370>;
  90                 };
  91                 cpu3: cpu@503 {
  92                         device_type = "cpu";
  93                         compatible = "arm,cortex-a12";
  94                         reg = <0x503>;
  95                         resets = <&cru SRST_CORE3>;
  96                         operating-points-v2 = <&cpu_opp_table>;
  97                         #cooling-cells = <2>; /* min followed by max */
  98                         clock-latency = <40000>;
  99                         clocks = <&cru ARMCLK>;
 100                         dynamic-power-coefficient = <370>;
 101                 };
 102         };
 103
 104         cpu_opp_table: cpu-opp-table {
 105                 compatible = "operating-points-v2";
 106                 opp-shared;
 107
 108                 opp-126000000 {
 109                         opp-hz = /bits/ 64 <126000000>;
 110                         opp-microvolt = <900000>;
 111                 };
 112                 opp-216000000 {
 113                         opp-hz = /bits/ 64 <216000000>;
 114                         opp-microvolt = <900000>;
 115                 };
 116                 opp-312000000 {
 117                         opp-hz = /bits/ 64 <312000000>;
 118                         opp-microvolt = <900000>;
 119                 };
 120                 opp-408000000 {
 121                         opp-hz = /bits/ 64 <408000000>;
 122                         opp-microvolt = <900000>;
 123                 };
 124                 opp-600000000 {
 125                         opp-hz = /bits/ 64 <600000000>;
 126                         opp-microvolt = <900000>;
 127                 };
 128                 opp-696000000 {
 129                         opp-hz = /bits/ 64 <696000000>;
 130                         opp-microvolt = <950000>;
 131                 };
 132                 opp-816000000 {
 133                         opp-hz = /bits/ 64 <816000000>;
 134                         opp-microvolt = <1000000>;
 135                 };
 136                 opp-1008000000 {
 137                         opp-hz = /bits/ 64 <1008000000>;
 138                         opp-microvolt = <1050000>;
 139                 };
 140                 opp-1200000000 {
 141                         opp-hz = /bits/ 64 <1200000000>;
 142                         opp-microvolt = <1100000>;
 143                 };
 144                 opp-1416000000 {
 145                         opp-hz = /bits/ 64 <1416000000>;
 146                         opp-microvolt = <1200000>;
 147                 };
 148                 opp-1512000000 {
 149                         opp-hz = /bits/ 64 <1512000000>;
 150                         opp-microvolt = <1300000>;
 151                 };
 152                 opp-1608000000 {
 153                         opp-hz = /bits/ 64 <1608000000>;
 154                         opp-microvolt = <1350000>;
 155                 };
 156         };
 157
 158         amba {
 159                 compatible = "simple-bus";
 160                 #address-cells = <2>;
 161                 #size-cells = <2>;
 162                 ranges;
 163
 164                 dmac_peri: dma-controller@ff250000 {
 165                         compatible = "arm,pl330", "arm,primecell";
 166                         reg = <0x0 0xff250000 0x0 0x4000>;
 167                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 168                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 169                         #dma-cells = <1>;
 170                         arm,pl330-broken-no-flushp;
 171                         clocks = <&cru ACLK_DMAC2>;
 172                         clock-names = "apb_pclk";
 173                 };
 174
 175                 dmac_bus_ns: dma-controller@ff600000 {
 176                         compatible = "arm,pl330", "arm,primecell";
 177                         reg = <0x0 0xff600000 0x0 0x4000>;
 178                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 179                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 180                         #dma-cells = <1>;
 181                         arm,pl330-broken-no-flushp;
 182                         clocks = <&cru ACLK_DMAC1>;
 183                         clock-names = "apb_pclk";
 184                         status = "disabled";
 185                 };
 186
 187                 dmac_bus_s: dma-controller@ffb20000 {
 188                         compatible = "arm,pl330", "arm,primecell";
 189                         reg = <0x0 0xffb20000 0x0 0x4000>;
 190                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 191                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 192                         #dma-cells = <1>;
 193                         arm,pl330-broken-no-flushp;
 194                         clocks = <&cru ACLK_DMAC1>;
 195                         clock-names = "apb_pclk";
 196                 };
 197         };
 198
 199         reserved-memory {
 200                 #address-cells = <2>;
 201                 #size-cells = <2>;
 202                 ranges;
 203
 204                 /*
 205                  * The rk3288 cannot use the memory area above 0xfe000000
 206                  * for dma operations for some reason. While there is
 207                  * probably a better solution available somewhere, we
 208                  * haven't found it yet and while devices with 2GB of ram
 209                  * are not affected, this issue prevents 4GB from booting.
 210                  * So to make these devices at least bootable, block
 211                  * this area for the time being until the real solution
 212                  * is found.
 213                  */
 214                 dma-unusable@fe000000 {
 215                         reg = <0x0 0xfe000000 0x0 0x1000000>;
 216                 };
 217         };
 218
 219         xin24m: oscillator {
 220                 compatible = "fixed-clock";
 221                 clock-frequency = <24000000>;
 222                 clock-output-names = "xin24m";
 223                 #clock-cells = <0>;
 224         };
 225
 226         timer {
 227                 compatible = "arm,armv7-timer";
 228                 arm,cpu-registers-not-fw-configured;
 229                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 230                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 231                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 232                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 233                 clock-frequency = <24000000>;
 234                 arm,no-tick-in-suspend;
 235         };
 236
 237         timer: timer@ff810000 {
 238                 compatible = "rockchip,rk3288-timer";
 239                 reg = <0x0 0xff810000 0x0 0x20>;
 240                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 241                 clocks = <&cru PCLK_TIMER>, <&xin24m>;
 242                 clock-names = "pclk", "timer";
 243         };
 244
 245         display-subsystem {
 246                 compatible = "rockchip,display-subsystem";
 247                 ports = <&vopl_out>, <&vopb_out>;
 248         };
 249
 250         sdmmc: dwmmc@ff0c0000 {
 251                 compatible = "rockchip,rk3288-dw-mshc";
 252                 max-frequency = <150000000>;
 253                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 254                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 255                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 256                 fifo-depth = <0x100>;
 257                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 258                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 259                 resets = <&cru SRST_MMC0>;
 260                 reset-names = "reset";
 261                 status = "disabled";
 262         };
 263
 264         sdio0: dwmmc@ff0d0000 {
 265                 compatible = "rockchip,rk3288-dw-mshc";
 266                 max-frequency = <150000000>;
 267                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 268                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 269                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 270                 fifo-depth = <0x100>;
 271                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 272                 reg = <0x0 0xff0d0000 0x0 0x4000>;
 273                 resets = <&cru SRST_SDIO0>;
 274                 reset-names = "reset";
 275                 status = "disabled";
 276         };
 277
 278         sdio1: dwmmc@ff0e0000 {
 279                 compatible = "rockchip,rk3288-dw-mshc";
 280                 max-frequency = <150000000>;
 281                 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
 282                          <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
 283                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 284                 fifo-depth = <0x100>;
 285                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 286                 reg = <0x0 0xff0e0000 0x0 0x4000>;
 287                 resets = <&cru SRST_SDIO1>;
 288                 reset-names = "reset";
 289                 status = "disabled";
 290         };
 291
 292         emmc: dwmmc@ff0f0000 {
 293                 compatible = "rockchip,rk3288-dw-mshc";
 294                 max-frequency = <150000000>;
 295                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 296                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 297                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 298                 fifo-depth = <0x100>;
 299                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 300                 reg = <0x0 0xff0f0000 0x0 0x4000>;
 301                 resets = <&cru SRST_EMMC>;
 302                 reset-names = "reset";
 303                 status = "disabled";
 304         };
 305
 306         saradc: saradc@ff100000 {
 307                 compatible = "rockchip,saradc";
 308                 reg = <0x0 0xff100000 0x0 0x100>;
 309                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 310                 #io-channel-cells = <1>;
 311                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 312                 clock-names = "saradc", "apb_pclk";
 313                 resets = <&cru SRST_SARADC>;
 314                 reset-names = "saradc-apb";
 315                 status = "disabled";
 316         };
 317
 318         spi0: spi@ff110000 {
 319                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 320                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 321                 clock-names = "spiclk", "apb_pclk";
 322                 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
 323                 dma-names = "tx", "rx";
 324                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 325                 pinctrl-names = "default";
 326                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 327                 reg = <0x0 0xff110000 0x0 0x1000>;
 328                 #address-cells = <1>;
 329                 #size-cells = <0>;
 330                 status = "disabled";
 331         };
 332
 333         spi1: spi@ff120000 {
 334                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 335                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 336                 clock-names = "spiclk", "apb_pclk";
 337                 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
 338                 dma-names = "tx", "rx";
 339                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 340                 pinctrl-names = "default";
 341                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 342                 reg = <0x0 0xff120000 0x0 0x1000>;
 343                 #address-cells = <1>;
 344                 #size-cells = <0>;
 345                 status = "disabled";
 346         };
 347
 348         spi2: spi@ff130000 {
 349                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 350                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 351                 clock-names = "spiclk", "apb_pclk";
 352                 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
 353                 dma-names = "tx", "rx";
 354                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 355                 pinctrl-names = "default";
 356                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 357                 reg = <0x0 0xff130000 0x0 0x1000>;
 358                 #address-cells = <1>;
 359                 #size-cells = <0>;
 360                 status = "disabled";
 361         };
 362
 363         i2c1: i2c@ff140000 {
 364                 compatible = "rockchip,rk3288-i2c";
 365                 reg = <0x0 0xff140000 0x0 0x1000>;
 366                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 367                 #address-cells = <1>;
 368                 #size-cells = <0>;
 369                 clock-names = "i2c";
 370                 clocks = <&cru PCLK_I2C1>;
 371                 pinctrl-names = "default";
 372                 pinctrl-0 = <&i2c1_xfer>;
 373                 status = "disabled";
 374         };
 375
 376         i2c3: i2c@ff150000 {
 377                 compatible = "rockchip,rk3288-i2c";
 378                 reg = <0x0 0xff150000 0x0 0x1000>;
 379                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 380                 #address-cells = <1>;
 381                 #size-cells = <0>;
 382                 clock-names = "i2c";
 383                 clocks = <&cru PCLK_I2C3>;
 384                 pinctrl-names = "default";
 385                 pinctrl-0 = <&i2c3_xfer>;
 386                 status = "disabled";
 387         };
 388
 389         i2c4: i2c@ff160000 {
 390                 compatible = "rockchip,rk3288-i2c";
 391                 reg = <0x0 0xff160000 0x0 0x1000>;
 392                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 393                 #address-cells = <1>;
 394                 #size-cells = <0>;
 395                 clock-names = "i2c";
 396                 clocks = <&cru PCLK_I2C4>;
 397                 pinctrl-names = "default";
 398                 pinctrl-0 = <&i2c4_xfer>;
 399                 status = "disabled";
 400         };
 401
 402         i2c5: i2c@ff170000 {
 403                 compatible = "rockchip,rk3288-i2c";
 404                 reg = <0x0 0xff170000 0x0 0x1000>;
 405                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 406                 #address-cells = <1>;
 407                 #size-cells = <0>;
 408                 clock-names = "i2c";
 409                 clocks = <&cru PCLK_I2C5>;
 410                 pinctrl-names = "default";
 411                 pinctrl-0 = <&i2c5_xfer>;
 412                 status = "disabled";
 413         };
 414
 415         uart0: serial@ff180000 {
 416                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 417                 reg = <0x0 0xff180000 0x0 0x100>;
 418                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 419                 reg-shift = <2>;
 420                 reg-io-width = <4>;
 421                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 422                 clock-names = "baudclk", "apb_pclk";
 423                 pinctrl-names = "default";
 424                 pinctrl-0 = <&uart0_xfer>;
 425                 status = "disabled";
 426         };
 427
 428         uart1: serial@ff190000 {
 429                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 430                 reg = <0x0 0xff190000 0x0 0x100>;
 431                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 432                 reg-shift = <2>;
 433                 reg-io-width = <4>;
 434                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 435                 clock-names = "baudclk", "apb_pclk";
 436                 pinctrl-names = "default";
 437                 pinctrl-0 = <&uart1_xfer>;
 438                 status = "disabled";
 439         };
 440
 441         uart2: serial@ff690000 {
 442                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 443                 reg = <0x0 0xff690000 0x0 0x100>;
 444                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 445                 reg-shift = <2>;
 446                 reg-io-width = <4>;
 447                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 448                 clock-names = "baudclk", "apb_pclk";
 449                 pinctrl-names = "default";
 450                 pinctrl-0 = <&uart2_xfer>;
 451                 status = "disabled";
 452         };
 453
 454         uart3: serial@ff1b0000 {
 455                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 456                 reg = <0x0 0xff1b0000 0x0 0x100>;
 457                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 458                 reg-shift = <2>;
 459                 reg-io-width = <4>;
 460                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 461                 clock-names = "baudclk", "apb_pclk";
 462                 pinctrl-names = "default";
 463                 pinctrl-0 = <&uart3_xfer>;
 464                 status = "disabled";
 465         };
 466
 467         uart4: serial@ff1c0000 {
 468                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 469                 reg = <0x0 0xff1c0000 0x0 0x100>;
 470                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 471                 reg-shift = <2>;
 472                 reg-io-width = <4>;
 473                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 474                 clock-names = "baudclk", "apb_pclk";
 475                 pinctrl-names = "default";
 476                 pinctrl-0 = <&uart4_xfer>;
 477                 status = "disabled";
 478         };
 479
 480         thermal-zones {
 481                 reserve_thermal: reserve_thermal {
 482                         polling-delay-passive = <1000>; /* milliseconds */
 483                         polling-delay = <5000>; /* milliseconds */
 484
 485                         thermal-sensors = <&tsadc 0>;
 486                 };
 487
 488                 cpu_thermal: cpu_thermal {
 489                         polling-delay-passive = <100>; /* milliseconds */
 490                         polling-delay = <5000>; /* milliseconds */
 491
 492                         thermal-sensors = <&tsadc 1>;
 493
 494                         trips {
 495                                 cpu_alert0: cpu_alert0 {
 496                                         temperature = <70000>; /* millicelsius */
 497                                         hysteresis = <2000>; /* millicelsius */
 498                                         type = "passive";
 499                                 };
 500                                 cpu_alert1: cpu_alert1 {
 501                                         temperature = <75000>; /* millicelsius */
 502                                         hysteresis = <2000>; /* millicelsius */
 503                                         type = "passive";
 504                                 };
 505                                 cpu_crit: cpu_crit {
 506                                         temperature = <90000>; /* millicelsius */
 507                                         hysteresis = <2000>; /* millicelsius */
 508                                         type = "critical";
 509                                 };
 510                         };
 511
 512                         cooling-maps {
 513                                 map0 {
 514                                         trip = <&cpu_alert0>;
 515                                         cooling-device =
 516                                                 <&cpu0 THERMAL_NO_LIMIT 6>,
 517                                                 <&cpu1 THERMAL_NO_LIMIT 6>,
 518                                                 <&cpu2 THERMAL_NO_LIMIT 6>,
 519                                                 <&cpu3 THERMAL_NO_LIMIT 6>;
 520                                 };
 521                                 map1 {
 522                                         trip = <&cpu_alert1>;
 523                                         cooling-device =
 524                                                 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 525                                                 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 526                                                 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 527                                                 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 528                                 };
 529                         };
 530                 };
 531
 532                 gpu_thermal: gpu_thermal {
 533                         polling-delay-passive = <100>; /* milliseconds */
 534                         polling-delay = <5000>; /* milliseconds */
 535
 536                         thermal-sensors = <&tsadc 2>;
 537
 538                         trips {
 539                                 gpu_alert0: gpu_alert0 {
 540                                         temperature = <70000>; /* millicelsius */
 541                                         hysteresis = <2000>; /* millicelsius */
 542                                         type = "passive";
 543                                 };
 544                                 gpu_crit: gpu_crit {
 545                                         temperature = <90000>; /* millicelsius */
 546                                         hysteresis = <2000>; /* millicelsius */
 547                                         type = "critical";
 548                                 };
 549                         };
 550
 551                         cooling-maps {
 552                                 map0 {
 553                                         trip = <&gpu_alert0>;
 554                                         cooling-device =
 555                                                 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 556                                 };
 557                         };
 558                 };
 559         };
 560
 561         tsadc: tsadc@ff280000 {
 562                 compatible = "rockchip,rk3288-tsadc";
 563                 reg = <0x0 0xff280000 0x0 0x100>;
 564                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 565                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 566                 clock-names = "tsadc", "apb_pclk";
 567                 resets = <&cru SRST_TSADC>;
 568                 reset-names = "tsadc-apb";
 569                 pinctrl-names = "init", "default", "sleep";
 570                 pinctrl-0 = <&otp_gpio>;
 571                 pinctrl-1 = <&otp_out>;
 572                 pinctrl-2 = <&otp_gpio>;
 573                 #thermal-sensor-cells = <1>;
 574                 rockchip,grf = <&grf>;
 575                 rockchip,hw-tshut-temp = <95000>;
 576                 status = "disabled";
 577         };
 578
 579         gmac: ethernet@ff290000 {
 580                 compatible = "rockchip,rk3288-gmac";
 581                 reg = <0x0 0xff290000 0x0 0x10000>;
 582                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
 583                                 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 584                 interrupt-names = "macirq", "eth_wake_irq";
 585                 rockchip,grf = <&grf>;
 586                 clocks = <&cru SCLK_MAC>,
 587                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 588                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 589                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 590                 clock-names = "stmmaceth",
 591                         "mac_clk_rx", "mac_clk_tx",
 592                         "clk_mac_ref", "clk_mac_refout",
 593                         "aclk_mac", "pclk_mac";
 594                 resets = <&cru SRST_MAC>;
 595                 reset-names = "stmmaceth";
 596                 status = "disabled";
 597         };
 598
 599         usb_host0_ehci: usb@ff500000 {
 600                 compatible = "generic-ehci";
 601                 reg = <0x0 0xff500000 0x0 0x100>;
 602                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 603                 clocks = <&cru HCLK_USBHOST0>;
 604                 clock-names = "usbhost";
 605                 phys = <&usbphy1>;
 606                 phy-names = "usb";
 607                 status = "disabled";
 608         };
 609
 610         /* NOTE: ohci@ff520000 doesn't actually work on hardware */
 611
 612         usb_host1: usb@ff540000 {
 613                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 614                                 "snps,dwc2";
 615                 reg = <0x0 0xff540000 0x0 0x40000>;
 616                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 617                 clocks = <&cru HCLK_USBHOST1>;
 618                 clock-names = "otg";
 619                 dr_mode = "host";
 620                 phys = <&usbphy2>;
 621                 phy-names = "usb2-phy";
 622                 snps,reset-phy-on-wake;
 623                 status = "disabled";
 624         };
 625
 626         usb_otg: usb@ff580000 {
 627                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 628                                 "snps,dwc2";
 629                 reg = <0x0 0xff580000 0x0 0x40000>;
 630                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 631                 clocks = <&cru HCLK_OTG0>;
 632                 clock-names = "otg";
 633                 dr_mode = "otg";
 634                 g-np-tx-fifo-size = <16>;
 635                 g-rx-fifo-size = <275>;
 636                 g-tx-fifo-size = <256 128 128 64 64 32>;
 637                 phys = <&usbphy0>;
 638                 phy-names = "usb2-phy";
 639                 status = "disabled";
 640         };
 641
 642         usb_hsic: usb@ff5c0000 {
 643                 compatible = "generic-ehci";
 644                 reg = <0x0 0xff5c0000 0x0 0x100>;
 645                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 646                 clocks = <&cru HCLK_HSIC>;
 647                 clock-names = "usbhost";
 648                 status = "disabled";
 649         };
 650
 651         i2c0: i2c@ff650000 {
 652                 compatible = "rockchip,rk3288-i2c";
 653                 reg = <0x0 0xff650000 0x0 0x1000>;
 654                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 655                 #address-cells = <1>;
 656                 #size-cells = <0>;
 657                 clock-names = "i2c";
 658                 clocks = <&cru PCLK_I2C0>;
 659                 pinctrl-names = "default";
 660                 pinctrl-0 = <&i2c0_xfer>;
 661                 status = "disabled";
 662         };
 663
 664         i2c2: i2c@ff660000 {
 665                 compatible = "rockchip,rk3288-i2c";
 666                 reg = <0x0 0xff660000 0x0 0x1000>;
 667                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 668                 #address-cells = <1>;
 669                 #size-cells = <0>;
 670                 clock-names = "i2c";
 671                 clocks = <&cru PCLK_I2C2>;
 672                 pinctrl-names = "default";
 673                 pinctrl-0 = <&i2c2_xfer>;
 674                 status = "disabled";
 675         };
 676
 677         pwm0: pwm@ff680000 {
 678                 compatible = "rockchip,rk3288-pwm";
 679                 reg = <0x0 0xff680000 0x0 0x10>;
 680                 #pwm-cells = <3>;
 681                 pinctrl-names = "default";
 682                 pinctrl-0 = <&pwm0_pin>;
 683                 clocks = <&cru PCLK_RKPWM>;
 684                 clock-names = "pwm";
 685                 status = "disabled";
 686         };
 687
 688         pwm1: pwm@ff680010 {
 689                 compatible = "rockchip,rk3288-pwm";
 690                 reg = <0x0 0xff680010 0x0 0x10>;
 691                 #pwm-cells = <3>;
 692                 pinctrl-names = "default";
 693                 pinctrl-0 = <&pwm1_pin>;
 694                 clocks = <&cru PCLK_RKPWM>;
 695                 clock-names = "pwm";
 696                 status = "disabled";
 697         };
 698
 699         pwm2: pwm@ff680020 {
 700                 compatible = "rockchip,rk3288-pwm";
 701                 reg = <0x0 0xff680020 0x0 0x10>;
 702                 #pwm-cells = <3>;
 703                 pinctrl-names = "default";
 704                 pinctrl-0 = <&pwm2_pin>;
 705                 clocks = <&cru PCLK_RKPWM>;
 706                 clock-names = "pwm";
 707                 status = "disabled";
 708         };
 709
 710         pwm3: pwm@ff680030 {
 711                 compatible = "rockchip,rk3288-pwm";
 712                 reg = <0x0 0xff680030 0x0 0x10>;
 713                 #pwm-cells = <3>;
 714                 pinctrl-names = "default";
 715                 pinctrl-0 = <&pwm3_pin>;
 716                 clocks = <&cru PCLK_RKPWM>;
 717                 clock-names = "pwm";
 718                 status = "disabled";
 719         };
 720
 721         bus_intmem@ff700000 {
 722                 compatible = "mmio-sram";
 723                 reg = <0x0 0xff700000 0x0 0x18000>;
 724                 #address-cells = <1>;
 725                 #size-cells = <1>;
 726                 ranges = <0 0x0 0xff700000 0x18000>;
 727                 smp-sram@0 {
 728                         compatible = "rockchip,rk3066-smp-sram";
 729                         reg = <0x00 0x10>;
 730                 };
 731         };
 732
 733         sram@ff720000 {
 734                 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
 735                 reg = <0x0 0xff720000 0x0 0x1000>;
 736         };
 737
 738         pmu: power-management@ff730000 {
 739                 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
 740                 reg = <0x0 0xff730000 0x0 0x100>;
 741
 742                 power: power-controller {
 743                         compatible = "rockchip,rk3288-power-controller";
 744                         #power-domain-cells = <1>;
 745                         #address-cells = <1>;
 746                         #size-cells = <0>;
 747
 748                         assigned-clocks = <&cru SCLK_EDP_24M>;
 749                         assigned-clock-parents = <&xin24m>;
 750
 751                         /*
 752                          * Note: Although SCLK_* are the working clocks
 753                          * of device without including on the NOC, needed for
 754                          * synchronous reset.
 755                          *
 756                          * The clocks on the which NOC:
 757                          * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 758                          * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
 759                          * ACLK_RGA is on ACLK_RGA_NIU.
 760                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 761                          *
 762                          * Which clock are device clocks:
 763                          *      clocks          devices
 764                          *      *_IEP           IEP:Image Enhancement Processor
 765                          *      *_ISP           ISP:Image Signal Processing
 766                          *      *_VIP           VIP:Video Input Processor
 767                          *      *_VOP*          VOP:Visual Output Processor
 768                          *      *_RGA           RGA
 769                          *      *_EDP*          EDP
 770                          *      *_LVDS_*        LVDS
 771                          *      *_HDMI          HDMI
 772                          *      *_MIPI_*        MIPI
 773                          */
 774                         power-domain@RK3288_PD_VIO {
 775                                 reg = <RK3288_PD_VIO>;
 776                                 clocks = <&cru ACLK_IEP>,
 777                                          <&cru ACLK_ISP>,
 778                                          <&cru ACLK_RGA>,
 779                                          <&cru ACLK_VIP>,
 780                                          <&cru ACLK_VOP0>,
 781                                          <&cru ACLK_VOP1>,
 782                                          <&cru DCLK_VOP0>,
 783                                          <&cru DCLK_VOP1>,
 784                                          <&cru HCLK_IEP>,
 785                                          <&cru HCLK_ISP>,
 786                                          <&cru HCLK_RGA>,
 787                                          <&cru HCLK_VIP>,
 788                                          <&cru HCLK_VOP0>,
 789                                          <&cru HCLK_VOP1>,
 790                                          <&cru PCLK_EDP_CTRL>,
 791                                          <&cru PCLK_HDMI_CTRL>,
 792                                          <&cru PCLK_LVDS_PHY>,
 793                                          <&cru PCLK_MIPI_CSI>,
 794                                          <&cru PCLK_MIPI_DSI0>,
 795                                          <&cru PCLK_MIPI_DSI1>,
 796                                          <&cru SCLK_EDP_24M>,
 797                                          <&cru SCLK_EDP>,
 798                                          <&cru SCLK_ISP_JPE>,
 799                                          <&cru SCLK_ISP>,
 800                                          <&cru SCLK_RGA>;
 801                                 pm_qos = <&qos_vio0_iep>,
 802                                          <&qos_vio1_vop>,
 803                                          <&qos_vio1_isp_w0>,
 804                                          <&qos_vio1_isp_w1>,
 805                                          <&qos_vio0_vop>,
 806                                          <&qos_vio0_vip>,
 807                                          <&qos_vio2_rga_r>,
 808                                          <&qos_vio2_rga_w>,
 809                                          <&qos_vio1_isp_r>;
 810                         };
 811
 812                         /*
 813                          * Note: The following 3 are HEVC(H.265) clocks,
 814                          * and on the ACLK_HEVC_NIU (NOC).
 815                          */
 816                         power-domain@RK3288_PD_HEVC {
 817                                 reg = <RK3288_PD_HEVC>;
 818                                 clocks = <&cru ACLK_HEVC>,
 819                                          <&cru SCLK_HEVC_CABAC>,
 820                                          <&cru SCLK_HEVC_CORE>;
 821                                 pm_qos = <&qos_hevc_r>,
 822                                          <&qos_hevc_w>;
 823                         };
 824
 825                         /*
 826                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
 827                          * (video endecoder & decoder) clocks that on the
 828                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
 829                          */
 830                         power-domain@RK3288_PD_VIDEO {
 831                                 reg = <RK3288_PD_VIDEO>;
 832                                 clocks = <&cru ACLK_VCODEC>,
 833                                          <&cru HCLK_VCODEC>;
 834                                 pm_qos = <&qos_video>;
 835                         };
 836
 837                         /*
 838                          * Note: ACLK_GPU is the GPU clock,
 839                          * and on the ACLK_GPU_NIU (NOC).
 840                          */
 841                         power-domain@RK3288_PD_GPU {
 842                                 reg = <RK3288_PD_GPU>;
 843                                 clocks = <&cru ACLK_GPU>;
 844                                 pm_qos = <&qos_gpu_r>,
 845                                          <&qos_gpu_w>;
 846                         };
 847                 };
 848
 849                 reboot-mode {
 850                         compatible = "syscon-reboot-mode";
 851                         offset = <0x94>;
 852                         mode-normal = <BOOT_NORMAL>;
 853                         mode-recovery = <BOOT_RECOVERY>;
 854                         mode-bootloader = <BOOT_FASTBOOT>;
 855                         mode-loader = <BOOT_BL_DOWNLOAD>;
 856                 };
 857         };
 858
 859         sgrf: syscon@ff740000 {
 860                 compatible = "rockchip,rk3288-sgrf", "syscon";
 861                 reg = <0x0 0xff740000 0x0 0x1000>;
 862         };
 863
 864         cru: clock-controller@ff760000 {
 865                 compatible = "rockchip,rk3288-cru";
 866                 reg = <0x0 0xff760000 0x0 0x1000>;
 867                 rockchip,grf = <&grf>;
 868                 #clock-cells = <1>;
 869                 #reset-cells = <1>;
 870                 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 871                                   <&cru PLL_NPLL>, <&cru ACLK_CPU>,
 872                                   <&cru HCLK_CPU>, <&cru PCLK_CPU>,
 873                                   <&cru ACLK_PERI>, <&cru HCLK_PERI>,
 874                                   <&cru PCLK_PERI>;
 875                 assigned-clock-rates = <594000000>, <400000000>,
 876                                        <500000000>, <300000000>,
 877                                        <150000000>, <75000000>,
 878                                        <300000000>, <150000000>,
 879                                        <75000000>;
 880         };
 881
 882         grf: syscon@ff770000 {
 883                 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
 884                 reg = <0x0 0xff770000 0x0 0x1000>;
 885
 886                 edp_phy: edp-phy {
 887                         compatible = "rockchip,rk3288-dp-phy";
 888                         clocks = <&cru SCLK_EDP_24M>;
 889                         clock-names = "24m";
 890                         #phy-cells = <0>;
 891                         status = "disabled";
 892                 };
 893
 894                 io_domains: io-domains {
 895                         compatible = "rockchip,rk3288-io-voltage-domain";
 896                         status = "disabled";
 897                 };
 898
 899                 usbphy: usbphy {
 900                         compatible = "rockchip,rk3288-usb-phy";
 901                         #address-cells = <1>;
 902                         #size-cells = <0>;
 903                         status = "disabled";
 904
 905                         usbphy0: usb-phy@320 {
 906                                 #phy-cells = <0>;
 907                                 reg = <0x320>;
 908                                 clocks = <&cru SCLK_OTGPHY0>;
 909                                 clock-names = "phyclk";
 910                                 #clock-cells = <0>;
 911                                 resets = <&cru SRST_USBOTG_PHY>;
 912                                 reset-names = "phy-reset";
 913                         };
 914
 915                         usbphy1: usb-phy@334 {
 916                                 #phy-cells = <0>;
 917                                 reg = <0x334>;
 918                                 clocks = <&cru SCLK_OTGPHY1>;
 919                                 clock-names = "phyclk";
 920                                 #clock-cells = <0>;
 921                                 resets = <&cru SRST_USBHOST0_PHY>;
 922                                 reset-names = "phy-reset";
 923                         };
 924
 925                         usbphy2: usb-phy@348 {
 926                                 #phy-cells = <0>;
 927                                 reg = <0x348>;
 928                                 clocks = <&cru SCLK_OTGPHY2>;
 929                                 clock-names = "phyclk";
 930                                 #clock-cells = <0>;
 931                                 resets = <&cru SRST_USBHOST1_PHY>;
 932                                 reset-names = "phy-reset";
 933                         };
 934                 };
 935         };
 936
 937         wdt: watchdog@ff800000 {
 938                 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
 939                 reg = <0x0 0xff800000 0x0 0x100>;
 940                 clocks = <&cru PCLK_WDT>;
 941                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 942                 status = "disabled";
 943         };
 944
 945         spdif: sound@ff8b0000 {
 946                 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
 947                 reg = <0x0 0xff8b0000 0x0 0x10000>;
 948                 #sound-dai-cells = <0>;
 949                 clock-names = "hclk", "mclk";
 950                 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
 951                 dmas = <&dmac_bus_s 3>;
 952                 dma-names = "tx";
 953                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 954                 pinctrl-names = "default";
 955                 pinctrl-0 = <&spdif_tx>;
 956                 rockchip,grf = <&grf>;
 957                 status = "disabled";
 958         };
 959
 960         i2s: i2s@ff890000 {
 961                 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
 962                 reg = <0x0 0xff890000 0x0 0x10000>;
 963                 #sound-dai-cells = <0>;
 964                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 965                 #address-cells = <1>;
 966                 #size-cells = <0>;
 967                 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
 968                 dma-names = "tx", "rx";
 969                 clock-names = "i2s_hclk", "i2s_clk";
 970                 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
 971                 pinctrl-names = "default";
 972                 pinctrl-0 = <&i2s0_bus>;
 973                 rockchip,playback-channels = <8>;
 974                 rockchip,capture-channels = <2>;
 975                 status = "disabled";
 976         };
 977
 978         crypto: crypto@ff8a0000 {
 979                 compatible = "rockchip,rk3288-crypto";
 980                 reg = <0x0 0xff8a0000 0x0 0x4000>;
 981                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 982                 clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>,
 983                          <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>;
 984                 clock-names = "aclk", "hclk", "sclk", "apb_pclk";
 985                 resets = <&cru SRST_CRYPTO>;
 986                 reset-names = "crypto-rst";
 987                 status = "okay";
 988         };
 989
 990         iep_mmu: iommu@ff900800 {
 991                 compatible = "rockchip,iommu";
 992                 reg = <0x0 0xff900800 0x0 0x40>;
 993                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 994                 interrupt-names = "iep_mmu";
 995                 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
 996                 clock-names = "aclk", "iface";
 997                 #iommu-cells = <0>;
 998                 status = "disabled";
 999         };
1000
1001         isp_mmu: iommu@ff914000 {
1002                 compatible = "rockchip,iommu";
1003                 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
1004                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1005                 interrupt-names = "isp_mmu";
1006                 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
1007                 clock-names = "aclk", "iface";
1008                 #iommu-cells = <0>;
1009                 rockchip,disable-mmu-reset;
1010                 status = "disabled";
1011         };
1012
1013         rga: rga@ff920000 {
1014                 compatible = "rockchip,rk3288-rga";
1015                 reg = <0x0 0xff920000 0x0 0x180>;
1016                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1017                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
1018                 clock-names = "aclk", "hclk", "sclk";
1019                 power-domains = <&power RK3288_PD_VIO>;
1020                 resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>;
1021                 reset-names = "core", "axi", "ahb";
1022         };
1023
1024         vopb: vop@ff930000 {
1025                 compatible = "rockchip,rk3288-vop";
1026                 reg = <0x0 0xff930000 0x0 0x19c>;
1027                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1028                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1029                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1030                 power-domains = <&power RK3288_PD_VIO>;
1031                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1032                 reset-names = "axi", "ahb", "dclk";
1033                 iommus = <&vopb_mmu>;
1034                 status = "disabled";
1035
1036                 vopb_out: port {
1037                         #address-cells = <1>;
1038                         #size-cells = <0>;
1039
1040                         vopb_out_hdmi: endpoint@0 {
1041                                 reg = <0>;
1042                                 remote-endpoint = <&hdmi_in_vopb>;
1043                         };
1044
1045                         vopb_out_edp: endpoint@1 {
1046                                 reg = <1>;
1047                                 remote-endpoint = <&edp_in_vopb>;
1048                         };
1049
1050                         vopb_out_mipi: endpoint@2 {
1051                                 reg = <2>;
1052                                 remote-endpoint = <&mipi_in_vopb>;
1053                         };
1054
1055                         vopb_out_lvds: endpoint@3 {
1056                                 reg = <3>;
1057                                 remote-endpoint = <&lvds_in_vopb>;
1058                         };
1059                 };
1060         };
1061
1062         vopb_mmu: iommu@ff930300 {
1063                 compatible = "rockchip,iommu";
1064                 reg = <0x0 0xff930300 0x0 0x100>;
1065                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1066                 interrupt-names = "vopb_mmu";
1067                 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1068                 clock-names = "aclk", "iface";
1069                 power-domains = <&power RK3288_PD_VIO>;
1070                 #iommu-cells = <0>;
1071                 status = "disabled";
1072         };
1073
1074         vopl: vop@ff940000 {
1075                 compatible = "rockchip,rk3288-vop";
1076                 reg = <0x0 0xff940000 0x0 0x19c>;
1077                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1078                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1079                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1080                 power-domains = <&power RK3288_PD_VIO>;
1081                 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
1082                 reset-names = "axi", "ahb", "dclk";
1083                 iommus = <&vopl_mmu>;
1084                 status = "disabled";
1085
1086                 vopl_out: port {
1087                         #address-cells = <1>;
1088                         #size-cells = <0>;
1089
1090                         vopl_out_hdmi: endpoint@0 {
1091                                 reg = <0>;
1092                                 remote-endpoint = <&hdmi_in_vopl>;
1093                         };
1094
1095                         vopl_out_edp: endpoint@1 {
1096                                 reg = <1>;
1097                                 remote-endpoint = <&edp_in_vopl>;
1098                         };
1099
1100                         vopl_out_mipi: endpoint@2 {
1101                                 reg = <2>;
1102                                 remote-endpoint = <&mipi_in_vopl>;
1103                         };
1104
1105                         vopl_out_lvds: endpoint@3 {
1106                                 reg = <3>;
1107                                 remote-endpoint = <&lvds_in_vopl>;
1108                         };
1109                 };
1110         };
1111
1112         vopl_mmu: iommu@ff940300 {
1113                 compatible = "rockchip,iommu";
1114                 reg = <0x0 0xff940300 0x0 0x100>;
1115                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1116                 interrupt-names = "vopl_mmu";
1117                 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1118                 clock-names = "aclk", "iface";
1119                 power-domains = <&power RK3288_PD_VIO>;
1120                 #iommu-cells = <0>;
1121                 status = "disabled";
1122         };
1123
1124         mipi_dsi: mipi@ff960000 {
1125                 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
1126                 reg = <0x0 0xff960000 0x0 0x4000>;
1127                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1128                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
1129                 clock-names = "ref", "pclk";
1130                 power-domains = <&power RK3288_PD_VIO>;
1131                 rockchip,grf = <&grf>;
1132                 status = "disabled";
1133
1134                 ports {
1135                         mipi_in: port {
1136                                 #address-cells = <1>;
1137                                 #size-cells = <0>;
1138                                 mipi_in_vopb: endpoint@0 {
1139                                         reg = <0>;
1140                                         remote-endpoint = <&vopb_out_mipi>;
1141                                 };
1142                                 mipi_in_vopl: endpoint@1 {
1143                                         reg = <1>;
1144                                         remote-endpoint = <&vopl_out_mipi>;
1145                                 };
1146                         };
1147                 };
1148         };
1149
1150         lvds: lvds@ff96c000 {
1151                 compatible = "rockchip,rk3288-lvds";
1152                 reg = <0x0 0xff96c000 0x0 0x4000>;
1153                 clocks = <&cru PCLK_LVDS_PHY>;
1154                 clock-names = "pclk_lvds";
1155                 pinctrl-names = "lcdc";
1156                 pinctrl-0 = <&lcdc_ctl>;
1157                 power-domains = <&power RK3288_PD_VIO>;
1158                 rockchip,grf = <&grf>;
1159                 status = "disabled";
1160
1161                 ports {
1162                         #address-cells = <1>;
1163                         #size-cells = <0>;
1164
1165                         lvds_in: port@0 {
1166                                 reg = <0>;
1167
1168                                 #address-cells = <1>;
1169                                 #size-cells = <0>;
1170
1171                                 lvds_in_vopb: endpoint@0 {
1172                                         reg = <0>;
1173                                         remote-endpoint = <&vopb_out_lvds>;
1174                                 };
1175                                 lvds_in_vopl: endpoint@1 {
1176                                         reg = <1>;
1177                                         remote-endpoint = <&vopl_out_lvds>;
1178                                 };
1179                         };
1180                 };
1181         };
1182
1183         edp: dp@ff970000 {
1184                 compatible = "rockchip,rk3288-dp";
1185                 reg = <0x0 0xff970000 0x0 0x4000>;
1186                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1187                 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1188                 clock-names = "dp", "pclk";
1189                 phys = <&edp_phy>;
1190                 phy-names = "dp";
1191                 power-domains = <&power RK3288_PD_VIO>;
1192                 resets = <&cru SRST_EDP>;
1193                 reset-names = "dp";
1194                 rockchip,grf = <&grf>;
1195                 status = "disabled";
1196
1197                 ports {
1198                         #address-cells = <1>;
1199                         #size-cells = <0>;
1200                         edp_in: port@0 {
1201                                 reg = <0>;
1202                                 #address-cells = <1>;
1203                                 #size-cells = <0>;
1204                                 edp_in_vopb: endpoint@0 {
1205                                         reg = <0>;
1206                                         remote-endpoint = <&vopb_out_edp>;
1207                                 };
1208                                 edp_in_vopl: endpoint@1 {
1209                                         reg = <1>;
1210                                         remote-endpoint = <&vopl_out_edp>;
1211                                 };
1212                         };
1213                 };
1214         };
1215
1216         hdmi: hdmi@ff980000 {
1217                 compatible = "rockchip,rk3288-dw-hdmi";
1218                 reg = <0x0 0xff980000 0x0 0x20000>;
1219                 reg-io-width = <4>;
1220                 #sound-dai-cells = <0>;
1221                 rockchip,grf = <&grf>;
1222                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1223                 clocks = <&cru  PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>;
1224                 clock-names = "iahb", "isfr", "cec";
1225                 power-domains = <&power RK3288_PD_VIO>;
1226                 status = "disabled";
1227
1228                 ports {
1229                         hdmi_in: port {
1230                                 #address-cells = <1>;
1231                                 #size-cells = <0>;
1232                                 hdmi_in_vopb: endpoint@0 {
1233                                         reg = <0>;
1234                                         remote-endpoint = <&vopb_out_hdmi>;
1235                                 };
1236                                 hdmi_in_vopl: endpoint@1 {
1237                                         reg = <1>;
1238                                         remote-endpoint = <&vopl_out_hdmi>;
1239                                 };
1240                         };
1241                 };
1242         };
1243
1244         vpu: video-codec@ff9a0000 {
1245                 compatible = "rockchip,rk3288-vpu";
1246                 reg = <0x0 0xff9a0000 0x0 0x800>;
1247                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1248                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1249                 interrupt-names = "vepu", "vdpu";
1250                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1251                 clock-names = "aclk", "hclk";
1252                 iommus = <&vpu_mmu>;
1253                 power-domains = <&power RK3288_PD_VIDEO>;
1254         };
1255
1256         vpu_mmu: iommu@ff9a0800 {
1257                 compatible = "rockchip,iommu";
1258                 reg = <0x0 0xff9a0800 0x0 0x100>;
1259                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1260                 interrupt-names = "vpu_mmu";
1261                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1262                 clock-names = "aclk", "iface";
1263                 #iommu-cells = <0>;
1264                 power-domains = <&power RK3288_PD_VIDEO>;
1265         };
1266
1267         hevc_mmu: iommu@ff9c0440 {
1268                 compatible = "rockchip,iommu";
1269                 reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>;
1270                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1271                 interrupt-names = "hevc_mmu";
1272                 clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>;
1273                 clock-names = "aclk", "iface";
1274                 #iommu-cells = <0>;
1275                 status = "disabled";
1276         };
1277
1278         gpu: gpu@ffa30000 {
1279                 compatible = "rockchip,rk3288-mali", "arm,mali-t760";
1280                 reg = <0x0 0xffa30000 0x0 0x10000>;
1281                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1282                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1283                              <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1284                 interrupt-names = "job", "mmu", "gpu";
1285                 clocks = <&cru ACLK_GPU>;
1286                 operating-points-v2 = <&gpu_opp_table>;
1287                 #cooling-cells = <2>; /* min followed by max */
1288                 power-domains = <&power RK3288_PD_GPU>;
1289                 status = "disabled";
1290         };
1291
1292         gpu_opp_table: gpu-opp-table {
1293                 compatible = "operating-points-v2";
1294
1295                 opp-100000000 {
1296                         opp-hz = /bits/ 64 <100000000>;
1297                         opp-microvolt = <950000>;
1298                 };
1299                 opp-200000000 {
1300                         opp-hz = /bits/ 64 <200000000>;
1301                         opp-microvolt = <950000>;
1302                 };
1303                 opp-300000000 {
1304                         opp-hz = /bits/ 64 <300000000>;
1305                         opp-microvolt = <1000000>;
1306                 };
1307                 opp-400000000 {
1308                         opp-hz = /bits/ 64 <400000000>;
1309                         opp-microvolt = <1100000>;
1310                 };
1311                 opp-600000000 {
1312                         opp-hz = /bits/ 64 <600000000>;
1313                         opp-microvolt = <1250000>;
1314                 };
1315         };
1316
1317         qos_gpu_r: qos@ffaa0000 {
1318                 compatible = "syscon";
1319                 reg = <0x0 0xffaa0000 0x0 0x20>;
1320         };
1321
1322         qos_gpu_w: qos@ffaa0080 {
1323                 compatible = "syscon";
1324                 reg = <0x0 0xffaa0080 0x0 0x20>;
1325         };
1326
1327         qos_vio1_vop: qos@ffad0000 {
1328                 compatible = "syscon";
1329                 reg = <0x0 0xffad0000 0x0 0x20>;
1330         };
1331
1332         qos_vio1_isp_w0: qos@ffad0100 {
1333                 compatible = "syscon";
1334                 reg = <0x0 0xffad0100 0x0 0x20>;
1335         };
1336
1337         qos_vio1_isp_w1: qos@ffad0180 {
1338                 compatible = "syscon";
1339                 reg = <0x0 0xffad0180 0x0 0x20>;
1340         };
1341
1342         qos_vio0_vop: qos@ffad0400 {
1343                 compatible = "syscon";
1344                 reg = <0x0 0xffad0400 0x0 0x20>;
1345         };
1346
1347         qos_vio0_vip: qos@ffad0480 {
1348                 compatible = "syscon";
1349                 reg = <0x0 0xffad0480 0x0 0x20>;
1350         };
1351
1352         qos_vio0_iep: qos@ffad0500 {
1353                 compatible = "syscon";
1354                 reg = <0x0 0xffad0500 0x0 0x20>;
1355         };
1356
1357         qos_vio2_rga_r: qos@ffad0800 {
1358                 compatible = "syscon";
1359                 reg = <0x0 0xffad0800 0x0 0x20>;
1360         };
1361
1362         qos_vio2_rga_w: qos@ffad0880 {
1363                 compatible = "syscon";
1364                 reg = <0x0 0xffad0880 0x0 0x20>;
1365         };
1366
1367         qos_vio1_isp_r: qos@ffad0900 {
1368                 compatible = "syscon";
1369                 reg = <0x0 0xffad0900 0x0 0x20>;
1370         };
1371
1372         qos_video: qos@ffae0000 {
1373                 compatible = "syscon";
1374                 reg = <0x0 0xffae0000 0x0 0x20>;
1375         };
1376
1377         qos_hevc_r: qos@ffaf0000 {
1378                 compatible = "syscon";
1379                 reg = <0x0 0xffaf0000 0x0 0x20>;
1380         };
1381
1382         qos_hevc_w: qos@ffaf0080 {
1383                 compatible = "syscon";
1384                 reg = <0x0 0xffaf0080 0x0 0x20>;
1385         };
1386
1387         efuse: efuse@ffb40000 {
1388                 compatible = "rockchip,rk3288-efuse";
1389                 reg = <0x0 0xffb40000 0x0 0x20>;
1390                 #address-cells = <1>;
1391                 #size-cells = <1>;
1392                 clocks = <&cru PCLK_EFUSE256>;
1393                 clock-names = "pclk_efuse";
1394
1395                 cpu_leakage: cpu_leakage@17 {
1396                         reg = <0x17 0x1>;
1397                 };
1398         };
1399
1400         gic: interrupt-controller@ffc01000 {
1401                 compatible = "arm,gic-400";
1402                 interrupt-controller;
1403                 #interrupt-cells = <3>;
1404                 #address-cells = <0>;
1405
1406                 reg = <0x0 0xffc01000 0x0 0x1000>,
1407                       <0x0 0xffc02000 0x0 0x2000>,
1408                       <0x0 0xffc04000 0x0 0x2000>,
1409                       <0x0 0xffc06000 0x0 0x2000>;
1410                 interrupts = <GIC_PPI 9 0xf04>;
1411         };
1412
1413         pinctrl: pinctrl {
1414                 compatible = "rockchip,rk3288-pinctrl";
1415                 rockchip,grf = <&grf>;
1416                 rockchip,pmu = <&pmu>;
1417                 #address-cells = <2>;
1418                 #size-cells = <2>;
1419                 ranges;
1420
1421                 gpio0: gpio0@ff750000 {
1422                         compatible = "rockchip,gpio-bank";
1423                         reg = <0x0 0xff750000 0x0 0x100>;
1424                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1425                         clocks = <&cru PCLK_GPIO0>;
1426
1427                         gpio-controller;
1428                         #gpio-cells = <2>;
1429
1430                         interrupt-controller;
1431                         #interrupt-cells = <2>;
1432                 };
1433
1434                 gpio1: gpio1@ff780000 {
1435                         compatible = "rockchip,gpio-bank";
1436                         reg = <0x0 0xff780000 0x0 0x100>;
1437                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1438                         clocks = <&cru PCLK_GPIO1>;
1439
1440                         gpio-controller;
1441                         #gpio-cells = <2>;
1442
1443                         interrupt-controller;
1444                         #interrupt-cells = <2>;
1445                 };
1446
1447                 gpio2: gpio2@ff790000 {
1448                         compatible = "rockchip,gpio-bank";
1449                         reg = <0x0 0xff790000 0x0 0x100>;
1450                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1451                         clocks = <&cru PCLK_GPIO2>;
1452
1453                         gpio-controller;
1454                         #gpio-cells = <2>;
1455
1456                         interrupt-controller;
1457                         #interrupt-cells = <2>;
1458                 };
1459
1460                 gpio3: gpio3@ff7a0000 {
1461                         compatible = "rockchip,gpio-bank";
1462                         reg = <0x0 0xff7a0000 0x0 0x100>;
1463                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1464                         clocks = <&cru PCLK_GPIO3>;
1465
1466                         gpio-controller;
1467                         #gpio-cells = <2>;
1468
1469                         interrupt-controller;
1470                         #interrupt-cells = <2>;
1471                 };
1472
1473                 gpio4: gpio4@ff7b0000 {
1474                         compatible = "rockchip,gpio-bank";
1475                         reg = <0x0 0xff7b0000 0x0 0x100>;
1476                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1477                         clocks = <&cru PCLK_GPIO4>;
1478
1479                         gpio-controller;
1480                         #gpio-cells = <2>;
1481
1482                         interrupt-controller;
1483                         #interrupt-cells = <2>;
1484                 };
1485
1486                 gpio5: gpio5@ff7c0000 {
1487                         compatible = "rockchip,gpio-bank";
1488                         reg = <0x0 0xff7c0000 0x0 0x100>;
1489                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1490                         clocks = <&cru PCLK_GPIO5>;
1491
1492                         gpio-controller;
1493                         #gpio-cells = <2>;
1494
1495                         interrupt-controller;
1496                         #interrupt-cells = <2>;
1497                 };
1498
1499                 gpio6: gpio6@ff7d0000 {
1500                         compatible = "rockchip,gpio-bank";
1501                         reg = <0x0 0xff7d0000 0x0 0x100>;
1502                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1503                         clocks = <&cru PCLK_GPIO6>;
1504
1505                         gpio-controller;
1506                         #gpio-cells = <2>;
1507
1508                         interrupt-controller;
1509                         #interrupt-cells = <2>;
1510                 };
1511
1512                 gpio7: gpio7@ff7e0000 {
1513                         compatible = "rockchip,gpio-bank";
1514                         reg = <0x0 0xff7e0000 0x0 0x100>;
1515                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1516                         clocks = <&cru PCLK_GPIO7>;
1517
1518                         gpio-controller;
1519                         #gpio-cells = <2>;
1520
1521                         interrupt-controller;
1522                         #interrupt-cells = <2>;
1523                 };
1524
1525                 gpio8: gpio8@ff7f0000 {
1526                         compatible = "rockchip,gpio-bank";
1527                         reg = <0x0 0xff7f0000 0x0 0x100>;
1528                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1529                         clocks = <&cru PCLK_GPIO8>;
1530
1531                         gpio-controller;
1532                         #gpio-cells = <2>;
1533
1534                         interrupt-controller;
1535                         #interrupt-cells = <2>;
1536                 };
1537
1538                 hdmi {
1539                         hdmi_cec_c0: hdmi-cec-c0 {
1540                                 rockchip,pins = <7 RK_PC0 2 &pcfg_pull_none>;
1541                         };
1542
1543                         hdmi_cec_c7: hdmi-cec-c7 {
1544                                 rockchip,pins = <7 RK_PC7 4 &pcfg_pull_none>;
1545                         };
1546
1547                         hdmi_ddc: hdmi-ddc {
1548                                 rockchip,pins = <7 RK_PC3 2 &pcfg_pull_none>,
1549                                                 <7 RK_PC4 2 &pcfg_pull_none>;
1550                         };
1551
1552                         hdmi_ddc_unwedge: hdmi-ddc-unwedge {
1553                                 rockchip,pins = <7 RK_PC3 RK_FUNC_GPIO &pcfg_output_low>,
1554                                                 <7 RK_PC4 2 &pcfg_pull_none>;
1555                         };
1556                 };
1557
1558                 pcfg_output_low: pcfg-output-low {
1559                         output-low;
1560                 };
1561
1562                 pcfg_pull_up: pcfg-pull-up {
1563                         bias-pull-up;
1564                 };
1565
1566                 pcfg_pull_down: pcfg-pull-down {
1567                         bias-pull-down;
1568                 };
1569
1570                 pcfg_pull_none: pcfg-pull-none {
1571                         bias-disable;
1572                 };
1573
1574                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1575                         bias-disable;
1576                         drive-strength = <12>;
1577                 };
1578
1579                 suspend {
1580                         global_pwroff: global-pwroff {
1581                                 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>;
1582                         };
1583
1584                         ddrio_pwroff: ddrio-pwroff {
1585                                 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>;
1586                         };
1587
1588                         ddr0_retention: ddr0-retention {
1589                                 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_up>;
1590                         };
1591
1592                         ddr1_retention: ddr1-retention {
1593                                 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_up>;
1594                         };
1595                 };
1596
1597                 edp {
1598                         edp_hpd: edp-hpd {
1599                                 rockchip,pins = <7 RK_PB3 2 &pcfg_pull_down>;
1600                         };
1601                 };
1602
1603                 i2c0 {
1604                         i2c0_xfer: i2c0-xfer {
1605                                 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>,
1606                                                 <0 RK_PC0 1 &pcfg_pull_none>;
1607                         };
1608                 };
1609
1610                 i2c1 {
1611                         i2c1_xfer: i2c1-xfer {
1612                                 rockchip,pins = <8 RK_PA4 1 &pcfg_pull_none>,
1613                                                 <8 RK_PA5 1 &pcfg_pull_none>;
1614                         };
1615                 };
1616
1617                 i2c2 {
1618                         i2c2_xfer: i2c2-xfer {
1619                                 rockchip,pins = <6 RK_PB1 1 &pcfg_pull_none>,
1620                                                 <6 RK_PB2 1 &pcfg_pull_none>;
1621                         };
1622                 };
1623
1624                 i2c3 {
1625                         i2c3_xfer: i2c3-xfer {
1626                                 rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>,
1627                                                 <2 RK_PC1 1 &pcfg_pull_none>;
1628                         };
1629                 };
1630
1631                 i2c4 {
1632                         i2c4_xfer: i2c4-xfer {
1633                                 rockchip,pins = <7 RK_PC1 1 &pcfg_pull_none>,
1634                                                 <7 RK_PC2 1 &pcfg_pull_none>;
1635                         };
1636                 };
1637
1638                 i2c5 {
1639                         i2c5_xfer: i2c5-xfer {
1640                                 rockchip,pins = <7 RK_PC3 1 &pcfg_pull_none>,
1641                                                 <7 RK_PC4 1 &pcfg_pull_none>;
1642                         };
1643                 };
1644
1645                 i2s0 {
1646                         i2s0_bus: i2s0-bus {
1647                                 rockchip,pins = <6 RK_PA0 1 &pcfg_pull_none>,
1648                                                 <6 RK_PA1 1 &pcfg_pull_none>,
1649                                                 <6 RK_PA2 1 &pcfg_pull_none>,
1650                                                 <6 RK_PA3 1 &pcfg_pull_none>,
1651                                                 <6 RK_PA4 1 &pcfg_pull_none>,
1652                                                 <6 RK_PB0 1 &pcfg_pull_none>;
1653                         };
1654                 };
1655
1656                 lcdc {
1657                         lcdc_ctl: lcdc-ctl {
1658                                 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>,
1659                                                 <1 RK_PD1 1 &pcfg_pull_none>,
1660                                                 <1 RK_PD2 1 &pcfg_pull_none>,
1661                                                 <1 RK_PD3 1 &pcfg_pull_none>;
1662                         };
1663                 };
1664
1665                 sdmmc {
1666                         sdmmc_clk: sdmmc-clk {
1667                                 rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none>;
1668                         };
1669
1670                         sdmmc_cmd: sdmmc-cmd {
1671                                 rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up>;
1672                         };
1673
1674                         sdmmc_cd: sdmmc-cd {
1675                                 rockchip,pins = <6 RK_PC6 1 &pcfg_pull_up>;
1676                         };
1677
1678                         sdmmc_bus1: sdmmc-bus1 {
1679                                 rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up>;
1680                         };
1681
1682                         sdmmc_bus4: sdmmc-bus4 {
1683                                 rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up>,
1684                                                 <6 RK_PC1 1 &pcfg_pull_up>,
1685                                                 <6 RK_PC2 1 &pcfg_pull_up>,
1686                                                 <6 RK_PC3 1 &pcfg_pull_up>;
1687                         };
1688                 };
1689
1690                 sdio0 {
1691                         sdio0_bus1: sdio0-bus1 {
1692                                 rockchip,pins = <4 RK_PC4 1 &pcfg_pull_up>;
1693                         };
1694
1695                         sdio0_bus4: sdio0-bus4 {
1696                                 rockchip,pins = <4 RK_PC4 1 &pcfg_pull_up>,
1697                                                 <4 RK_PC5 1 &pcfg_pull_up>,
1698                                                 <4 RK_PC6 1 &pcfg_pull_up>,
1699                                                 <4 RK_PC7 1 &pcfg_pull_up>;
1700                         };
1701
1702                         sdio0_cmd: sdio0-cmd {
1703                                 rockchip,pins = <4 RK_PD0 1 &pcfg_pull_up>;
1704                         };
1705
1706                         sdio0_clk: sdio0-clk {
1707                                 rockchip,pins = <4 RK_PD1 1 &pcfg_pull_none>;
1708                         };
1709
1710                         sdio0_cd: sdio0-cd {
1711                                 rockchip,pins = <4 RK_PD2 1 &pcfg_pull_up>;
1712                         };
1713
1714                         sdio0_wp: sdio0-wp {
1715                                 rockchip,pins = <4 RK_PD3 1 &pcfg_pull_up>;
1716                         };
1717
1718                         sdio0_pwr: sdio0-pwr {
1719                                 rockchip,pins = <4 RK_PD4 1 &pcfg_pull_up>;
1720                         };
1721
1722                         sdio0_bkpwr: sdio0-bkpwr {
1723                                 rockchip,pins = <4 RK_PD5 1 &pcfg_pull_up>;
1724                         };
1725
1726                         sdio0_int: sdio0-int {
1727                                 rockchip,pins = <4 RK_PD6 1 &pcfg_pull_up>;
1728                         };
1729                 };
1730
1731                 sdio1 {
1732                         sdio1_bus1: sdio1-bus1 {
1733                                 rockchip,pins = <3 RK_PD0 4 &pcfg_pull_up>;
1734                         };
1735
1736                         sdio1_bus4: sdio1-bus4 {
1737                                 rockchip,pins = <3 RK_PD0 4 &pcfg_pull_up>,
1738                                                 <3 RK_PD1 4 &pcfg_pull_up>,
1739                                                 <3 RK_PD2 4 &pcfg_pull_up>,
1740                                                 <3 RK_PD3 4 &pcfg_pull_up>;
1741                         };
1742
1743                         sdio1_cd: sdio1-cd {
1744                                 rockchip,pins = <3 RK_PD4 4 &pcfg_pull_up>;
1745                         };
1746
1747                         sdio1_wp: sdio1-wp {
1748                                 rockchip,pins = <3 RK_PD5 4 &pcfg_pull_up>;
1749                         };
1750
1751                         sdio1_bkpwr: sdio1-bkpwr {
1752                                 rockchip,pins = <3 RK_PD6 4 &pcfg_pull_up>;
1753                         };
1754
1755                         sdio1_int: sdio1-int {
1756                                 rockchip,pins = <3 RK_PD7 4 &pcfg_pull_up>;
1757                         };
1758
1759                         sdio1_cmd: sdio1-cmd {
1760                                 rockchip,pins = <4 RK_PA6 4 &pcfg_pull_up>;
1761                         };
1762
1763                         sdio1_clk: sdio1-clk {
1764                                 rockchip,pins = <4 RK_PA7 4 &pcfg_pull_none>;
1765                         };
1766
1767                         sdio1_pwr: sdio1-pwr {
1768                                 rockchip,pins = <4 RK_PB1 4 &pcfg_pull_up>;
1769                         };
1770                 };
1771
1772                 emmc {
1773                         emmc_clk: emmc-clk {
1774                                 rockchip,pins = <3 RK_PC2 2 &pcfg_pull_none>;
1775                         };
1776
1777                         emmc_cmd: emmc-cmd {
1778                                 rockchip,pins = <3 RK_PC0 2 &pcfg_pull_up>;
1779                         };
1780
1781                         emmc_pwr: emmc-pwr {
1782                                 rockchip,pins = <3 RK_PB1 2 &pcfg_pull_up>;
1783                         };
1784
1785                         emmc_bus1: emmc-bus1 {
1786                                 rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>;
1787                         };
1788
1789                         emmc_bus4: emmc-bus4 {
1790                                 rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>,
1791                                                 <3 RK_PA1 2 &pcfg_pull_up>,
1792                                                 <3 RK_PA2 2 &pcfg_pull_up>,
1793                                                 <3 RK_PA3 2 &pcfg_pull_up>;
1794                         };
1795
1796                         emmc_bus8: emmc-bus8 {
1797                                 rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>,
1798                                                 <3 RK_PA1 2 &pcfg_pull_up>,
1799                                                 <3 RK_PA2 2 &pcfg_pull_up>,
1800                                                 <3 RK_PA3 2 &pcfg_pull_up>,
1801                                                 <3 RK_PA4 2 &pcfg_pull_up>,
1802                                                 <3 RK_PA5 2 &pcfg_pull_up>,
1803                                                 <3 RK_PA6 2 &pcfg_pull_up>,
1804                                                 <3 RK_PA7 2 &pcfg_pull_up>;
1805                         };
1806                 };
1807
1808                 spi0 {
1809                         spi0_clk: spi0-clk {
1810                                 rockchip,pins = <5 RK_PB4 1 &pcfg_pull_up>;
1811                         };
1812                         spi0_cs0: spi0-cs0 {
1813                                 rockchip,pins = <5 RK_PB5 1 &pcfg_pull_up>;
1814                         };
1815                         spi0_tx: spi0-tx {
1816                                 rockchip,pins = <5 RK_PB6 1 &pcfg_pull_up>;
1817                         };
1818                         spi0_rx: spi0-rx {
1819                                 rockchip,pins = <5 RK_PB7 1 &pcfg_pull_up>;
1820                         };
1821                         spi0_cs1: spi0-cs1 {
1822                                 rockchip,pins = <5 RK_PC0 1 &pcfg_pull_up>;
1823                         };
1824                 };
1825                 spi1 {
1826                         spi1_clk: spi1-clk {
1827                                 rockchip,pins = <7 RK_PB4 2 &pcfg_pull_up>;
1828                         };
1829                         spi1_cs0: spi1-cs0 {
1830                                 rockchip,pins = <7 RK_PB5 2 &pcfg_pull_up>;
1831                         };
1832                         spi1_rx: spi1-rx {
1833                                 rockchip,pins = <7 RK_PB6 2 &pcfg_pull_up>;
1834                         };
1835                         spi1_tx: spi1-tx {
1836                                 rockchip,pins = <7 RK_PB7 2 &pcfg_pull_up>;
1837                         };
1838                 };
1839
1840                 spi2 {
1841                         spi2_cs1: spi2-cs1 {
1842                                 rockchip,pins = <8 RK_PA3 1 &pcfg_pull_up>;
1843                         };
1844                         spi2_clk: spi2-clk {
1845                                 rockchip,pins = <8 RK_PA6 1 &pcfg_pull_up>;
1846                         };
1847                         spi2_cs0: spi2-cs0 {
1848                                 rockchip,pins = <8 RK_PA7 1 &pcfg_pull_up>;
1849                         };
1850                         spi2_rx: spi2-rx {
1851                                 rockchip,pins = <8 RK_PB0 1 &pcfg_pull_up>;
1852                         };
1853                         spi2_tx: spi2-tx {
1854                                 rockchip,pins = <8 RK_PB1 1 &pcfg_pull_up>;
1855                         };
1856                 };
1857
1858                 uart0 {
1859                         uart0_xfer: uart0-xfer {
1860                                 rockchip,pins = <4 RK_PC0 1 &pcfg_pull_up>,
1861                                                 <4 RK_PC1 1 &pcfg_pull_none>;
1862                         };
1863
1864                         uart0_cts: uart0-cts {
1865                                 rockchip,pins = <4 RK_PC2 1 &pcfg_pull_up>;
1866                         };
1867
1868                         uart0_rts: uart0-rts {
1869                                 rockchip,pins = <4 RK_PC3 1 &pcfg_pull_none>;
1870                         };
1871                 };
1872
1873                 uart1 {
1874                         uart1_xfer: uart1-xfer {
1875                                 rockchip,pins = <5 RK_PB0 1 &pcfg_pull_up>,
1876                                                 <5 RK_PB1 1 &pcfg_pull_none>;
1877                         };
1878
1879                         uart1_cts: uart1-cts {
1880                                 rockchip,pins = <5 RK_PB2 1 &pcfg_pull_up>;
1881                         };
1882
1883                         uart1_rts: uart1-rts {
1884                                 rockchip,pins = <5 RK_PB3 1 &pcfg_pull_none>;
1885                         };
1886                 };
1887
1888                 uart2 {
1889                         uart2_xfer: uart2-xfer {
1890                                 rockchip,pins = <7 RK_PC6 1 &pcfg_pull_up>,
1891                                                 <7 RK_PC7 1 &pcfg_pull_none>;
1892                         };
1893                         /* no rts / cts for uart2 */
1894                 };
1895
1896                 uart3 {
1897                         uart3_xfer: uart3-xfer {
1898                                 rockchip,pins = <7 RK_PA7 1 &pcfg_pull_up>,
1899                                                 <7 RK_PB0 1 &pcfg_pull_none>;
1900                         };
1901
1902                         uart3_cts: uart3-cts {
1903                                 rockchip,pins = <7 RK_PB1 1 &pcfg_pull_up>;
1904                         };
1905
1906                         uart3_rts: uart3-rts {
1907                                 rockchip,pins = <7 RK_PB2 1 &pcfg_pull_none>;
1908                         };
1909                 };
1910
1911                 uart4 {
1912                         uart4_xfer: uart4-xfer {
1913                                 rockchip,pins = <5 RK_PB7 3 &pcfg_pull_up>,
1914                                                 <5 RK_PB6 3 &pcfg_pull_none>;
1915                         };
1916
1917                         uart4_cts: uart4-cts {
1918                                 rockchip,pins = <5 RK_PB4 3 &pcfg_pull_up>;
1919                         };
1920
1921                         uart4_rts: uart4-rts {
1922                                 rockchip,pins = <5 RK_PB5 3 &pcfg_pull_none>;
1923                         };
1924                 };
1925
1926                 tsadc {
1927                         otp_gpio: otp-gpio {
1928                                 rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
1929                         };
1930
1931                         otp_out: otp-out {
1932                                 rockchip,pins = <0 RK_PB2 1 &pcfg_pull_none>;
1933                         };
1934                 };
1935
1936                 pwm0 {
1937                         pwm0_pin: pwm0-pin {
1938                                 rockchip,pins = <7 RK_PA0 1 &pcfg_pull_none>;
1939                         };
1940                 };
1941
1942                 pwm1 {
1943                         pwm1_pin: pwm1-pin {
1944                                 rockchip,pins = <7 RK_PA1 1 &pcfg_pull_none>;
1945                         };
1946                 };
1947
1948                 pwm2 {
1949                         pwm2_pin: pwm2-pin {
1950                                 rockchip,pins = <7 RK_PC6 3 &pcfg_pull_none>;
1951                         };
1952                 };
1953
1954                 pwm3 {
1955                         pwm3_pin: pwm3-pin {
1956                                 rockchip,pins = <7 RK_PC7 3 &pcfg_pull_none>;
1957                         };
1958                 };
1959
1960                 gmac {
1961                         rgmii_pins: rgmii-pins {
1962                                 rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>,
1963                                                 <3 RK_PD7 3 &pcfg_pull_none>,
1964                                                 <3 RK_PD2 3 &pcfg_pull_none>,
1965                                                 <3 RK_PD3 3 &pcfg_pull_none>,
1966                                                 <3 RK_PD4 3 &pcfg_pull_none_12ma>,
1967                                                 <3 RK_PD5 3 &pcfg_pull_none_12ma>,
1968                                                 <3 RK_PD0 3 &pcfg_pull_none_12ma>,
1969                                                 <3 RK_PD1 3 &pcfg_pull_none_12ma>,
1970                                                 <4 RK_PA0 3 &pcfg_pull_none>,
1971                                                 <4 RK_PA5 3 &pcfg_pull_none>,
1972                                                 <4 RK_PA6 3 &pcfg_pull_none>,
1973                                                 <4 RK_PB1 3 &pcfg_pull_none_12ma>,
1974                                                 <4 RK_PA4 3 &pcfg_pull_none_12ma>,
1975                                                 <4 RK_PA1 3 &pcfg_pull_none>,
1976                                                 <4 RK_PA3 3 &pcfg_pull_none>;
1977                         };
1978
1979                         rmii_pins: rmii-pins {
1980                                 rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>,
1981                                                 <3 RK_PD7 3 &pcfg_pull_none>,
1982                                                 <3 RK_PD4 3 &pcfg_pull_none>,
1983                                                 <3 RK_PD5 3 &pcfg_pull_none>,
1984                                                 <4 RK_PA0 3 &pcfg_pull_none>,
1985                                                 <4 RK_PA5 3 &pcfg_pull_none>,
1986                                                 <4 RK_PA4 3 &pcfg_pull_none>,
1987                                                 <4 RK_PA1 3 &pcfg_pull_none>,
1988                                                 <4 RK_PA2 3 &pcfg_pull_none>,
1989                                                 <4 RK_PA3 3 &pcfg_pull_none>;
1990                         };
1991                 };
1992
1993                 spdif {
1994                         spdif_tx: spdif-tx {
1995                                 rockchip,pins = <6 RK_PB3 1 &pcfg_pull_none>;
1996                         };
1997                 };
1998         };
1999 };