arch/arm/boot/dts/rk3288-veyron.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Google Veyron (and derivatives) board device tree source
   4  *
   5  * Copyright 2015 Google, Inc
   6  */
   7
   8 #include <dt-bindings/clock/rockchip,rk808.h>
   9 #include <dt-bindings/input/input.h>
  10 #include "rk3288.dtsi"
  11
  12 / {
  13         /*
  14          * The default coreboot on veyron devices ignores memory@0 nodes
  15          * and would instead create another memory node.
  16          */
  17         memory {
  18                 device_type = "memory";
  19                 reg = <0x0 0x0 0x0 0x80000000>;
  20         };
  21
  22         gpio_keys: gpio-keys {
  23                 compatible = "gpio-keys";
  24                 #address-cells = <1>;
  25                 #size-cells = <0>;
  26
  27                 pinctrl-names = "default";
  28                 pinctrl-0 = <&pwr_key_l>;
  29                 power {
  30                         label = "Power";
  31                         gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
  32                         linux,code = <KEY_POWER>;
  33                         debounce-interval = <100>;
  34                         wakeup-source;
  35                 };
  36         };
  37
  38         gpio-restart {
  39                 compatible = "gpio-restart";
  40                 gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
  41                 pinctrl-names = "default";
  42                 pinctrl-0 = <&ap_warm_reset_h>;
  43                 priority = <200>;
  44         };
  45
  46         emmc_pwrseq: emmc-pwrseq {
  47                 compatible = "mmc-pwrseq-emmc";
  48                 pinctrl-0 = <&emmc_reset>;
  49                 pinctrl-names = "default";
  50                 reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>;
  51         };
  52
  53         sdio_pwrseq: sdio-pwrseq {
  54                 compatible = "mmc-pwrseq-simple";
  55                 clocks = <&rk808 RK808_CLKOUT1>;
  56                 clock-names = "ext_clock";
  57                 pinctrl-names = "default";
  58                 pinctrl-0 = <&bt_enable_l>, <&wifi_enable_h>;
  59
  60                 /*
  61                  * On the module itself this is one of these (depending
  62                  * on the actual card populated):
  63                  * - SDIO_RESET_L_WL_REG_ON
  64                  * - PDN (power down when low)
  65                  */
  66                 reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>;
  67         };
  68
  69         vcc_5v: vcc-5v {
  70                 compatible = "regulator-fixed";
  71                 regulator-name = "vcc_5v";
  72                 regulator-always-on;
  73                 regulator-boot-on;
  74                 regulator-min-microvolt = <5000000>;
  75                 regulator-max-microvolt = <5000000>;
  76         };
  77
  78         vcc33_sys: vcc33-sys {
  79                 compatible = "regulator-fixed";
  80                 regulator-name = "vcc33_sys";
  81                 regulator-always-on;
  82                 regulator-boot-on;
  83                 regulator-min-microvolt = <3300000>;
  84                 regulator-max-microvolt = <3300000>;
  85         };
  86
  87         vcc50_hdmi: vcc50-hdmi {
  88                 compatible = "regulator-fixed";
  89                 regulator-name = "vcc50_hdmi";
  90                 regulator-always-on;
  91                 regulator-boot-on;
  92                 vin-supply = <&vcc_5v>;
  93         };
  94 };
  95
  96 &cpu0 {
  97         cpu0-supply = <&vdd_cpu>;
  98 };
  99
 100 /* rk3288-c used in Veyron Chrome-devices has slightly changed OPPs */
 101 &cpu_opp_table {
 102         /delete-node/ opp-312000000;
 103
 104         opp-1512000000 {
 105                 opp-microvolt = <1250000>;
 106         };
 107         opp-1608000000 {
 108                 opp-microvolt = <1300000>;
 109         };
 110         opp-1704000000 {
 111                 opp-hz = /bits/ 64 <1704000000>;
 112                 opp-microvolt = <1350000>;
 113         };
 114         opp-1800000000 {
 115                 opp-hz = /bits/ 64 <1800000000>;
 116                 opp-microvolt = <1400000>;
 117         };
 118 };
 119
 120 &emmc {
 121         status = "okay";
 122
 123         bus-width = <8>;
 124         cap-mmc-highspeed;
 125         rockchip,default-sample-phase = <158>;
 126         disable-wp;
 127         mmc-hs200-1_8v;
 128         mmc-pwrseq = <&emmc_pwrseq>;
 129         non-removable;
 130         pinctrl-names = "default";
 131         pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
 132 };
 133
 134 &gpu {
 135         mali-supply = <&vdd_gpu>;
 136         status = "okay";
 137 };
 138
 139 &hdmi {
 140         ddc-i2c-bus = <&i2c5>;
 141         status = "okay";
 142 };
 143
 144 &i2c0 {
 145         status = "okay";
 146
 147         clock-frequency = <400000>;
 148         i2c-scl-falling-time-ns = <50>;         /* 2.5ns measured */
 149         i2c-scl-rising-time-ns = <100>;         /* 45ns measured */
 150
 151         rk808: pmic@1b {
 152                 compatible = "rockchip,rk808";
 153                 reg = <0x1b>;
 154                 clock-output-names = "xin32k", "wifibt_32kin";
 155                 interrupt-parent = <&gpio0>;
 156                 interrupts = <RK_PA4 IRQ_TYPE_LEVEL_LOW>;
 157                 pinctrl-names = "default";
 158                 pinctrl-0 = <&pmic_int_l>;
 159                 rockchip,system-power-controller;
 160                 wakeup-source;
 161                 #clock-cells = <1>;
 162
 163                 vcc1-supply = <&vcc33_sys>;
 164                 vcc2-supply = <&vcc33_sys>;
 165                 vcc3-supply = <&vcc33_sys>;
 166                 vcc4-supply = <&vcc33_sys>;
 167                 vcc6-supply = <&vcc_5v>;
 168                 vcc7-supply = <&vcc33_sys>;
 169                 vcc8-supply = <&vcc33_sys>;
 170                 vcc12-supply = <&vcc_18>;
 171                 vddio-supply = <&vcc33_io>;
 172
 173                 regulators {
 174                         vdd_cpu: DCDC_REG1 {
 175                                 regulator-name = "vdd_arm";
 176                                 regulator-always-on;
 177                                 regulator-boot-on;
 178                                 regulator-min-microvolt = <750000>;
 179                                 regulator-max-microvolt = <1450000>;
 180                                 regulator-ramp-delay = <6001>;
 181                                 regulator-state-mem {
 182                                         regulator-off-in-suspend;
 183                                 };
 184                         };
 185
 186                         vdd_gpu: DCDC_REG2 {
 187                                 regulator-name = "vdd_gpu";
 188                                 regulator-always-on;
 189                                 regulator-boot-on;
 190                                 regulator-min-microvolt = <800000>;
 191                                 regulator-max-microvolt = <1250000>;
 192                                 regulator-ramp-delay = <6001>;
 193                                 regulator-state-mem {
 194                                         regulator-on-in-suspend;
 195                                         regulator-suspend-microvolt = <1000000>;
 196                                 };
 197                         };
 198
 199                         vcc135_ddr: DCDC_REG3 {
 200                                 regulator-name = "vcc135_ddr";
 201                                 regulator-always-on;
 202                                 regulator-boot-on;
 203                                 regulator-state-mem {
 204                                         regulator-on-in-suspend;
 205                                 };
 206                         };
 207
 208                         /*
 209                          * vcc_18 has several aliases.  (vcc18_flashio and
 210                          * vcc18_wl).  We'll add those aliases here just to
 211                          * make it easier to follow the schematic.  The signals
 212                          * are actually hooked together and only separated for
 213                          * power measurement purposes).
 214                          */
 215                         vcc18_wl: vcc18_flashio: vcc_18: DCDC_REG4 {
 216                                 regulator-name = "vcc_18";
 217                                 regulator-always-on;
 218                                 regulator-boot-on;
 219                                 regulator-min-microvolt = <1800000>;
 220                                 regulator-max-microvolt = <1800000>;
 221                                 regulator-state-mem {
 222                                         regulator-on-in-suspend;
 223                                         regulator-suspend-microvolt = <1800000>;
 224                                 };
 225                         };
 226
 227                         /*
 228                          * Note that both vcc33_io and vcc33_pmuio are always
 229                          * powered together. To simplify the logic in the dts
 230                          * we just refer to vcc33_io every time something is
 231                          * powered from vcc33_pmuio. In fact, on later boards
 232                          * (such as danger) they're the same net.
 233                          */
 234                         vcc33_io: LDO_REG1 {
 235                                 regulator-name = "vcc33_io";
 236                                 regulator-always-on;
 237                                 regulator-boot-on;
 238                                 regulator-min-microvolt = <3300000>;
 239                                 regulator-max-microvolt = <3300000>;
 240                                 regulator-state-mem {
 241                                         regulator-on-in-suspend;
 242                                         regulator-suspend-microvolt = <3300000>;
 243                                 };
 244                         };
 245
 246                         vdd_10: LDO_REG3 {
 247                                 regulator-name = "vdd_10";
 248                                 regulator-always-on;
 249                                 regulator-boot-on;
 250                                 regulator-min-microvolt = <1000000>;
 251                                 regulator-max-microvolt = <1000000>;
 252                                 regulator-state-mem {
 253                                         regulator-on-in-suspend;
 254                                         regulator-suspend-microvolt = <1000000>;
 255                                 };
 256                         };
 257
 258                         vdd10_lcd_pwren_h: LDO_REG7 {
 259                                 regulator-name = "vdd10_lcd_pwren_h";
 260                                 regulator-always-on;
 261                                 regulator-boot-on;
 262                                 regulator-min-microvolt = <2500000>;
 263                                 regulator-max-microvolt = <2500000>;
 264                                 regulator-state-mem {
 265                                         regulator-off-in-suspend;
 266                                 };
 267                         };
 268
 269                         vcc33_lcd: SWITCH_REG1 {
 270                                 regulator-name = "vcc33_lcd";
 271                                 regulator-always-on;
 272                                 regulator-boot-on;
 273                                 regulator-state-mem {
 274                                         regulator-off-in-suspend;
 275                                 };
 276                         };
 277                 };
 278         };
 279 };
 280
 281 &i2c1 {
 282         status = "okay";
 283
 284         clock-frequency = <400000>;
 285         i2c-scl-falling-time-ns = <50>;         /* 2.5ns measured */
 286         i2c-scl-rising-time-ns = <100>;         /* 40ns measured */
 287
 288         tpm: tpm@20 {
 289                 compatible = "infineon,slb9645tt";
 290                 reg = <0x20>;
 291                 powered-while-suspended;
 292         };
 293 };
 294
 295 &i2c2 {
 296         status = "okay";
 297
 298         /* 100kHz since 4.7k resistors don't rise fast enough */
 299         clock-frequency = <100000>;
 300         i2c-scl-falling-time-ns = <50>;         /* 10ns measured */
 301         i2c-scl-rising-time-ns = <800>;         /* 600ns measured */
 302 };
 303
 304 &i2c4 {
 305         status = "okay";
 306
 307         clock-frequency = <400000>;
 308         i2c-scl-falling-time-ns = <50>;         /* 11ns measured */
 309         i2c-scl-rising-time-ns = <300>;         /* 225ns measured */
 310 };
 311
 312 &i2c5 {
 313         status = "okay";
 314
 315         clock-frequency = <100000>;
 316         i2c-scl-falling-time-ns = <300>;
 317         i2c-scl-rising-time-ns = <1000>;
 318 };
 319
 320 &io_domains {
 321         status = "okay";
 322
 323         bb-supply = <&vcc33_io>;
 324         dvp-supply = <&vcc_18>;
 325         flash0-supply = <&vcc18_flashio>;
 326         gpio1830-supply = <&vcc33_io>;
 327         gpio30-supply = <&vcc33_io>;
 328         lcdc-supply = <&vcc33_lcd>;
 329         wifi-supply = <&vcc18_wl>;
 330 };
 331
 332 &pwm1 {
 333         status = "okay";
 334 };
 335
 336 &sdio0 {
 337         status = "okay";
 338
 339         bus-width = <4>;
 340         cap-sd-highspeed;
 341         cap-sdio-irq;
 342         keep-power-in-suspend;
 343         mmc-pwrseq = <&sdio_pwrseq>;
 344         non-removable;
 345         pinctrl-names = "default";
 346         pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_bus4>;
 347         sd-uhs-sdr12;
 348         sd-uhs-sdr25;
 349         sd-uhs-sdr50;
 350         sd-uhs-sdr104;
 351         vmmc-supply = <&vcc33_sys>;
 352         vqmmc-supply = <&vcc18_wl>;
 353 };
 354
 355 &spi2 {
 356         status = "okay";
 357
 358         rx-sample-delay-ns = <12>;
 359
 360         flash@0 {
 361                 compatible = "jedec,spi-nor";
 362                 spi-max-frequency = <50000000>;
 363                 reg = <0>;
 364         };
 365 };
 366
 367 &tsadc {
 368         status = "okay";
 369
 370         rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
 371         rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
 372 };
 373
 374 &uart0 {
 375         status = "okay";
 376
 377         /* We need to go faster than 24MHz, so adjust clock parents / rates */
 378         assigned-clocks = <&cru SCLK_UART0>;
 379         assigned-clock-rates = <48000000>;
 380
 381         /* Pins don't include flow control by default; add that in */
 382         pinctrl-names = "default";
 383         pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 384 };
 385
 386 &uart1 {
 387         status = "okay";
 388 };
 389
 390 &uart2 {
 391         status = "okay";
 392 };
 393
 394 &usbphy {
 395         status = "okay";
 396 };
 397
 398 &usb_host0_ehci {
 399         status = "okay";
 400
 401         needs-reset-on-resume;
 402 };
 403
 404 &usb_host1 {
 405         status = "okay";
 406 };
 407
 408 &usb_otg {
 409         status = "okay";
 410
 411         assigned-clocks = <&cru SCLK_USBPHY480M_SRC>;
 412         assigned-clock-parents = <&usbphy0>;
 413         dr_mode = "host";
 414 };
 415
 416 &vopb {
 417         status = "okay";
 418 };
 419
 420 &vopb_mmu {
 421         status = "okay";
 422 };
 423
 424 &wdt {
 425         status = "okay";
 426 };
 427
 428 &pinctrl {
 429         pinctrl-names = "default", "sleep";
 430         pinctrl-0 = <
 431                 /* Common for sleep and wake, but no owners */
 432                 &global_pwroff
 433         >;
 434         pinctrl-1 = <
 435                 /* Common for sleep and wake, but no owners */
 436                 &global_pwroff
 437         >;
 438
 439         pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
 440                 bias-disable;
 441                 drive-strength = <8>;
 442         };
 443
 444         pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
 445                 bias-pull-up;
 446                 drive-strength = <8>;
 447         };
 448
 449         pcfg_output_high: pcfg-output-high {
 450                 output-high;
 451         };
 452
 453         pcfg_output_low: pcfg-output-low {
 454                 output-low;
 455         };
 456
 457         buttons {
 458                 pwr_key_l: pwr-key-l {
 459                         rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
 460                 };
 461         };
 462
 463         emmc {
 464                 emmc_reset: emmc-reset {
 465                         rockchip,pins = <2 9 RK_FUNC_GPIO &pcfg_pull_none>;
 466                 };
 467
 468                 /*
 469                  * We run eMMC at max speed; bump up drive strength.
 470                  * We also have external pulls, so disable the internal ones.
 471                  */
 472                 emmc_clk: emmc-clk {
 473                         rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
 474                 };
 475
 476                 emmc_cmd: emmc-cmd {
 477                         rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
 478                 };
 479
 480                 emmc_bus8: emmc-bus8 {
 481                         rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 482                                         <3 1 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 483                                         <3 2 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 484                                         <3 3 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 485                                         <3 4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 486                                         <3 5 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 487                                         <3 6 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 488                                         <3 7 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
 489                 };
 490         };
 491
 492         pmic {
 493                 pmic_int_l: pmic-int-l {
 494                         rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;
 495                 };
 496         };
 497
 498         reboot {
 499                 ap_warm_reset_h: ap-warm-reset-h {
 500                         rockchip,pins = <RK_GPIO0 13 RK_FUNC_GPIO &pcfg_pull_none>;
 501                 };
 502         };
 503
 504         recovery-switch {
 505                 rec_mode_l: rec-mode-l {
 506                         rockchip,pins = <0 9 RK_FUNC_GPIO &pcfg_pull_up>;
 507                 };
 508         };
 509
 510         sdio0 {
 511                 wifi_enable_h: wifienable-h {
 512                         rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_none>;
 513                 };
 514
 515                 /* NOTE: mislabelled on schematic; should be bt_enable_h */
 516                 bt_enable_l: bt-enable-l {
 517                         rockchip,pins = <4 29 RK_FUNC_GPIO &pcfg_pull_none>;
 518                 };
 519
 520                 /*
 521                  * We run sdio0 at max speed; bump up drive strength.
 522                  * We also have external pulls, so disable the internal ones.
 523                  */
 524                 sdio0_bus4: sdio0-bus4 {
 525                         rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
 526                                         <4 21 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
 527                                         <4 22 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
 528                                         <4 23 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
 529                 };
 530
 531                 sdio0_cmd: sdio0-cmd {
 532                         rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
 533                 };
 534
 535                 sdio0_clk: sdio0-clk {
 536                         rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
 537                 };
 538         };
 539
 540         tpm {
 541                 tpm_int_h: tpm-int-h {
 542                         rockchip,pins = <7 4 RK_FUNC_GPIO &pcfg_pull_none>;
 543                 };
 544         };
 545
 546         write-protect {
 547                 fw_wp_ap: fw-wp-ap {
 548                         rockchip,pins = <7 6 RK_FUNC_GPIO &pcfg_pull_none>;
 549                 };
 550         };
 551 };