1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3228-cru.h>
8 #include <dt-bindings/thermal/thermal.h>
14 interrupt-parent = <&gic>;
29 compatible = "arm,cortex-a7";
31 resets = <&cru SRST_CORE0>;
32 operating-points-v2 = <&cpu0_opp_table>;
33 #cooling-cells = <2>; /* min followed by max */
34 clock-latency = <40000>;
35 clocks = <&cru ARMCLK>;
36 enable-method = "psci";
41 compatible = "arm,cortex-a7";
43 resets = <&cru SRST_CORE1>;
44 operating-points-v2 = <&cpu0_opp_table>;
45 #cooling-cells = <2>; /* min followed by max */
46 enable-method = "psci";
51 compatible = "arm,cortex-a7";
53 resets = <&cru SRST_CORE2>;
54 operating-points-v2 = <&cpu0_opp_table>;
55 #cooling-cells = <2>; /* min followed by max */
56 enable-method = "psci";
61 compatible = "arm,cortex-a7";
63 resets = <&cru SRST_CORE3>;
64 operating-points-v2 = <&cpu0_opp_table>;
65 #cooling-cells = <2>; /* min followed by max */
66 enable-method = "psci";
70 cpu0_opp_table: opp_table0 {
71 compatible = "operating-points-v2";
75 opp-hz = /bits/ 64 <408000000>;
76 opp-microvolt = <950000>;
77 clock-latency-ns = <40000>;
81 opp-hz = /bits/ 64 <600000000>;
82 opp-microvolt = <975000>;
85 opp-hz = /bits/ 64 <816000000>;
86 opp-microvolt = <1000000>;
89 opp-hz = /bits/ 64 <1008000000>;
90 opp-microvolt = <1175000>;
93 opp-hz = /bits/ 64 <1200000000>;
94 opp-microvolt = <1275000>;
99 compatible = "simple-bus";
100 #address-cells = <1>;
104 pdma: pdma@110f0000 {
105 compatible = "arm,pl330", "arm,primecell";
106 reg = <0x110f0000 0x4000>;
107 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
108 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
110 clocks = <&cru ACLK_DMAC>;
111 clock-names = "apb_pclk";
116 compatible = "arm,cortex-a7-pmu";
117 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
118 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
119 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
120 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
121 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
125 compatible = "arm,psci-1.0", "arm,psci-0.2";
130 compatible = "arm,armv7-timer";
131 arm,cpu-registers-not-fw-configured;
132 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
133 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
134 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
135 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
136 clock-frequency = <24000000>;
140 compatible = "fixed-clock";
141 clock-frequency = <24000000>;
142 clock-output-names = "xin24m";
146 display_subsystem: display-subsystem {
147 compatible = "rockchip,display-subsystem";
151 i2s1: i2s1@100b0000 {
152 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
153 reg = <0x100b0000 0x4000>;
154 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
155 #address-cells = <1>;
157 clock-names = "i2s_clk", "i2s_hclk";
158 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
159 dmas = <&pdma 14>, <&pdma 15>;
160 dma-names = "tx", "rx";
161 pinctrl-names = "default";
162 pinctrl-0 = <&i2s1_bus>;
166 i2s0: i2s0@100c0000 {
167 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
168 reg = <0x100c0000 0x4000>;
169 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
170 #address-cells = <1>;
172 clock-names = "i2s_clk", "i2s_hclk";
173 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
174 dmas = <&pdma 11>, <&pdma 12>;
175 dma-names = "tx", "rx";
179 spdif: spdif@100d0000 {
180 compatible = "rockchip,rk3228-spdif";
181 reg = <0x100d0000 0x1000>;
182 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
183 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
184 clock-names = "mclk", "hclk";
187 pinctrl-names = "default";
188 pinctrl-0 = <&spdif_tx>;
192 i2s2: i2s2@100e0000 {
193 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
194 reg = <0x100e0000 0x4000>;
195 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
196 #address-cells = <1>;
198 clock-names = "i2s_clk", "i2s_hclk";
199 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
200 dmas = <&pdma 0>, <&pdma 1>;
201 dma-names = "tx", "rx";
205 grf: syscon@11000000 {
206 compatible = "rockchip,rk3228-grf", "syscon", "simple-mfd";
207 reg = <0x11000000 0x1000>;
208 #address-cells = <1>;
211 io_domains: io-domains {
212 compatible = "rockchip,rk3228-io-voltage-domain";
216 u2phy0: usb2-phy@760 {
217 compatible = "rockchip,rk3228-usb2phy";
219 clocks = <&cru SCLK_OTGPHY0>;
220 clock-names = "phyclk";
221 clock-output-names = "usb480m_phy0";
225 u2phy0_otg: otg-port {
226 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
227 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
228 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
229 interrupt-names = "otg-bvalid", "otg-id",
235 u2phy0_host: host-port {
236 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
237 interrupt-names = "linestate";
243 u2phy1: usb2-phy@800 {
244 compatible = "rockchip,rk3228-usb2phy";
246 clocks = <&cru SCLK_OTGPHY1>;
247 clock-names = "phyclk";
248 clock-output-names = "usb480m_phy1";
252 u2phy1_otg: otg-port {
253 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
254 interrupt-names = "linestate";
259 u2phy1_host: host-port {
260 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
261 interrupt-names = "linestate";
268 uart0: serial@11010000 {
269 compatible = "snps,dw-apb-uart";
270 reg = <0x11010000 0x100>;
271 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
272 clock-frequency = <24000000>;
273 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
274 clock-names = "baudclk", "apb_pclk";
275 pinctrl-names = "default";
276 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
282 uart1: serial@11020000 {
283 compatible = "snps,dw-apb-uart";
284 reg = <0x11020000 0x100>;
285 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
286 clock-frequency = <24000000>;
287 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
288 clock-names = "baudclk", "apb_pclk";
289 pinctrl-names = "default";
290 pinctrl-0 = <&uart1_xfer>;
296 uart2: serial@11030000 {
297 compatible = "snps,dw-apb-uart";
298 reg = <0x11030000 0x100>;
299 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
300 clock-frequency = <24000000>;
301 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
302 clock-names = "baudclk", "apb_pclk";
303 pinctrl-names = "default";
304 pinctrl-0 = <&uart2_xfer>;
310 efuse: efuse@11040000 {
311 compatible = "rockchip,rk3228-efuse";
312 reg = <0x11040000 0x20>;
313 clocks = <&cru PCLK_EFUSE_256>;
314 clock-names = "pclk_efuse";
315 #address-cells = <1>;
322 cpu_leakage: cpu_leakage@17 {
328 compatible = "rockchip,rk3228-i2c";
329 reg = <0x11050000 0x1000>;
330 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
331 #address-cells = <1>;
334 clocks = <&cru PCLK_I2C0>;
335 pinctrl-names = "default";
336 pinctrl-0 = <&i2c0_xfer>;
341 compatible = "rockchip,rk3228-i2c";
342 reg = <0x11060000 0x1000>;
343 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
344 #address-cells = <1>;
347 clocks = <&cru PCLK_I2C1>;
348 pinctrl-names = "default";
349 pinctrl-0 = <&i2c1_xfer>;
354 compatible = "rockchip,rk3228-i2c";
355 reg = <0x11070000 0x1000>;
356 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
357 #address-cells = <1>;
360 clocks = <&cru PCLK_I2C2>;
361 pinctrl-names = "default";
362 pinctrl-0 = <&i2c2_xfer>;
367 compatible = "rockchip,rk3228-i2c";
368 reg = <0x11080000 0x1000>;
369 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
370 #address-cells = <1>;
373 clocks = <&cru PCLK_I2C3>;
374 pinctrl-names = "default";
375 pinctrl-0 = <&i2c3_xfer>;
380 compatible = "rockchip,rk3228-spi";
381 reg = <0x11090000 0x1000>;
382 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
383 #address-cells = <1>;
385 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
386 clock-names = "spiclk", "apb_pclk";
387 pinctrl-names = "default";
388 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>;
392 wdt: watchdog@110a0000 {
393 compatible = "snps,dw-wdt";
394 reg = <0x110a0000 0x100>;
395 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
396 clocks = <&cru PCLK_CPU>;
401 compatible = "rockchip,rk3288-pwm";
402 reg = <0x110b0000 0x10>;
404 clocks = <&cru PCLK_PWM>;
406 pinctrl-names = "default";
407 pinctrl-0 = <&pwm0_pin>;
412 compatible = "rockchip,rk3288-pwm";
413 reg = <0x110b0010 0x10>;
415 clocks = <&cru PCLK_PWM>;
417 pinctrl-names = "default";
418 pinctrl-0 = <&pwm1_pin>;
423 compatible = "rockchip,rk3288-pwm";
424 reg = <0x110b0020 0x10>;
426 clocks = <&cru PCLK_PWM>;
428 pinctrl-names = "default";
429 pinctrl-0 = <&pwm2_pin>;
434 compatible = "rockchip,rk3288-pwm";
435 reg = <0x110b0030 0x10>;
437 clocks = <&cru PCLK_PWM>;
439 pinctrl-names = "default";
440 pinctrl-0 = <&pwm3_pin>;
444 timer: timer@110c0000 {
445 compatible = "rockchip,rk3228-timer", "rockchip,rk3288-timer";
446 reg = <0x110c0000 0x20>;
447 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
448 clocks = <&xin24m>, <&cru PCLK_TIMER>;
449 clock-names = "timer", "pclk";
452 cru: clock-controller@110e0000 {
453 compatible = "rockchip,rk3228-cru";
454 reg = <0x110e0000 0x1000>;
455 rockchip,grf = <&grf>;
459 <&cru PLL_GPLL>, <&cru ARMCLK>,
460 <&cru PLL_CPLL>, <&cru ACLK_PERI>,
461 <&cru HCLK_PERI>, <&cru PCLK_PERI>,
462 <&cru ACLK_CPU>, <&cru HCLK_CPU>,
464 assigned-clock-rates =
465 <594000000>, <816000000>,
466 <500000000>, <150000000>,
467 <150000000>, <75000000>,
468 <150000000>, <150000000>,
473 cpu_thermal: cpu-thermal {
474 polling-delay-passive = <100>; /* milliseconds */
475 polling-delay = <5000>; /* milliseconds */
477 thermal-sensors = <&tsadc 0>;
480 cpu_alert0: cpu_alert0 {
481 temperature = <70000>; /* millicelsius */
482 hysteresis = <2000>; /* millicelsius */
485 cpu_alert1: cpu_alert1 {
486 temperature = <75000>; /* millicelsius */
487 hysteresis = <2000>; /* millicelsius */
491 temperature = <90000>; /* millicelsius */
492 hysteresis = <2000>; /* millicelsius */
499 trip = <&cpu_alert0>;
501 <&cpu0 THERMAL_NO_LIMIT 6>,
502 <&cpu1 THERMAL_NO_LIMIT 6>,
503 <&cpu2 THERMAL_NO_LIMIT 6>,
504 <&cpu3 THERMAL_NO_LIMIT 6>;
507 trip = <&cpu_alert1>;
509 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
510 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
511 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
512 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
518 tsadc: tsadc@11150000 {
519 compatible = "rockchip,rk3228-tsadc";
520 reg = <0x11150000 0x100>;
521 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
522 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
523 clock-names = "tsadc", "apb_pclk";
524 assigned-clocks = <&cru SCLK_TSADC>;
525 assigned-clock-rates = <32768>;
526 resets = <&cru SRST_TSADC>;
527 reset-names = "tsadc-apb";
528 pinctrl-names = "init", "default", "sleep";
529 pinctrl-0 = <&otp_gpio>;
530 pinctrl-1 = <&otp_out>;
531 pinctrl-2 = <&otp_gpio>;
532 #thermal-sensor-cells = <0>;
533 rockchip,hw-tshut-temp = <95000>;
537 hdmi_phy: hdmi-phy@12030000 {
538 compatible = "rockchip,rk3228-hdmi-phy";
539 reg = <0x12030000 0x10000>;
540 clocks = <&cru PCLK_HDMI_PHY>, <&xin24m>, <&cru DCLK_HDMI_PHY>;
541 clock-names = "sysclk", "refoclk", "refpclk";
543 clock-output-names = "hdmiphy_phy";
549 compatible = "rockchip,rk3228-mali", "arm,mali-400";
550 reg = <0x20000000 0x10000>;
551 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
552 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
553 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
554 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
555 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
556 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
557 interrupt-names = "gp",
563 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
564 clock-names = "bus", "core";
565 resets = <&cru SRST_GPU_A>;
569 vpu_mmu: iommu@20020800 {
570 compatible = "rockchip,iommu";
571 reg = <0x20020800 0x100>;
572 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
573 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
574 clock-names = "aclk", "iface";
579 vdec_mmu: iommu@20030480 {
580 compatible = "rockchip,iommu";
581 reg = <0x20030480 0x40>, <0x200304c0 0x40>;
582 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
583 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
584 clock-names = "aclk", "iface";
590 compatible = "rockchip,rk3228-vop";
591 reg = <0x20050000 0x1ffc>;
592 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
593 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
594 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
595 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
596 reset-names = "axi", "ahb", "dclk";
601 #address-cells = <1>;
604 vop_out_hdmi: endpoint@0 {
606 remote-endpoint = <&hdmi_in_vop>;
611 vop_mmu: iommu@20053f00 {
612 compatible = "rockchip,iommu";
613 reg = <0x20053f00 0x100>;
614 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
615 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
616 clock-names = "aclk", "iface";
621 iep_mmu: iommu@20070800 {
622 compatible = "rockchip,iommu";
623 reg = <0x20070800 0x100>;
624 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
625 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
626 clock-names = "aclk", "iface";
631 hdmi: hdmi@200a0000 {
632 compatible = "rockchip,rk3228-dw-hdmi";
633 reg = <0x200a0000 0x20000>;
635 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
636 assigned-clocks = <&cru SCLK_HDMI_PHY>;
637 assigned-clock-parents = <&hdmi_phy>;
638 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>;
639 clock-names = "iahb", "isfr", "cec";
640 pinctrl-names = "default";
641 pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>;
642 resets = <&cru SRST_HDMI_P>;
643 reset-names = "hdmi";
646 rockchip,grf = <&grf>;
651 #address-cells = <1>;
653 hdmi_in_vop: endpoint@0 {
655 remote-endpoint = <&vop_out_hdmi>;
661 sdmmc: dwmmc@30000000 {
662 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
663 reg = <0x30000000 0x4000>;
664 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
665 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
666 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
667 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
668 fifo-depth = <0x100>;
669 pinctrl-names = "default";
670 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
674 sdio: dwmmc@30010000 {
675 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
676 reg = <0x30010000 0x4000>;
677 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
678 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
679 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
680 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
681 fifo-depth = <0x100>;
682 pinctrl-names = "default";
683 pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>;
687 emmc: dwmmc@30020000 {
688 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
689 reg = <0x30020000 0x4000>;
690 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
691 clock-frequency = <37500000>;
692 max-frequency = <37500000>;
693 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
694 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
695 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
697 default-sample-phase = <158>;
698 fifo-depth = <0x100>;
699 pinctrl-names = "default";
700 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
701 resets = <&cru SRST_EMMC>;
702 reset-names = "reset";
706 usb_otg: usb@30040000 {
707 compatible = "rockchip,rk3228-usb", "rockchip,rk3066-usb",
709 reg = <0x30040000 0x40000>;
710 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
711 clocks = <&cru HCLK_OTG>;
714 g-np-tx-fifo-size = <16>;
715 g-rx-fifo-size = <280>;
716 g-tx-fifo-size = <256 128 128 64 32 16>;
718 phys = <&u2phy0_otg>;
719 phy-names = "usb2-phy";
723 usb_host0_ehci: usb@30080000 {
724 compatible = "generic-ehci";
725 reg = <0x30080000 0x20000>;
726 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
727 clocks = <&cru HCLK_HOST0>, <&u2phy0>;
728 clock-names = "usbhost", "utmi";
729 phys = <&u2phy0_host>;
734 usb_host0_ohci: usb@300a0000 {
735 compatible = "generic-ohci";
736 reg = <0x300a0000 0x20000>;
737 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
738 clocks = <&cru HCLK_HOST0>, <&u2phy0>;
739 clock-names = "usbhost", "utmi";
740 phys = <&u2phy0_host>;
745 usb_host1_ehci: usb@300c0000 {
746 compatible = "generic-ehci";
747 reg = <0x300c0000 0x20000>;
748 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
749 clocks = <&cru HCLK_HOST1>, <&u2phy1>;
750 clock-names = "usbhost", "utmi";
751 phys = <&u2phy1_otg>;
756 usb_host1_ohci: usb@300e0000 {
757 compatible = "generic-ohci";
758 reg = <0x300e0000 0x20000>;
759 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
760 clocks = <&cru HCLK_HOST1>, <&u2phy1>;
761 clock-names = "usbhost", "utmi";
762 phys = <&u2phy1_otg>;
767 usb_host2_ehci: usb@30100000 {
768 compatible = "generic-ehci";
769 reg = <0x30100000 0x20000>;
770 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
771 clocks = <&cru HCLK_HOST2>, <&u2phy1>;
772 phys = <&u2phy1_host>;
774 clock-names = "usbhost", "utmi";
778 usb_host2_ohci: usb@30120000 {
779 compatible = "generic-ohci";
780 reg = <0x30120000 0x20000>;
781 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
782 clocks = <&cru HCLK_HOST2>, <&u2phy1>;
783 clock-names = "usbhost", "utmi";
784 phys = <&u2phy1_host>;
789 gmac: ethernet@30200000 {
790 compatible = "rockchip,rk3228-gmac";
791 reg = <0x30200000 0x10000>;
792 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
793 interrupt-names = "macirq";
794 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
795 <&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>,
796 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
798 clock-names = "stmmaceth", "mac_clk_rx",
799 "mac_clk_tx", "clk_mac_ref",
800 "clk_mac_refout", "aclk_mac",
802 resets = <&cru SRST_GMAC>;
803 reset-names = "stmmaceth";
804 rockchip,grf = <&grf>;
808 gic: interrupt-controller@32010000 {
809 compatible = "arm,gic-400";
810 interrupt-controller;
811 #interrupt-cells = <3>;
812 #address-cells = <0>;
814 reg = <0x32011000 0x1000>,
818 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
822 compatible = "rockchip,rk3228-pinctrl";
823 rockchip,grf = <&grf>;
824 #address-cells = <1>;
828 gpio0: gpio0@11110000 {
829 compatible = "rockchip,gpio-bank";
830 reg = <0x11110000 0x100>;
831 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
832 clocks = <&cru PCLK_GPIO0>;
837 interrupt-controller;
838 #interrupt-cells = <2>;
841 gpio1: gpio1@11120000 {
842 compatible = "rockchip,gpio-bank";
843 reg = <0x11120000 0x100>;
844 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
845 clocks = <&cru PCLK_GPIO1>;
850 interrupt-controller;
851 #interrupt-cells = <2>;
854 gpio2: gpio2@11130000 {
855 compatible = "rockchip,gpio-bank";
856 reg = <0x11130000 0x100>;
857 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
858 clocks = <&cru PCLK_GPIO2>;
863 interrupt-controller;
864 #interrupt-cells = <2>;
867 gpio3: gpio3@11140000 {
868 compatible = "rockchip,gpio-bank";
869 reg = <0x11140000 0x100>;
870 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
871 clocks = <&cru PCLK_GPIO3>;
876 interrupt-controller;
877 #interrupt-cells = <2>;
880 pcfg_pull_up: pcfg-pull-up {
884 pcfg_pull_down: pcfg-pull-down {
888 pcfg_pull_none: pcfg-pull-none {
892 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
893 drive-strength = <12>;
897 sdmmc_clk: sdmmc-clk {
898 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none_drv_12ma>;
901 sdmmc_cmd: sdmmc-cmd {
902 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_none_drv_12ma>;
905 sdmmc_bus4: sdmmc-bus4 {
906 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_none_drv_12ma>,
907 <1 RK_PC3 1 &pcfg_pull_none_drv_12ma>,
908 <1 RK_PC4 1 &pcfg_pull_none_drv_12ma>,
909 <1 RK_PC5 1 &pcfg_pull_none_drv_12ma>;
915 rockchip,pins = <3 RK_PA0 1 &pcfg_pull_none_drv_12ma>;
919 rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none_drv_12ma>;
922 sdio_bus4: sdio-bus4 {
923 rockchip,pins = <3 RK_PA2 1 &pcfg_pull_none_drv_12ma>,
924 <3 RK_PA3 1 &pcfg_pull_none_drv_12ma>,
925 <3 RK_PA4 1 &pcfg_pull_none_drv_12ma>,
926 <3 RK_PA5 1 &pcfg_pull_none_drv_12ma>;
932 rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>;
936 rockchip,pins = <1 RK_PC6 2 &pcfg_pull_none>;
939 emmc_bus8: emmc-bus8 {
940 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>,
941 <1 RK_PD1 2 &pcfg_pull_none>,
942 <1 RK_PD2 2 &pcfg_pull_none>,
943 <1 RK_PD3 2 &pcfg_pull_none>,
944 <1 RK_PD4 2 &pcfg_pull_none>,
945 <1 RK_PD5 2 &pcfg_pull_none>,
946 <1 RK_PD6 2 &pcfg_pull_none>,
947 <1 RK_PD7 2 &pcfg_pull_none>;
952 rgmii_pins: rgmii-pins {
953 rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>,
954 <2 RK_PB4 1 &pcfg_pull_none>,
955 <2 RK_PD1 1 &pcfg_pull_none>,
956 <2 RK_PC3 1 &pcfg_pull_none_drv_12ma>,
957 <2 RK_PC2 1 &pcfg_pull_none_drv_12ma>,
958 <2 RK_PC6 1 &pcfg_pull_none_drv_12ma>,
959 <2 RK_PC7 1 &pcfg_pull_none_drv_12ma>,
960 <2 RK_PB1 1 &pcfg_pull_none_drv_12ma>,
961 <2 RK_PB5 1 &pcfg_pull_none_drv_12ma>,
962 <2 RK_PC1 1 &pcfg_pull_none>,
963 <2 RK_PC0 1 &pcfg_pull_none>,
964 <2 RK_PC5 2 &pcfg_pull_none>,
965 <2 RK_PC4 2 &pcfg_pull_none>,
966 <2 RK_PB3 1 &pcfg_pull_none>,
967 <2 RK_PB0 1 &pcfg_pull_none>;
970 rmii_pins: rmii-pins {
971 rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>,
972 <2 RK_PB4 1 &pcfg_pull_none>,
973 <2 RK_PD1 1 &pcfg_pull_none>,
974 <2 RK_PC3 1 &pcfg_pull_none_drv_12ma>,
975 <2 RK_PC2 1 &pcfg_pull_none_drv_12ma>,
976 <2 RK_PB5 1 &pcfg_pull_none_drv_12ma>,
977 <2 RK_PC1 1 &pcfg_pull_none>,
978 <2 RK_PC0 1 &pcfg_pull_none>,
979 <2 RK_PB0 1 &pcfg_pull_none>,
980 <2 RK_PB7 1 &pcfg_pull_none>;
984 rockchip,pins = <2 RK_PB6 2 &pcfg_pull_none>,
985 <2 RK_PB0 2 &pcfg_pull_none>;
991 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_down>;
994 hdmii2c_xfer: hdmii2c-xfer {
995 rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>,
996 <0 RK_PA7 2 &pcfg_pull_none>;
1000 rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>;
1005 i2c0_xfer: i2c0-xfer {
1006 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
1007 <0 RK_PA1 1 &pcfg_pull_none>;
1012 i2c1_xfer: i2c1-xfer {
1013 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,
1014 <0 RK_PA3 1 &pcfg_pull_none>;
1019 i2c2_xfer: i2c2-xfer {
1020 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>,
1021 <2 RK_PC5 1 &pcfg_pull_none>;
1026 i2c3_xfer: i2c3-xfer {
1027 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,
1028 <0 RK_PA7 1 &pcfg_pull_none>;
1033 spi0_clk: spi0-clk {
1034 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_up>;
1036 spi0_cs0: spi0-cs0 {
1037 rockchip,pins = <0 RK_PB6 2 &pcfg_pull_up>;
1040 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_up>;
1043 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_up>;
1045 spi0_cs1: spi0-cs1 {
1046 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_up>;
1051 spi1_clk: spi1-clk {
1052 rockchip,pins = <0 RK_PC7 2 &pcfg_pull_up>;
1054 spi1_cs0: spi1-cs0 {
1055 rockchip,pins = <2 RK_PA2 2 &pcfg_pull_up>;
1058 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_up>;
1061 rockchip,pins = <2 RK_PA1 2 &pcfg_pull_up>;
1063 spi1_cs1: spi1-cs1 {
1064 rockchip,pins = <2 RK_PA3 2 &pcfg_pull_up>;
1069 i2s1_bus: i2s1-bus {
1070 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>,
1071 <0 RK_PB1 1 &pcfg_pull_none>,
1072 <0 RK_PB3 1 &pcfg_pull_none>,
1073 <0 RK_PB4 1 &pcfg_pull_none>,
1074 <0 RK_PB5 1 &pcfg_pull_none>,
1075 <0 RK_PB6 1 &pcfg_pull_none>,
1076 <1 RK_PA2 2 &pcfg_pull_none>,
1077 <1 RK_PA4 2 &pcfg_pull_none>,
1078 <1 RK_PA5 2 &pcfg_pull_none>;
1083 pwm0_pin: pwm0-pin {
1084 rockchip,pins = <3 RK_PC5 1 &pcfg_pull_none>;
1089 pwm1_pin: pwm1-pin {
1090 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>;
1095 pwm2_pin: pwm2-pin {
1096 rockchip,pins = <1 RK_PB4 2 &pcfg_pull_none>;
1101 pwm3_pin: pwm3-pin {
1102 rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>;
1107 spdif_tx: spdif-tx {
1108 rockchip,pins = <3 RK_PD7 2 &pcfg_pull_none>;
1113 otp_gpio: otp-gpio {
1114 rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
1118 rockchip,pins = <0 RK_PD0 2 &pcfg_pull_none>;
1123 uart0_xfer: uart0-xfer {
1124 rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>,
1125 <2 RK_PD3 1 &pcfg_pull_none>;
1128 uart0_cts: uart0-cts {
1129 rockchip,pins = <2 RK_PD5 1 &pcfg_pull_none>;
1132 uart0_rts: uart0-rts {
1133 rockchip,pins = <0 RK_PC1 1 &pcfg_pull_none>;
1138 uart1_xfer: uart1-xfer {
1139 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>,
1140 <1 RK_PB2 1 &pcfg_pull_none>;
1143 uart1_cts: uart1-cts {
1144 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>;
1147 uart1_rts: uart1-rts {
1148 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>;
1153 uart2_xfer: uart2-xfer {
1154 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>,
1155 <1 RK_PC3 2 &pcfg_pull_none>;
1158 uart21_xfer: uart21-xfer {
1159 rockchip,pins = <1 RK_PB2 2 &pcfg_pull_up>,
1160 <1 RK_PB1 2 &pcfg_pull_none>;
1163 uart2_cts: uart2-cts {
1164 rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>;
1167 uart2_rts: uart2-rts {
1168 rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>;