1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3228-cru.h>
8 #include <dt-bindings/thermal/thermal.h>
14 interrupt-parent = <&gic>;
29 compatible = "arm,cortex-a7";
31 resets = <&cru SRST_CORE0>;
32 operating-points-v2 = <&cpu0_opp_table>;
33 #cooling-cells = <2>; /* min followed by max */
34 clock-latency = <40000>;
35 clocks = <&cru ARMCLK>;
36 enable-method = "psci";
41 compatible = "arm,cortex-a7";
43 resets = <&cru SRST_CORE1>;
44 operating-points-v2 = <&cpu0_opp_table>;
45 #cooling-cells = <2>; /* min followed by max */
46 enable-method = "psci";
51 compatible = "arm,cortex-a7";
53 resets = <&cru SRST_CORE2>;
54 operating-points-v2 = <&cpu0_opp_table>;
55 #cooling-cells = <2>; /* min followed by max */
56 enable-method = "psci";
61 compatible = "arm,cortex-a7";
63 resets = <&cru SRST_CORE3>;
64 operating-points-v2 = <&cpu0_opp_table>;
65 #cooling-cells = <2>; /* min followed by max */
66 enable-method = "psci";
70 cpu0_opp_table: opp_table0 {
71 compatible = "operating-points-v2";
75 opp-hz = /bits/ 64 <408000000>;
76 opp-microvolt = <950000>;
77 clock-latency-ns = <40000>;
81 opp-hz = /bits/ 64 <600000000>;
82 opp-microvolt = <975000>;
85 opp-hz = /bits/ 64 <816000000>;
86 opp-microvolt = <1000000>;
89 opp-hz = /bits/ 64 <1008000000>;
90 opp-microvolt = <1175000>;
93 opp-hz = /bits/ 64 <1200000000>;
94 opp-microvolt = <1275000>;
99 compatible = "simple-bus";
100 #address-cells = <1>;
104 pdma: pdma@110f0000 {
105 compatible = "arm,pl330", "arm,primecell";
106 reg = <0x110f0000 0x4000>;
107 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
108 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
110 clocks = <&cru ACLK_DMAC>;
111 clock-names = "apb_pclk";
116 compatible = "arm,cortex-a7-pmu";
117 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
118 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
119 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
120 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
121 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
125 compatible = "arm,psci-1.0", "arm,psci-0.2";
130 compatible = "arm,armv7-timer";
131 arm,cpu-registers-not-fw-configured;
132 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
133 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
134 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
135 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
136 clock-frequency = <24000000>;
140 compatible = "fixed-clock";
141 clock-frequency = <24000000>;
142 clock-output-names = "xin24m";
146 i2s1: i2s1@100b0000 {
147 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
148 reg = <0x100b0000 0x4000>;
149 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
150 #address-cells = <1>;
152 clock-names = "i2s_clk", "i2s_hclk";
153 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
154 dmas = <&pdma 14>, <&pdma 15>;
155 dma-names = "tx", "rx";
156 pinctrl-names = "default";
157 pinctrl-0 = <&i2s1_bus>;
161 i2s0: i2s0@100c0000 {
162 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
163 reg = <0x100c0000 0x4000>;
164 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
165 #address-cells = <1>;
167 clock-names = "i2s_clk", "i2s_hclk";
168 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
169 dmas = <&pdma 11>, <&pdma 12>;
170 dma-names = "tx", "rx";
174 spdif: spdif@100d0000 {
175 compatible = "rockchip,rk3228-spdif";
176 reg = <0x100d0000 0x1000>;
177 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
178 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
179 clock-names = "mclk", "hclk";
182 pinctrl-names = "default";
183 pinctrl-0 = <&spdif_tx>;
187 i2s2: i2s2@100e0000 {
188 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
189 reg = <0x100e0000 0x4000>;
190 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
191 #address-cells = <1>;
193 clock-names = "i2s_clk", "i2s_hclk";
194 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
195 dmas = <&pdma 0>, <&pdma 1>;
196 dma-names = "tx", "rx";
200 grf: syscon@11000000 {
201 compatible = "rockchip,rk3228-grf", "syscon", "simple-mfd";
202 reg = <0x11000000 0x1000>;
203 #address-cells = <1>;
206 io_domains: io-domains {
207 compatible = "rockchip,rk3228-io-voltage-domain";
211 u2phy0: usb2-phy@760 {
212 compatible = "rockchip,rk3228-usb2phy";
214 clocks = <&cru SCLK_OTGPHY0>;
215 clock-names = "phyclk";
216 clock-output-names = "usb480m_phy0";
220 u2phy0_otg: otg-port {
221 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
222 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
223 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
224 interrupt-names = "otg-bvalid", "otg-id",
230 u2phy0_host: host-port {
231 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
232 interrupt-names = "linestate";
238 u2phy1: usb2-phy@800 {
239 compatible = "rockchip,rk3228-usb2phy";
241 clocks = <&cru SCLK_OTGPHY1>;
242 clock-names = "phyclk";
243 clock-output-names = "usb480m_phy1";
247 u2phy1_otg: otg-port {
248 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
249 interrupt-names = "linestate";
254 u2phy1_host: host-port {
255 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
256 interrupt-names = "linestate";
263 uart0: serial@11010000 {
264 compatible = "snps,dw-apb-uart";
265 reg = <0x11010000 0x100>;
266 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
267 clock-frequency = <24000000>;
268 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
269 clock-names = "baudclk", "apb_pclk";
270 pinctrl-names = "default";
271 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
277 uart1: serial@11020000 {
278 compatible = "snps,dw-apb-uart";
279 reg = <0x11020000 0x100>;
280 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
281 clock-frequency = <24000000>;
282 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
283 clock-names = "baudclk", "apb_pclk";
284 pinctrl-names = "default";
285 pinctrl-0 = <&uart1_xfer>;
291 uart2: serial@11030000 {
292 compatible = "snps,dw-apb-uart";
293 reg = <0x11030000 0x100>;
294 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
295 clock-frequency = <24000000>;
296 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
297 clock-names = "baudclk", "apb_pclk";
298 pinctrl-names = "default";
299 pinctrl-0 = <&uart2_xfer>;
305 efuse: efuse@11040000 {
306 compatible = "rockchip,rk3228-efuse";
307 reg = <0x11040000 0x20>;
308 clocks = <&cru PCLK_EFUSE_256>;
309 clock-names = "pclk_efuse";
310 #address-cells = <1>;
317 cpu_leakage: cpu_leakage@17 {
323 compatible = "rockchip,rk3228-i2c";
324 reg = <0x11050000 0x1000>;
325 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
326 #address-cells = <1>;
329 clocks = <&cru PCLK_I2C0>;
330 pinctrl-names = "default";
331 pinctrl-0 = <&i2c0_xfer>;
336 compatible = "rockchip,rk3228-i2c";
337 reg = <0x11060000 0x1000>;
338 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
339 #address-cells = <1>;
342 clocks = <&cru PCLK_I2C1>;
343 pinctrl-names = "default";
344 pinctrl-0 = <&i2c1_xfer>;
349 compatible = "rockchip,rk3228-i2c";
350 reg = <0x11070000 0x1000>;
351 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
352 #address-cells = <1>;
355 clocks = <&cru PCLK_I2C2>;
356 pinctrl-names = "default";
357 pinctrl-0 = <&i2c2_xfer>;
362 compatible = "rockchip,rk3228-i2c";
363 reg = <0x11080000 0x1000>;
364 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
365 #address-cells = <1>;
368 clocks = <&cru PCLK_I2C3>;
369 pinctrl-names = "default";
370 pinctrl-0 = <&i2c3_xfer>;
375 compatible = "rockchip,rk3228-spi";
376 reg = <0x11090000 0x1000>;
377 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
378 #address-cells = <1>;
380 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
381 clock-names = "spiclk", "apb_pclk";
382 pinctrl-names = "default";
383 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>;
387 wdt: watchdog@110a0000 {
388 compatible = "snps,dw-wdt";
389 reg = <0x110a0000 0x100>;
390 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
391 clocks = <&cru PCLK_CPU>;
396 compatible = "rockchip,rk3288-pwm";
397 reg = <0x110b0000 0x10>;
399 clocks = <&cru PCLK_PWM>;
401 pinctrl-names = "default";
402 pinctrl-0 = <&pwm0_pin>;
407 compatible = "rockchip,rk3288-pwm";
408 reg = <0x110b0010 0x10>;
410 clocks = <&cru PCLK_PWM>;
412 pinctrl-names = "default";
413 pinctrl-0 = <&pwm1_pin>;
418 compatible = "rockchip,rk3288-pwm";
419 reg = <0x110b0020 0x10>;
421 clocks = <&cru PCLK_PWM>;
423 pinctrl-names = "default";
424 pinctrl-0 = <&pwm2_pin>;
429 compatible = "rockchip,rk3288-pwm";
430 reg = <0x110b0030 0x10>;
432 clocks = <&cru PCLK_PWM>;
434 pinctrl-names = "default";
435 pinctrl-0 = <&pwm3_pin>;
439 timer: timer@110c0000 {
440 compatible = "rockchip,rk3228-timer", "rockchip,rk3288-timer";
441 reg = <0x110c0000 0x20>;
442 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
443 clocks = <&xin24m>, <&cru PCLK_TIMER>;
444 clock-names = "timer", "pclk";
447 cru: clock-controller@110e0000 {
448 compatible = "rockchip,rk3228-cru";
449 reg = <0x110e0000 0x1000>;
450 rockchip,grf = <&grf>;
454 <&cru PLL_GPLL>, <&cru ARMCLK>,
455 <&cru PLL_CPLL>, <&cru ACLK_PERI>,
456 <&cru HCLK_PERI>, <&cru PCLK_PERI>,
457 <&cru ACLK_CPU>, <&cru HCLK_CPU>,
459 assigned-clock-rates =
460 <594000000>, <816000000>,
461 <500000000>, <150000000>,
462 <150000000>, <75000000>,
463 <150000000>, <150000000>,
468 cpu_thermal: cpu-thermal {
469 polling-delay-passive = <100>; /* milliseconds */
470 polling-delay = <5000>; /* milliseconds */
472 thermal-sensors = <&tsadc 0>;
475 cpu_alert0: cpu_alert0 {
476 temperature = <70000>; /* millicelsius */
477 hysteresis = <2000>; /* millicelsius */
480 cpu_alert1: cpu_alert1 {
481 temperature = <75000>; /* millicelsius */
482 hysteresis = <2000>; /* millicelsius */
486 temperature = <90000>; /* millicelsius */
487 hysteresis = <2000>; /* millicelsius */
494 trip = <&cpu_alert0>;
496 <&cpu0 THERMAL_NO_LIMIT 6>;
499 trip = <&cpu_alert1>;
501 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
507 tsadc: tsadc@11150000 {
508 compatible = "rockchip,rk3228-tsadc";
509 reg = <0x11150000 0x100>;
510 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
511 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
512 clock-names = "tsadc", "apb_pclk";
513 assigned-clocks = <&cru SCLK_TSADC>;
514 assigned-clock-rates = <32768>;
515 resets = <&cru SRST_TSADC>;
516 reset-names = "tsadc-apb";
517 pinctrl-names = "init", "default", "sleep";
518 pinctrl-0 = <&otp_gpio>;
519 pinctrl-1 = <&otp_out>;
520 pinctrl-2 = <&otp_gpio>;
521 #thermal-sensor-cells = <0>;
522 rockchip,hw-tshut-temp = <95000>;
527 compatible = "rockchip,rk3228-mali", "arm,mali-400";
528 reg = <0x20000000 0x10000>;
529 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
530 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
531 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
532 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
533 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
534 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
535 interrupt-names = "gp",
541 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
542 clock-names = "bus", "core";
543 resets = <&cru SRST_GPU_A>;
547 vpu_mmu: iommu@20020800 {
548 compatible = "rockchip,iommu";
549 reg = <0x20020800 0x100>;
550 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
551 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
552 clock-names = "aclk", "iface";
557 vdec_mmu: iommu@20030480 {
558 compatible = "rockchip,iommu";
559 reg = <0x20030480 0x40>, <0x200304c0 0x40>;
560 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
561 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
562 clock-names = "aclk", "iface";
567 vop_mmu: iommu@20053f00 {
568 compatible = "rockchip,iommu";
569 reg = <0x20053f00 0x100>;
570 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
571 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
572 clock-names = "aclk", "iface";
577 iep_mmu: iommu@20070800 {
578 compatible = "rockchip,iommu";
579 reg = <0x20070800 0x100>;
580 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
581 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
582 clock-names = "aclk", "iface";
587 sdmmc: dwmmc@30000000 {
588 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
589 reg = <0x30000000 0x4000>;
590 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
591 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
592 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
593 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
594 fifo-depth = <0x100>;
595 pinctrl-names = "default";
596 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
600 sdio: dwmmc@30010000 {
601 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
602 reg = <0x30010000 0x4000>;
603 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
604 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
605 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
606 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
607 fifo-depth = <0x100>;
608 pinctrl-names = "default";
609 pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>;
613 emmc: dwmmc@30020000 {
614 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
615 reg = <0x30020000 0x4000>;
616 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
617 clock-frequency = <37500000>;
618 max-frequency = <37500000>;
619 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
620 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
621 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
623 default-sample-phase = <158>;
624 fifo-depth = <0x100>;
625 pinctrl-names = "default";
626 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
627 resets = <&cru SRST_EMMC>;
628 reset-names = "reset";
632 usb_otg: usb@30040000 {
633 compatible = "rockchip,rk3228-usb", "rockchip,rk3066-usb",
635 reg = <0x30040000 0x40000>;
636 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
637 clocks = <&cru HCLK_OTG>;
640 g-np-tx-fifo-size = <16>;
641 g-rx-fifo-size = <280>;
642 g-tx-fifo-size = <256 128 128 64 32 16>;
644 phys = <&u2phy0_otg>;
645 phy-names = "usb2-phy";
649 usb_host0_ehci: usb@30080000 {
650 compatible = "generic-ehci";
651 reg = <0x30080000 0x20000>;
652 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
653 clocks = <&cru HCLK_HOST0>, <&u2phy0>;
654 clock-names = "usbhost", "utmi";
655 phys = <&u2phy0_host>;
660 usb_host0_ohci: usb@300a0000 {
661 compatible = "generic-ohci";
662 reg = <0x300a0000 0x20000>;
663 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
664 clocks = <&cru HCLK_HOST0>, <&u2phy0>;
665 clock-names = "usbhost", "utmi";
666 phys = <&u2phy0_host>;
671 usb_host1_ehci: usb@300c0000 {
672 compatible = "generic-ehci";
673 reg = <0x300c0000 0x20000>;
674 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
675 clocks = <&cru HCLK_HOST1>, <&u2phy1>;
676 clock-names = "usbhost", "utmi";
677 phys = <&u2phy1_otg>;
682 usb_host1_ohci: usb@300e0000 {
683 compatible = "generic-ohci";
684 reg = <0x300e0000 0x20000>;
685 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
686 clocks = <&cru HCLK_HOST1>, <&u2phy1>;
687 clock-names = "usbhost", "utmi";
688 phys = <&u2phy1_otg>;
693 usb_host2_ehci: usb@30100000 {
694 compatible = "generic-ehci";
695 reg = <0x30100000 0x20000>;
696 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
697 clocks = <&cru HCLK_HOST2>, <&u2phy1>;
698 phys = <&u2phy1_host>;
700 clock-names = "usbhost", "utmi";
704 usb_host2_ohci: usb@30120000 {
705 compatible = "generic-ohci";
706 reg = <0x30120000 0x20000>;
707 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
708 clocks = <&cru HCLK_HOST2>, <&u2phy1>;
709 clock-names = "usbhost", "utmi";
710 phys = <&u2phy1_host>;
715 gmac: ethernet@30200000 {
716 compatible = "rockchip,rk3228-gmac";
717 reg = <0x30200000 0x10000>;
718 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
719 interrupt-names = "macirq";
720 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
721 <&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>,
722 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
724 clock-names = "stmmaceth", "mac_clk_rx",
725 "mac_clk_tx", "clk_mac_ref",
726 "clk_mac_refout", "aclk_mac",
728 resets = <&cru SRST_GMAC>;
729 reset-names = "stmmaceth";
730 rockchip,grf = <&grf>;
734 gic: interrupt-controller@32010000 {
735 compatible = "arm,gic-400";
736 interrupt-controller;
737 #interrupt-cells = <3>;
738 #address-cells = <0>;
740 reg = <0x32011000 0x1000>,
744 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
748 compatible = "rockchip,rk3228-pinctrl";
749 rockchip,grf = <&grf>;
750 #address-cells = <1>;
754 gpio0: gpio0@11110000 {
755 compatible = "rockchip,gpio-bank";
756 reg = <0x11110000 0x100>;
757 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
758 clocks = <&cru PCLK_GPIO0>;
763 interrupt-controller;
764 #interrupt-cells = <2>;
767 gpio1: gpio1@11120000 {
768 compatible = "rockchip,gpio-bank";
769 reg = <0x11120000 0x100>;
770 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
771 clocks = <&cru PCLK_GPIO1>;
776 interrupt-controller;
777 #interrupt-cells = <2>;
780 gpio2: gpio2@11130000 {
781 compatible = "rockchip,gpio-bank";
782 reg = <0x11130000 0x100>;
783 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
784 clocks = <&cru PCLK_GPIO2>;
789 interrupt-controller;
790 #interrupt-cells = <2>;
793 gpio3: gpio3@11140000 {
794 compatible = "rockchip,gpio-bank";
795 reg = <0x11140000 0x100>;
796 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
797 clocks = <&cru PCLK_GPIO3>;
802 interrupt-controller;
803 #interrupt-cells = <2>;
806 pcfg_pull_up: pcfg-pull-up {
810 pcfg_pull_down: pcfg-pull-down {
814 pcfg_pull_none: pcfg-pull-none {
818 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
819 drive-strength = <12>;
823 sdmmc_clk: sdmmc-clk {
824 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none_drv_12ma>;
827 sdmmc_cmd: sdmmc-cmd {
828 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_none_drv_12ma>;
831 sdmmc_bus4: sdmmc-bus4 {
832 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_none_drv_12ma>,
833 <1 RK_PC3 1 &pcfg_pull_none_drv_12ma>,
834 <1 RK_PC4 1 &pcfg_pull_none_drv_12ma>,
835 <1 RK_PC5 1 &pcfg_pull_none_drv_12ma>;
841 rockchip,pins = <3 RK_PA0 1 &pcfg_pull_none_drv_12ma>;
845 rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none_drv_12ma>;
848 sdio_bus4: sdio-bus4 {
849 rockchip,pins = <3 RK_PA2 1 &pcfg_pull_none_drv_12ma>,
850 <3 RK_PA3 1 &pcfg_pull_none_drv_12ma>,
851 <3 RK_PA4 1 &pcfg_pull_none_drv_12ma>,
852 <3 RK_PA5 1 &pcfg_pull_none_drv_12ma>;
858 rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>;
862 rockchip,pins = <1 22 RK_FUNC_2 &pcfg_pull_none>;
865 emmc_bus8: emmc-bus8 {
866 rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>,
867 <1 25 RK_FUNC_2 &pcfg_pull_none>,
868 <1 26 RK_FUNC_2 &pcfg_pull_none>,
869 <1 27 RK_FUNC_2 &pcfg_pull_none>,
870 <1 28 RK_FUNC_2 &pcfg_pull_none>,
871 <1 29 RK_FUNC_2 &pcfg_pull_none>,
872 <1 30 RK_FUNC_2 &pcfg_pull_none>,
873 <1 31 RK_FUNC_2 &pcfg_pull_none>;
878 rgmii_pins: rgmii-pins {
879 rockchip,pins = <2 14 RK_FUNC_1 &pcfg_pull_none>,
880 <2 12 RK_FUNC_1 &pcfg_pull_none>,
881 <2 25 RK_FUNC_1 &pcfg_pull_none>,
882 <2 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
883 <2 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
884 <2 22 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
885 <2 23 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
886 <2 9 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
887 <2 13 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
888 <2 17 RK_FUNC_1 &pcfg_pull_none>,
889 <2 16 RK_FUNC_1 &pcfg_pull_none>,
890 <2 21 RK_FUNC_2 &pcfg_pull_none>,
891 <2 20 RK_FUNC_2 &pcfg_pull_none>,
892 <2 11 RK_FUNC_1 &pcfg_pull_none>,
893 <2 8 RK_FUNC_1 &pcfg_pull_none>;
896 rmii_pins: rmii-pins {
897 rockchip,pins = <2 14 RK_FUNC_1 &pcfg_pull_none>,
898 <2 12 RK_FUNC_1 &pcfg_pull_none>,
899 <2 25 RK_FUNC_1 &pcfg_pull_none>,
900 <2 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
901 <2 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
902 <2 13 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
903 <2 17 RK_FUNC_1 &pcfg_pull_none>,
904 <2 16 RK_FUNC_1 &pcfg_pull_none>,
905 <2 8 RK_FUNC_1 &pcfg_pull_none>,
906 <2 15 RK_FUNC_1 &pcfg_pull_none>;
910 rockchip,pins = <2 14 RK_FUNC_2 &pcfg_pull_none>,
911 <2 8 RK_FUNC_2 &pcfg_pull_none>;
916 i2c0_xfer: i2c0-xfer {
917 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>,
918 <0 1 RK_FUNC_1 &pcfg_pull_none>;
923 i2c1_xfer: i2c1-xfer {
924 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>,
925 <0 3 RK_FUNC_1 &pcfg_pull_none>;
930 i2c2_xfer: i2c2-xfer {
931 rockchip,pins = <2 20 RK_FUNC_1 &pcfg_pull_none>,
932 <2 21 RK_FUNC_1 &pcfg_pull_none>;
937 i2c3_xfer: i2c3-xfer {
938 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
939 <0 7 RK_FUNC_1 &pcfg_pull_none>;
945 rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_up>;
948 rockchip,pins = <0 14 RK_FUNC_2 &pcfg_pull_up>;
951 rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
954 rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
957 rockchip,pins = <1 12 RK_FUNC_1 &pcfg_pull_up>;
963 rockchip,pins = <0 23 RK_FUNC_2 &pcfg_pull_up>;
966 rockchip,pins = <2 2 RK_FUNC_2 &pcfg_pull_up>;
969 rockchip,pins = <2 0 RK_FUNC_2 &pcfg_pull_up>;
972 rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_up>;
975 rockchip,pins = <2 3 RK_FUNC_2 &pcfg_pull_up>;
981 rockchip,pins = <0 8 RK_FUNC_1 &pcfg_pull_none>,
982 <0 9 RK_FUNC_1 &pcfg_pull_none>,
983 <0 11 RK_FUNC_1 &pcfg_pull_none>,
984 <0 12 RK_FUNC_1 &pcfg_pull_none>,
985 <0 13 RK_FUNC_1 &pcfg_pull_none>,
986 <0 14 RK_FUNC_1 &pcfg_pull_none>,
987 <1 2 RK_FUNC_2 &pcfg_pull_none>,
988 <1 4 RK_FUNC_2 &pcfg_pull_none>,
989 <1 5 RK_FUNC_2 &pcfg_pull_none>;
995 rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_none>;
1000 pwm1_pin: pwm1-pin {
1001 rockchip,pins = <0 30 RK_FUNC_2 &pcfg_pull_none>;
1006 pwm2_pin: pwm2-pin {
1007 rockchip,pins = <1 12 RK_FUNC_2 &pcfg_pull_none>;
1012 pwm3_pin: pwm3-pin {
1013 rockchip,pins = <1 11 RK_FUNC_2 &pcfg_pull_none>;
1018 spdif_tx: spdif-tx {
1019 rockchip,pins = <3 31 RK_FUNC_2 &pcfg_pull_none>;
1024 otp_gpio: otp-gpio {
1025 rockchip,pins = <0 24 RK_FUNC_GPIO &pcfg_pull_none>;
1029 rockchip,pins = <0 24 RK_FUNC_2 &pcfg_pull_none>;
1034 uart0_xfer: uart0-xfer {
1035 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>,
1036 <2 27 RK_FUNC_1 &pcfg_pull_none>;
1039 uart0_cts: uart0-cts {
1040 rockchip,pins = <2 29 RK_FUNC_1 &pcfg_pull_none>;
1043 uart0_rts: uart0-rts {
1044 rockchip,pins = <0 17 RK_FUNC_1 &pcfg_pull_none>;
1049 uart1_xfer: uart1-xfer {
1050 rockchip,pins = <1 9 RK_FUNC_1 &pcfg_pull_none>,
1051 <1 10 RK_FUNC_1 &pcfg_pull_none>;
1054 uart1_cts: uart1-cts {
1055 rockchip,pins = <1 8 RK_FUNC_1 &pcfg_pull_none>;
1058 uart1_rts: uart1-rts {
1059 rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>;
1064 uart2_xfer: uart2-xfer {
1065 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
1066 <1 19 RK_FUNC_2 &pcfg_pull_none>;
1069 uart21_xfer: uart21-xfer {
1070 rockchip,pins = <1 10 RK_FUNC_2 &pcfg_pull_up>,
1071 <1 9 RK_FUNC_2 &pcfg_pull_none>;
1074 uart2_cts: uart2-cts {
1075 rockchip,pins = <0 25 RK_FUNC_1 &pcfg_pull_none>;
1078 uart2_rts: uart2-rts {
1079 rockchip,pins = <0 24 RK_FUNC_1 &pcfg_pull_none>;