arch/arm/boot/dts/rk3188.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2013 MundoReader S.L.
   4  * Author: Heiko Stuebner <heiko@sntech.de>
   5  */
   6
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include <dt-bindings/pinctrl/rockchip.h>
   9 #include <dt-bindings/clock/rk3188-cru.h>
  10 #include <dt-bindings/power/rk3188-power.h>
  11 #include "rk3xxx.dtsi"
  12
  13 / {
  14         compatible = "rockchip,rk3188";
  15
  16         cpus {
  17                 #address-cells = <1>;
  18                 #size-cells = <0>;
  19                 enable-method = "rockchip,rk3066-smp";
  20
  21                 cpu0: cpu@0 {
  22                         device_type = "cpu";
  23                         compatible = "arm,cortex-a9";
  24                         next-level-cache = <&L2>;
  25                         reg = <0x0>;
  26                         clock-latency = <40000>;
  27                         clocks = <&cru ARMCLK>;
  28                         operating-points-v2 = <&cpu0_opp_table>;
  29                         resets = <&cru SRST_CORE0>;
  30                 };
  31                 cpu1: cpu@1 {
  32                         device_type = "cpu";
  33                         compatible = "arm,cortex-a9";
  34                         next-level-cache = <&L2>;
  35                         reg = <0x1>;
  36                         operating-points-v2 = <&cpu0_opp_table>;
  37                         resets = <&cru SRST_CORE1>;
  38                 };
  39                 cpu2: cpu@2 {
  40                         device_type = "cpu";
  41                         compatible = "arm,cortex-a9";
  42                         next-level-cache = <&L2>;
  43                         reg = <0x2>;
  44                         operating-points-v2 = <&cpu0_opp_table>;
  45                         resets = <&cru SRST_CORE2>;
  46                 };
  47                 cpu3: cpu@3 {
  48                         device_type = "cpu";
  49                         compatible = "arm,cortex-a9";
  50                         next-level-cache = <&L2>;
  51                         reg = <0x3>;
  52                         operating-points-v2 = <&cpu0_opp_table>;
  53                         resets = <&cru SRST_CORE3>;
  54                 };
  55         };
  56
  57         cpu0_opp_table: opp-table-0 {
  58                 compatible = "operating-points-v2";
  59                 opp-shared;
  60
  61                 opp-312000000 {
  62                         opp-hz = /bits/ 64 <312000000>;
  63                         opp-microvolt = <875000>;
  64                         clock-latency-ns = <40000>;
  65                 };
  66                 opp-504000000 {
  67                         opp-hz = /bits/ 64 <504000000>;
  68                         opp-microvolt = <925000>;
  69                 };
  70                 opp-600000000 {
  71                         opp-hz = /bits/ 64 <600000000>;
  72                         opp-microvolt = <950000>;
  73                         opp-suspend;
  74                 };
  75                 opp-816000000 {
  76                         opp-hz = /bits/ 64 <816000000>;
  77                         opp-microvolt = <975000>;
  78                 };
  79                 opp-1008000000 {
  80                         opp-hz = /bits/ 64 <1008000000>;
  81                         opp-microvolt = <1075000>;
  82                 };
  83                 opp-1200000000 {
  84                         opp-hz = /bits/ 64 <1200000000>;
  85                         opp-microvolt = <1150000>;
  86                 };
  87                 opp-1416000000 {
  88                         opp-hz = /bits/ 64 <1416000000>;
  89                         opp-microvolt = <1250000>;
  90                 };
  91                 opp-1608000000 {
  92                         opp-hz = /bits/ 64 <1608000000>;
  93                         opp-microvolt = <1350000>;
  94                 };
  95         };
  96
  97         display-subsystem {
  98                 compatible = "rockchip,display-subsystem";
  99                 ports = <&vop0_out>, <&vop1_out>;
 100         };
 101
 102         sram: sram@10080000 {
 103                 compatible = "mmio-sram";
 104                 reg = <0x10080000 0x8000>;
 105                 #address-cells = <1>;
 106                 #size-cells = <1>;
 107                 ranges = <0 0x10080000 0x8000>;
 108
 109                 smp-sram@0 {
 110                         compatible = "rockchip,rk3066-smp-sram";
 111                         reg = <0x0 0x50>;
 112                 };
 113         };
 114
 115         vop0: vop@1010c000 {
 116                 compatible = "rockchip,rk3188-vop";
 117                 reg = <0x1010c000 0x1000>;
 118                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 119                 clocks = <&cru ACLK_LCDC0>, <&cru DCLK_LCDC0>, <&cru HCLK_LCDC0>;
 120                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 121                 power-domains = <&power RK3188_PD_VIO>;
 122                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
 123                 reset-names = "axi", "ahb", "dclk";
 124                 status = "disabled";
 125
 126                 vop0_out: port {
 127                         #address-cells = <1>;
 128                         #size-cells = <0>;
 129                 };
 130         };
 131
 132         vop1: vop@1010e000 {
 133                 compatible = "rockchip,rk3188-vop";
 134                 reg = <0x1010e000 0x1000>;
 135                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 136                 clocks = <&cru ACLK_LCDC1>, <&cru DCLK_LCDC1>, <&cru HCLK_LCDC1>;
 137                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 138                 power-domains = <&power RK3188_PD_VIO>;
 139                 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
 140                 reset-names = "axi", "ahb", "dclk";
 141                 status = "disabled";
 142
 143                 vop1_out: port {
 144                         #address-cells = <1>;
 145                         #size-cells = <0>;
 146                 };
 147         };
 148
 149         timer3: timer@2000e000 {
 150                 compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
 151                 reg = <0x2000e000 0x20>;
 152                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 153                 clocks = <&cru PCLK_TIMER3>, <&cru SCLK_TIMER3>;
 154                 clock-names = "pclk", "timer";
 155         };
 156
 157         timer6: timer@200380a0 {
 158                 compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
 159                 reg = <0x200380a0 0x20>;
 160                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 161                 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER6>;
 162                 clock-names = "pclk", "timer";
 163         };
 164
 165         i2s0: i2s@1011a000 {
 166                 compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s";
 167                 reg = <0x1011a000 0x2000>;
 168                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 169                 pinctrl-names = "default";
 170                 pinctrl-0 = <&i2s0_bus>;
 171                 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>;
 172                 clock-names = "i2s_clk", "i2s_hclk";
 173                 dmas = <&dmac1_s 6>, <&dmac1_s 7>;
 174                 dma-names = "tx", "rx";
 175                 rockchip,playback-channels = <2>;
 176                 rockchip,capture-channels = <2>;
 177                 #sound-dai-cells = <0>;
 178                 status = "disabled";
 179         };
 180
 181         spdif: sound@1011e000 {
 182                 compatible = "rockchip,rk3188-spdif", "rockchip,rk3066-spdif";
 183                 reg = <0x1011e000 0x2000>;
 184                 #sound-dai-cells = <0>;
 185                 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF>;
 186                 clock-names = "mclk", "hclk";
 187                 dmas = <&dmac1_s 8>;
 188                 dma-names = "tx";
 189                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 190                 pinctrl-names = "default";
 191                 pinctrl-0 = <&spdif_tx>;
 192                 status = "disabled";
 193         };
 194
 195         cru: clock-controller@20000000 {
 196                 compatible = "rockchip,rk3188-cru";
 197                 reg = <0x20000000 0x1000>;
 198                 clocks = <&xin24m>;
 199                 clock-names = "xin24m";
 200                 rockchip,grf = <&grf>;
 201                 #clock-cells = <1>;
 202                 #reset-cells = <1>;
 203         };
 204
 205         efuse: efuse@20010000 {
 206                 compatible = "rockchip,rk3188-efuse";
 207                 reg = <0x20010000 0x4000>;
 208                 #address-cells = <1>;
 209                 #size-cells = <1>;
 210                 clocks = <&cru PCLK_EFUSE>;
 211                 clock-names = "pclk_efuse";
 212
 213                 cpu_leakage: cpu_leakage@17 {
 214                         reg = <0x17 0x1>;
 215                 };
 216         };
 217
 218         pinctrl: pinctrl {
 219                 compatible = "rockchip,rk3188-pinctrl";
 220                 rockchip,grf = <&grf>;
 221                 rockchip,pmu = <&pmu>;
 222
 223                 #address-cells = <1>;
 224                 #size-cells = <1>;
 225                 ranges;
 226
 227                 gpio0: gpio@2000a000 {
 228                         compatible = "rockchip,rk3188-gpio-bank0";
 229                         reg = <0x2000a000 0x100>;
 230                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 231                         clocks = <&cru PCLK_GPIO0>;
 232
 233                         gpio-controller;
 234                         #gpio-cells = <2>;
 235
 236                         interrupt-controller;
 237                         #interrupt-cells = <2>;
 238                 };
 239
 240                 gpio1: gpio@2003c000 {
 241                         compatible = "rockchip,gpio-bank";
 242                         reg = <0x2003c000 0x100>;
 243                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 244                         clocks = <&cru PCLK_GPIO1>;
 245
 246                         gpio-controller;
 247                         #gpio-cells = <2>;
 248
 249                         interrupt-controller;
 250                         #interrupt-cells = <2>;
 251                 };
 252
 253                 gpio2: gpio@2003e000 {
 254                         compatible = "rockchip,gpio-bank";
 255                         reg = <0x2003e000 0x100>;
 256                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 257                         clocks = <&cru PCLK_GPIO2>;
 258
 259                         gpio-controller;
 260                         #gpio-cells = <2>;
 261
 262                         interrupt-controller;
 263                         #interrupt-cells = <2>;
 264                 };
 265
 266                 gpio3: gpio@20080000 {
 267                         compatible = "rockchip,gpio-bank";
 268                         reg = <0x20080000 0x100>;
 269                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 270                         clocks = <&cru PCLK_GPIO3>;
 271
 272                         gpio-controller;
 273                         #gpio-cells = <2>;
 274
 275                         interrupt-controller;
 276                         #interrupt-cells = <2>;
 277                 };
 278
 279                 pcfg_pull_up: pcfg-pull-up {
 280                         bias-pull-up;
 281                 };
 282
 283                 pcfg_pull_down: pcfg-pull-down {
 284                         bias-pull-down;
 285                 };
 286
 287                 pcfg_pull_none: pcfg-pull-none {
 288                         bias-disable;
 289                 };
 290
 291                 emmc {
 292                         emmc_clk: emmc-clk {
 293                                 rockchip,pins = <0 RK_PD0 2 &pcfg_pull_none>;
 294                         };
 295
 296                         emmc_cmd: emmc-cmd {
 297                                 rockchip,pins = <0 RK_PD2 2 &pcfg_pull_up>;
 298                         };
 299
 300                         emmc_rst: emmc-rst {
 301                                 rockchip,pins = <0 RK_PD3 2 &pcfg_pull_none>;
 302                         };
 303
 304                         /*
 305                          * The data pins are shared between nandc and emmc and
 306                          * not accessible through pinctrl. Also they should've
 307                          * been already set correctly by firmware, as
 308                          * flash/emmc is the boot-device.
 309                          */
 310                 };
 311
 312                 emac {
 313                         emac_xfer: emac-xfer {
 314                                 rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none>, /* tx_en */
 315                                                 <3 RK_PC1 2 &pcfg_pull_none>, /* txd1 */
 316                                                 <3 RK_PC2 2 &pcfg_pull_none>, /* txd0 */
 317                                                 <3 RK_PC3 2 &pcfg_pull_none>, /* rxd0 */
 318                                                 <3 RK_PC4 2 &pcfg_pull_none>, /* rxd1 */
 319                                                 <3 RK_PC5 2 &pcfg_pull_none>, /* mac_clk */
 320                                                 <3 RK_PC6 2 &pcfg_pull_none>, /* rx_err */
 321                                                 <3 RK_PC7 2 &pcfg_pull_none>; /* crs_dvalid */
 322                         };
 323
 324                         emac_mdio: emac-mdio {
 325                                 rockchip,pins = <3 RK_PD0 2 &pcfg_pull_none>,
 326                                                 <3 RK_PD1 2 &pcfg_pull_none>;
 327                         };
 328                 };
 329
 330                 i2c0 {
 331                         i2c0_xfer: i2c0-xfer {
 332                                 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>,
 333                                                 <1 RK_PD1 1 &pcfg_pull_none>;
 334                         };
 335                 };
 336
 337                 i2c1 {
 338                         i2c1_xfer: i2c1-xfer {
 339                                 rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>,
 340                                                 <1 RK_PD3 1 &pcfg_pull_none>;
 341                         };
 342                 };
 343
 344                 i2c2 {
 345                         i2c2_xfer: i2c2-xfer {
 346                                 rockchip,pins = <1 RK_PD4 1 &pcfg_pull_none>,
 347                                                 <1 RK_PD5 1 &pcfg_pull_none>;
 348                         };
 349                 };
 350
 351                 i2c3 {
 352                         i2c3_xfer: i2c3-xfer {
 353                                 rockchip,pins = <3 RK_PB6 2 &pcfg_pull_none>,
 354                                                 <3 RK_PB7 2 &pcfg_pull_none>;
 355                         };
 356                 };
 357
 358                 i2c4 {
 359                         i2c4_xfer: i2c4-xfer {
 360                                 rockchip,pins = <1 RK_PD6 1 &pcfg_pull_none>,
 361                                                 <1 RK_PD7 1 &pcfg_pull_none>;
 362                         };
 363                 };
 364
 365                 lcdc1 {
 366                         lcdc1_dclk: lcdc1-dclk {
 367                                 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>;
 368                         };
 369
 370                         lcdc1_den: lcdc1-den {
 371                                 rockchip,pins = <2 RK_PD1 1 &pcfg_pull_none>;
 372                         };
 373
 374                         lcdc1_hsync: lcdc1-hsync {
 375                                 rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>;
 376                         };
 377
 378                         lcdc1_vsync: lcdc1-vsync {
 379                                 rockchip,pins = <2 RK_PD3 1 &pcfg_pull_none>;
 380                         };
 381
 382                         lcdc1_rgb24: lcdc1-rgb24 {
 383                                 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>,
 384                                                 <2 RK_PA1 1 &pcfg_pull_none>,
 385                                                 <2 RK_PA2 1 &pcfg_pull_none>,
 386                                                 <2 RK_PA3 1 &pcfg_pull_none>,
 387                                                 <2 RK_PA4 1 &pcfg_pull_none>,
 388                                                 <2 RK_PA5 1 &pcfg_pull_none>,
 389                                                 <2 RK_PA6 1 &pcfg_pull_none>,
 390                                                 <2 RK_PA7 1 &pcfg_pull_none>,
 391                                                 <2 RK_PB0 1 &pcfg_pull_none>,
 392                                                 <2 RK_PB1 1 &pcfg_pull_none>,
 393                                                 <2 RK_PB2 1 &pcfg_pull_none>,
 394                                                 <2 RK_PB3 1 &pcfg_pull_none>,
 395                                                 <2 RK_PB4 1 &pcfg_pull_none>,
 396                                                 <2 RK_PB5 1 &pcfg_pull_none>,
 397                                                 <2 RK_PB6 1 &pcfg_pull_none>,
 398                                                 <2 RK_PB7 1 &pcfg_pull_none>,
 399                                                 <2 RK_PC0 1 &pcfg_pull_none>,
 400                                                 <2 RK_PC1 1 &pcfg_pull_none>,
 401                                                 <2 RK_PC2 1 &pcfg_pull_none>,
 402                                                 <2 RK_PC3 1 &pcfg_pull_none>,
 403                                                 <2 RK_PC4 1 &pcfg_pull_none>,
 404                                                 <2 RK_PC5 1 &pcfg_pull_none>,
 405                                                 <2 RK_PC6 1 &pcfg_pull_none>,
 406                                                 <2 RK_PC7 1 &pcfg_pull_none>;
 407                         };
 408                 };
 409
 410                 pwm0 {
 411                         pwm0_out: pwm0-out {
 412                                 rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>;
 413                         };
 414                 };
 415
 416                 pwm1 {
 417                         pwm1_out: pwm1-out {
 418                                 rockchip,pins = <3 RK_PD4 1 &pcfg_pull_none>;
 419                         };
 420                 };
 421
 422                 pwm2 {
 423                         pwm2_out: pwm2-out {
 424                                 rockchip,pins = <3 RK_PD5 1 &pcfg_pull_none>;
 425                         };
 426                 };
 427
 428                 pwm3 {
 429                         pwm3_out: pwm3-out {
 430                                 rockchip,pins = <3 RK_PD6 1 &pcfg_pull_none>;
 431                         };
 432                 };
 433
 434                 spi0 {
 435                         spi0_clk: spi0-clk {
 436                                 rockchip,pins = <1 RK_PA6 2 &pcfg_pull_up>;
 437                         };
 438                         spi0_cs0: spi0-cs0 {
 439                                 rockchip,pins = <1 RK_PA7 2 &pcfg_pull_up>;
 440                         };
 441                         spi0_tx: spi0-tx {
 442                                 rockchip,pins = <1 RK_PA5 2 &pcfg_pull_up>;
 443                         };
 444                         spi0_rx: spi0-rx {
 445                                 rockchip,pins = <1 RK_PA4 2 &pcfg_pull_up>;
 446                         };
 447                         spi0_cs1: spi0-cs1 {
 448                                 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_up>;
 449                         };
 450                 };
 451
 452                 spi1 {
 453                         spi1_clk: spi1-clk {
 454                                 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_up>;
 455                         };
 456                         spi1_cs0: spi1-cs0 {
 457                                 rockchip,pins = <0 RK_PD7 1 &pcfg_pull_up>;
 458                         };
 459                         spi1_rx: spi1-rx {
 460                                 rockchip,pins = <0 RK_PD4 1 &pcfg_pull_up>;
 461                         };
 462                         spi1_tx: spi1-tx {
 463                                 rockchip,pins = <0 RK_PD5 1 &pcfg_pull_up>;
 464                         };
 465                         spi1_cs1: spi1-cs1 {
 466                                 rockchip,pins = <1 RK_PB6 2 &pcfg_pull_up>;
 467                         };
 468                 };
 469
 470                 uart0 {
 471                         uart0_xfer: uart0-xfer {
 472                                 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up>,
 473                                                 <1 RK_PA1 1 &pcfg_pull_none>;
 474                         };
 475
 476                         uart0_cts: uart0-cts {
 477                                 rockchip,pins = <1 RK_PA2 1 &pcfg_pull_none>;
 478                         };
 479
 480                         uart0_rts: uart0-rts {
 481                                 rockchip,pins = <1 RK_PA3 1 &pcfg_pull_none>;
 482                         };
 483                 };
 484
 485                 uart1 {
 486                         uart1_xfer: uart1-xfer {
 487                                 rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up>,
 488                                                 <1 RK_PA5 1 &pcfg_pull_none>;
 489                         };
 490
 491                         uart1_cts: uart1-cts {
 492                                 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none>;
 493                         };
 494
 495                         uart1_rts: uart1-rts {
 496                                 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_none>;
 497                         };
 498                 };
 499
 500                 uart2 {
 501                         uart2_xfer: uart2-xfer {
 502                                 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_up>,
 503                                                 <1 RK_PB1 1 &pcfg_pull_none>;
 504                         };
 505                         /* no rts / cts for uart2 */
 506                 };
 507
 508                 uart3 {
 509                         uart3_xfer: uart3-xfer {
 510                                 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_up>,
 511                                                 <1 RK_PB3 1 &pcfg_pull_none>;
 512                         };
 513
 514                         uart3_cts: uart3-cts {
 515                                 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none>;
 516                         };
 517
 518                         uart3_rts: uart3-rts {
 519                                 rockchip,pins = <1 RK_PB5 1 &pcfg_pull_none>;
 520                         };
 521                 };
 522
 523                 sd0 {
 524                         sd0_clk: sd0-clk {
 525                                 rockchip,pins = <3 RK_PA2 1 &pcfg_pull_none>;
 526                         };
 527
 528                         sd0_cmd: sd0-cmd {
 529                                 rockchip,pins = <3 RK_PA3 1 &pcfg_pull_none>;
 530                         };
 531
 532                         sd0_cd: sd0-cd {
 533                                 rockchip,pins = <3 RK_PB0 1 &pcfg_pull_none>;
 534                         };
 535
 536                         sd0_wp: sd0-wp {
 537                                 rockchip,pins = <3 RK_PB1 1 &pcfg_pull_none>;
 538                         };
 539
 540                         sd0_pwr: sd0-pwr {
 541                                 rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none>;
 542                         };
 543
 544                         sd0_bus1: sd0-bus-width1 {
 545                                 rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>;
 546                         };
 547
 548                         sd0_bus4: sd0-bus-width4 {
 549                                 rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>,
 550                                                 <3 RK_PA5 1 &pcfg_pull_none>,
 551                                                 <3 RK_PA6 1 &pcfg_pull_none>,
 552                                                 <3 RK_PA7 1 &pcfg_pull_none>;
 553                         };
 554                 };
 555
 556                 sd1 {
 557                         sd1_clk: sd1-clk {
 558                                 rockchip,pins = <3 RK_PC5 1 &pcfg_pull_none>;
 559                         };
 560
 561                         sd1_cmd: sd1-cmd {
 562                                 rockchip,pins = <3 RK_PC0 1 &pcfg_pull_none>;
 563                         };
 564
 565                         sd1_cd: sd1-cd {
 566                                 rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>;
 567                         };
 568
 569                         sd1_wp: sd1-wp {
 570                                 rockchip,pins = <3 RK_PC7 1 &pcfg_pull_none>;
 571                         };
 572
 573                         sd1_bus1: sd1-bus-width1 {
 574                                 rockchip,pins = <3 RK_PC1 1 &pcfg_pull_none>;
 575                         };
 576
 577                         sd1_bus4: sd1-bus-width4 {
 578                                 rockchip,pins = <3 RK_PC1 1 &pcfg_pull_none>,
 579                                                 <3 RK_PC2 1 &pcfg_pull_none>,
 580                                                 <3 RK_PC3 1 &pcfg_pull_none>,
 581                                                 <3 RK_PC4 1 &pcfg_pull_none>;
 582                         };
 583                 };
 584
 585                 i2s0 {
 586                         i2s0_bus: i2s0-bus {
 587                                 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>,
 588                                                 <1 RK_PC1 1 &pcfg_pull_none>,
 589                                                 <1 RK_PC2 1 &pcfg_pull_none>,
 590                                                 <1 RK_PC3 1 &pcfg_pull_none>,
 591                                                 <1 RK_PC4 1 &pcfg_pull_none>,
 592                                                 <1 RK_PC5 1 &pcfg_pull_none>;
 593                         };
 594                 };
 595
 596                 spdif {
 597                         spdif_tx: spdif-tx {
 598                                 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_none>;
 599                         };
 600                 };
 601         };
 602 };
 603
 604 &emac {
 605         compatible = "rockchip,rk3188-emac";
 606 };
 607
 608 &global_timer {
 609         interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
 610 };
 611
 612 &local_timer {
 613         interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
 614 };
 615
 616 &gpu {
 617         compatible = "rockchip,rk3188-mali", "arm,mali-400";
 618         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 619                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 620                      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 621                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 622                      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 623                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 624                      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 625                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 626                      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 627                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 628         interrupt-names = "gp",
 629                           "gpmmu",
 630                           "pp0",
 631                           "ppmmu0",
 632                           "pp1",
 633                           "ppmmu1",
 634                           "pp2",
 635                           "ppmmu2",
 636                           "pp3",
 637                           "ppmmu3";
 638         power-domains = <&power RK3188_PD_GPU>;
 639 };
 640
 641 &grf {
 642         compatible = "rockchip,rk3188-grf", "syscon", "simple-mfd";
 643
 644         io_domains: io-domains {
 645                 compatible = "rockchip,rk3188-io-voltage-domain";
 646                 status = "disabled";
 647         };
 648
 649         usbphy: usbphy {
 650                 compatible = "rockchip,rk3188-usb-phy";
 651                 #address-cells = <1>;
 652                 #size-cells = <0>;
 653                 status = "disabled";
 654
 655                 usbphy0: usb-phy@10c {
 656                         reg = <0x10c>;
 657                         clocks = <&cru SCLK_OTGPHY0>;
 658                         clock-names = "phyclk";
 659                         #clock-cells = <0>;
 660                         #phy-cells = <0>;
 661                 };
 662
 663                 usbphy1: usb-phy@11c {
 664                         reg = <0x11c>;
 665                         clocks = <&cru SCLK_OTGPHY1>;
 666                         clock-names = "phyclk";
 667                         #clock-cells = <0>;
 668                         #phy-cells = <0>;
 669                 };
 670         };
 671 };
 672
 673 &i2c0 {
 674         compatible = "rockchip,rk3188-i2c";
 675         pinctrl-names = "default";
 676         pinctrl-0 = <&i2c0_xfer>;
 677 };
 678
 679 &i2c1 {
 680         compatible = "rockchip,rk3188-i2c";
 681         pinctrl-names = "default";
 682         pinctrl-0 = <&i2c1_xfer>;
 683 };
 684
 685 &i2c2 {
 686         compatible = "rockchip,rk3188-i2c";
 687         pinctrl-names = "default";
 688         pinctrl-0 = <&i2c2_xfer>;
 689 };
 690
 691 &i2c3 {
 692         compatible = "rockchip,rk3188-i2c";
 693         pinctrl-names = "default";
 694         pinctrl-0 = <&i2c3_xfer>;
 695 };
 696
 697 &i2c4 {
 698         compatible = "rockchip,rk3188-i2c";
 699         pinctrl-names = "default";
 700         pinctrl-0 = <&i2c4_xfer>;
 701 };
 702
 703 &pmu {
 704         power: power-controller {
 705                 compatible = "rockchip,rk3188-power-controller";
 706                 #power-domain-cells = <1>;
 707                 #address-cells = <1>;
 708                 #size-cells = <0>;
 709
 710                 power-domain@RK3188_PD_VIO {
 711                         reg = <RK3188_PD_VIO>;
 712                         clocks = <&cru ACLK_LCDC0>,
 713                                  <&cru ACLK_LCDC1>,
 714                                  <&cru DCLK_LCDC0>,
 715                                  <&cru DCLK_LCDC1>,
 716                                  <&cru HCLK_LCDC0>,
 717                                  <&cru HCLK_LCDC1>,
 718                                  <&cru SCLK_CIF0>,
 719                                  <&cru ACLK_CIF0>,
 720                                  <&cru HCLK_CIF0>,
 721                                  <&cru ACLK_IPP>,
 722                                  <&cru HCLK_IPP>,
 723                                  <&cru ACLK_RGA>,
 724                                  <&cru HCLK_RGA>;
 725                         pm_qos = <&qos_lcdc0>,
 726                                  <&qos_lcdc1>,
 727                                  <&qos_cif0>,
 728                                  <&qos_ipp>,
 729                                  <&qos_rga>;
 730                         #power-domain-cells = <0>;
 731                 };
 732
 733                 power-domain@RK3188_PD_VIDEO {
 734                         reg = <RK3188_PD_VIDEO>;
 735                         clocks = <&cru ACLK_VDPU>,
 736                                  <&cru ACLK_VEPU>,
 737                                  <&cru HCLK_VDPU>,
 738                                  <&cru HCLK_VEPU>;
 739                         pm_qos = <&qos_vpu>;
 740                         #power-domain-cells = <0>;
 741                 };
 742
 743                 power-domain@RK3188_PD_GPU {
 744                         reg = <RK3188_PD_GPU>;
 745                         clocks = <&cru ACLK_GPU>;
 746                         pm_qos = <&qos_gpu>;
 747                         #power-domain-cells = <0>;
 748                 };
 749         };
 750 };
 751
 752 &pwm0 {
 753         pinctrl-names = "default";
 754         pinctrl-0 = <&pwm0_out>;
 755 };
 756
 757 &pwm1 {
 758         pinctrl-names = "default";
 759         pinctrl-0 = <&pwm1_out>;
 760 };
 761
 762 &pwm2 {
 763         pinctrl-names = "default";
 764         pinctrl-0 = <&pwm2_out>;
 765 };
 766
 767 &pwm3 {
 768         pinctrl-names = "default";
 769         pinctrl-0 = <&pwm3_out>;
 770 };
 771
 772 &spi0 {
 773         compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
 774         pinctrl-names = "default";
 775         pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 776 };
 777
 778 &spi1 {
 779         compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
 780         pinctrl-names = "default";
 781         pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 782 };
 783
 784 &uart0 {
 785         compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
 786         pinctrl-names = "default";
 787         pinctrl-0 = <&uart0_xfer>;
 788 };
 789
 790 &uart1 {
 791         compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
 792         pinctrl-names = "default";
 793         pinctrl-0 = <&uart1_xfer>;
 794 };
 795
 796 &uart2 {
 797         compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
 798         pinctrl-names = "default";
 799         pinctrl-0 = <&uart2_xfer>;
 800 };
 801
 802 &uart3 {
 803         compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
 804         pinctrl-names = "default";
 805         pinctrl-0 = <&uart3_xfer>;
 806 };
 807
 808 &vpu {
 809         compatible = "rockchip,rk3188-vpu", "rockchip,rk3066-vpu";
 810         power-domains = <&power RK3188_PD_VIDEO>;
 811 };
 812
 813 &wdt {
 814         compatible = "rockchip,rk3188-wdt", "snps,dw-wdt";
 815 };