arch/arm/boot/dts/rk3188.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2013 MundoReader S.L.
   4  * Author: Heiko Stuebner <heiko@sntech.de>
   5  */
   6
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include <dt-bindings/pinctrl/rockchip.h>
   9 #include <dt-bindings/clock/rk3188-cru.h>
  10 #include "rk3xxx.dtsi"
  11
  12 / {
  13         compatible = "rockchip,rk3188";
  14
  15         cpus {
  16                 #address-cells = <1>;
  17                 #size-cells = <0>;
  18                 enable-method = "rockchip,rk3066-smp";
  19
  20                 cpu0: cpu@0 {
  21                         device_type = "cpu";
  22                         compatible = "arm,cortex-a9";
  23                         next-level-cache = <&L2>;
  24                         reg = <0x0>;
  25                         operating-points = <
  26                                 /* kHz    uV */
  27                                 1608000 1350000
  28                                 1416000 1250000
  29                                 1200000 1150000
  30                                 1008000 1075000
  31                                  816000  975000
  32                                  600000  950000
  33                                  504000  925000
  34                                  312000  875000
  35                         >;
  36                         clock-latency = <40000>;
  37                         clocks = <&cru ARMCLK>;
  38                 };
  39                 cpu@1 {
  40                         device_type = "cpu";
  41                         compatible = "arm,cortex-a9";
  42                         next-level-cache = <&L2>;
  43                         reg = <0x1>;
  44                 };
  45                 cpu@2 {
  46                         device_type = "cpu";
  47                         compatible = "arm,cortex-a9";
  48                         next-level-cache = <&L2>;
  49                         reg = <0x2>;
  50                 };
  51                 cpu@3 {
  52                         device_type = "cpu";
  53                         compatible = "arm,cortex-a9";
  54                         next-level-cache = <&L2>;
  55                         reg = <0x3>;
  56                 };
  57         };
  58
  59         sram: sram@10080000 {
  60                 compatible = "mmio-sram";
  61                 reg = <0x10080000 0x8000>;
  62                 #address-cells = <1>;
  63                 #size-cells = <1>;
  64                 ranges = <0 0x10080000 0x8000>;
  65
  66                 smp-sram@0 {
  67                         compatible = "rockchip,rk3066-smp-sram";
  68                         reg = <0x0 0x50>;
  69                 };
  70         };
  71
  72         timer3: timer@2000e000 {
  73                 compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
  74                 reg = <0x2000e000 0x20>;
  75                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
  76                 clocks = <&cru PCLK_TIMER3>, <&cru SCLK_TIMER3>;
  77                 clock-names = "pclk", "timer";
  78         };
  79
  80         timer6: timer@200380a0 {
  81                 compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
  82                 reg = <0x200380a0 0x20>;
  83                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
  84                 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER6>;
  85                 clock-names = "pclk", "timer";
  86         };
  87
  88         i2s0: i2s@1011a000 {
  89                 compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s";
  90                 reg = <0x1011a000 0x2000>;
  91                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
  92                 #address-cells = <1>;
  93                 #size-cells = <0>;
  94                 pinctrl-names = "default";
  95                 pinctrl-0 = <&i2s0_bus>;
  96                 dmas = <&dmac1_s 6>, <&dmac1_s 7>;
  97                 dma-names = "tx", "rx";
  98                 clock-names = "i2s_hclk", "i2s_clk";
  99                 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
 100                 rockchip,playback-channels = <2>;
 101                 rockchip,capture-channels = <2>;
 102                 status = "disabled";
 103         };
 104
 105         spdif: sound@1011e000 {
 106                 compatible = "rockchip,rk3188-spdif", "rockchip,rk3066-spdif";
 107                 reg = <0x1011e000 0x2000>;
 108                 #sound-dai-cells = <0>;
 109                 clock-names = "hclk", "mclk";
 110                 clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF>;
 111                 dmas = <&dmac1_s 8>;
 112                 dma-names = "tx";
 113                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 114                 pinctrl-names = "default";
 115                 pinctrl-0 = <&spdif_tx>;
 116                 status = "disabled";
 117         };
 118
 119         cru: clock-controller@20000000 {
 120                 compatible = "rockchip,rk3188-cru";
 121                 reg = <0x20000000 0x1000>;
 122                 rockchip,grf = <&grf>;
 123
 124                 #clock-cells = <1>;
 125                 #reset-cells = <1>;
 126         };
 127
 128         efuse: efuse@20010000 {
 129                 compatible = "rockchip,rk3188-efuse";
 130                 reg = <0x20010000 0x4000>;
 131                 #address-cells = <1>;
 132                 #size-cells = <1>;
 133                 clocks = <&cru PCLK_EFUSE>;
 134                 clock-names = "pclk_efuse";
 135
 136                 cpu_leakage: cpu_leakage@17 {
 137                         reg = <0x17 0x1>;
 138                 };
 139         };
 140
 141         usbphy: phy {
 142                 compatible = "rockchip,rk3188-usb-phy", "rockchip,rk3288-usb-phy";
 143                 rockchip,grf = <&grf>;
 144                 #address-cells = <1>;
 145                 #size-cells = <0>;
 146                 status = "disabled";
 147
 148                 usbphy0: usb-phy@10c {
 149                         #phy-cells = <0>;
 150                         reg = <0x10c>;
 151                         clocks = <&cru SCLK_OTGPHY0>;
 152                         clock-names = "phyclk";
 153                         #clock-cells = <0>;
 154                 };
 155
 156                 usbphy1: usb-phy@11c {
 157                         #phy-cells = <0>;
 158                         reg = <0x11c>;
 159                         clocks = <&cru SCLK_OTGPHY1>;
 160                         clock-names = "phyclk";
 161                         #clock-cells = <0>;
 162                 };
 163         };
 164
 165         pinctrl: pinctrl {
 166                 compatible = "rockchip,rk3188-pinctrl";
 167                 rockchip,grf = <&grf>;
 168                 rockchip,pmu = <&pmu>;
 169
 170                 #address-cells = <1>;
 171                 #size-cells = <1>;
 172                 ranges;
 173
 174                 gpio0: gpio0@2000a000 {
 175                         compatible = "rockchip,rk3188-gpio-bank0";
 176                         reg = <0x2000a000 0x100>;
 177                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 178                         clocks = <&cru PCLK_GPIO0>;
 179
 180                         gpio-controller;
 181                         #gpio-cells = <2>;
 182
 183                         interrupt-controller;
 184                         #interrupt-cells = <2>;
 185                 };
 186
 187                 gpio1: gpio1@2003c000 {
 188                         compatible = "rockchip,gpio-bank";
 189                         reg = <0x2003c000 0x100>;
 190                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 191                         clocks = <&cru PCLK_GPIO1>;
 192
 193                         gpio-controller;
 194                         #gpio-cells = <2>;
 195
 196                         interrupt-controller;
 197                         #interrupt-cells = <2>;
 198                 };
 199
 200                 gpio2: gpio2@2003e000 {
 201                         compatible = "rockchip,gpio-bank";
 202                         reg = <0x2003e000 0x100>;
 203                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 204                         clocks = <&cru PCLK_GPIO2>;
 205
 206                         gpio-controller;
 207                         #gpio-cells = <2>;
 208
 209                         interrupt-controller;
 210                         #interrupt-cells = <2>;
 211                 };
 212
 213                 gpio3: gpio3@20080000 {
 214                         compatible = "rockchip,gpio-bank";
 215                         reg = <0x20080000 0x100>;
 216                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 217                         clocks = <&cru PCLK_GPIO3>;
 218
 219                         gpio-controller;
 220                         #gpio-cells = <2>;
 221
 222                         interrupt-controller;
 223                         #interrupt-cells = <2>;
 224                 };
 225
 226                 pcfg_pull_up: pcfg_pull_up {
 227                         bias-pull-up;
 228                 };
 229
 230                 pcfg_pull_down: pcfg_pull_down {
 231                         bias-pull-down;
 232                 };
 233
 234                 pcfg_pull_none: pcfg_pull_none {
 235                         bias-disable;
 236                 };
 237
 238                 emmc {
 239                         emmc_clk: emmc-clk {
 240                                 rockchip,pins = <RK_GPIO0 24 RK_FUNC_2 &pcfg_pull_none>;
 241                         };
 242
 243                         emmc_cmd: emmc-cmd {
 244                                 rockchip,pins = <RK_GPIO0 26 RK_FUNC_2 &pcfg_pull_up>;
 245                         };
 246
 247                         emmc_rst: emmc-rst {
 248                                 rockchip,pins = <RK_GPIO0 27 RK_FUNC_2 &pcfg_pull_none>;
 249                         };
 250
 251                         /*
 252                          * The data pins are shared between nandc and emmc and
 253                          * not accessible through pinctrl. Also they should've
 254                          * been already set correctly by firmware, as
 255                          * flash/emmc is the boot-device.
 256                          */
 257                 };
 258
 259                 emac {
 260                         emac_xfer: emac-xfer {
 261                                 rockchip,pins = <RK_GPIO3 16 RK_FUNC_2 &pcfg_pull_none>, /* tx_en */
 262                                                 <RK_GPIO3 17 RK_FUNC_2 &pcfg_pull_none>, /* txd1 */
 263                                                 <RK_GPIO3 18 RK_FUNC_2 &pcfg_pull_none>, /* txd0 */
 264                                                 <RK_GPIO3 19 RK_FUNC_2 &pcfg_pull_none>, /* rxd0 */
 265                                                 <RK_GPIO3 20 RK_FUNC_2 &pcfg_pull_none>, /* rxd1 */
 266                                                 <RK_GPIO3 21 RK_FUNC_2 &pcfg_pull_none>, /* mac_clk */
 267                                                 <RK_GPIO3 22 RK_FUNC_2 &pcfg_pull_none>, /* rx_err */
 268                                                 <RK_GPIO3 23 RK_FUNC_2 &pcfg_pull_none>; /* crs_dvalid */
 269                         };
 270
 271                         emac_mdio: emac-mdio {
 272                                 rockchip,pins = <RK_GPIO3 24 RK_FUNC_2 &pcfg_pull_none>,
 273                                                 <RK_GPIO3 25 RK_FUNC_2 &pcfg_pull_none>;
 274                         };
 275                 };
 276
 277                 i2c0 {
 278                         i2c0_xfer: i2c0-xfer {
 279                                 rockchip,pins = <RK_GPIO1 24 RK_FUNC_1 &pcfg_pull_none>,
 280                                                 <RK_GPIO1 25 RK_FUNC_1 &pcfg_pull_none>;
 281                         };
 282                 };
 283
 284                 i2c1 {
 285                         i2c1_xfer: i2c1-xfer {
 286                                 rockchip,pins = <RK_GPIO1 26 RK_FUNC_1 &pcfg_pull_none>,
 287                                                 <RK_GPIO1 27 RK_FUNC_1 &pcfg_pull_none>;
 288                         };
 289                 };
 290
 291                 i2c2 {
 292                         i2c2_xfer: i2c2-xfer {
 293                                 rockchip,pins = <RK_GPIO1 28 RK_FUNC_1 &pcfg_pull_none>,
 294                                                 <RK_GPIO1 29 RK_FUNC_1 &pcfg_pull_none>;
 295                         };
 296                 };
 297
 298                 i2c3 {
 299                         i2c3_xfer: i2c3-xfer {
 300                                 rockchip,pins = <RK_GPIO3 14 RK_FUNC_2 &pcfg_pull_none>,
 301                                                 <RK_GPIO3 15 RK_FUNC_2 &pcfg_pull_none>;
 302                         };
 303                 };
 304
 305                 i2c4 {
 306                         i2c4_xfer: i2c4-xfer {
 307                                 rockchip,pins = <RK_GPIO1 30 RK_FUNC_1 &pcfg_pull_none>,
 308                                                 <RK_GPIO1 31 RK_FUNC_1 &pcfg_pull_none>;
 309                         };
 310                 };
 311
 312                 pwm0 {
 313                         pwm0_out: pwm0-out {
 314                                 rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_none>;
 315                         };
 316                 };
 317
 318                 pwm1 {
 319                         pwm1_out: pwm1-out {
 320                                 rockchip,pins = <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_none>;
 321                         };
 322                 };
 323
 324                 pwm2 {
 325                         pwm2_out: pwm2-out {
 326                                 rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_none>;
 327                         };
 328                 };
 329
 330                 pwm3 {
 331                         pwm3_out: pwm3-out {
 332                                 rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_none>;
 333                         };
 334                 };
 335
 336                 spi0 {
 337                         spi0_clk: spi0-clk {
 338                                 rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_up>;
 339                         };
 340                         spi0_cs0: spi0-cs0 {
 341                                 rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_up>;
 342                         };
 343                         spi0_tx: spi0-tx {
 344                                 rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_up>;
 345                         };
 346                         spi0_rx: spi0-rx {
 347                                 rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_up>;
 348                         };
 349                         spi0_cs1: spi0-cs1 {
 350                                 rockchip,pins = <RK_GPIO1 15 RK_FUNC_1 &pcfg_pull_up>;
 351                         };
 352                 };
 353
 354                 spi1 {
 355                         spi1_clk: spi1-clk {
 356                                 rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_up>;
 357                         };
 358                         spi1_cs0: spi1-cs0 {
 359                                 rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_up>;
 360                         };
 361                         spi1_rx: spi1-rx {
 362                                 rockchip,pins = <RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_up>;
 363                         };
 364                         spi1_tx: spi1-tx {
 365                                 rockchip,pins = <RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_up>;
 366                         };
 367                         spi1_cs1: spi1-cs1 {
 368                                 rockchip,pins = <RK_GPIO1 14 RK_FUNC_2 &pcfg_pull_up>;
 369                         };
 370                 };
 371
 372                 uart0 {
 373                         uart0_xfer: uart0-xfer {
 374                                 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>,
 375                                                 <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>;
 376                         };
 377
 378                         uart0_cts: uart0-cts {
 379                                 rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_none>;
 380                         };
 381
 382                         uart0_rts: uart0-rts {
 383                                 rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_none>;
 384                         };
 385                 };
 386
 387                 uart1 {
 388                         uart1_xfer: uart1-xfer {
 389                                 rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_up>,
 390                                                 <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>;
 391                         };
 392
 393                         uart1_cts: uart1-cts {
 394                                 rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_none>;
 395                         };
 396
 397                         uart1_rts: uart1-rts {
 398                                 rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_none>;
 399                         };
 400                 };
 401
 402                 uart2 {
 403                         uart2_xfer: uart2-xfer {
 404                                 rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_up>,
 405                                                 <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>;
 406                         };
 407                         /* no rts / cts for uart2 */
 408                 };
 409
 410                 uart3 {
 411                         uart3_xfer: uart3-xfer {
 412                                 rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_up>,
 413                                                 <RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>;
 414                         };
 415
 416                         uart3_cts: uart3-cts {
 417                                 rockchip,pins = <RK_GPIO1 12 RK_FUNC_1 &pcfg_pull_none>;
 418                         };
 419
 420                         uart3_rts: uart3-rts {
 421                                 rockchip,pins = <RK_GPIO1 13 RK_FUNC_1 &pcfg_pull_none>;
 422                         };
 423                 };
 424
 425                 sd0 {
 426                         sd0_clk: sd0-clk {
 427                                 rockchip,pins = <RK_GPIO3 2 RK_FUNC_1 &pcfg_pull_none>;
 428                         };
 429
 430                         sd0_cmd: sd0-cmd {
 431                                 rockchip,pins = <RK_GPIO3 3 RK_FUNC_1 &pcfg_pull_none>;
 432                         };
 433
 434                         sd0_cd: sd0-cd {
 435                                 rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_none>;
 436                         };
 437
 438                         sd0_wp: sd0-wp {
 439                                 rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_none>;
 440                         };
 441
 442                         sd0_pwr: sd0-pwr {
 443                                 rockchip,pins = <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
 444                         };
 445
 446                         sd0_bus1: sd0-bus-width1 {
 447                                 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>;
 448                         };
 449
 450                         sd0_bus4: sd0-bus-width4 {
 451                                 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
 452                                                 <RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>,
 453                                                 <RK_GPIO3 6 RK_FUNC_1 &pcfg_pull_none>,
 454                                                 <RK_GPIO3 7 RK_FUNC_1 &pcfg_pull_none>;
 455                         };
 456                 };
 457
 458                 sd1 {
 459                         sd1_clk: sd1-clk {
 460                                 rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_none>;
 461                         };
 462
 463                         sd1_cmd: sd1-cmd {
 464                                 rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_none>;
 465                         };
 466
 467                         sd1_cd: sd1-cd {
 468                                 rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_none>;
 469                         };
 470
 471                         sd1_wp: sd1-wp {
 472                                 rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_none>;
 473                         };
 474
 475                         sd1_bus1: sd1-bus-width1 {
 476                                 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>;
 477                         };
 478
 479                         sd1_bus4: sd1-bus-width4 {
 480                                 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>,
 481                                                 <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_none>,
 482                                                 <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_none>,
 483                                                 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>;
 484                         };
 485                 };
 486
 487                 i2s0 {
 488                         i2s0_bus: i2s0-bus {
 489                                 rockchip,pins = <RK_GPIO1 16 RK_FUNC_1 &pcfg_pull_none>,
 490                                                 <RK_GPIO1 17 RK_FUNC_1 &pcfg_pull_none>,
 491                                                 <RK_GPIO1 18 RK_FUNC_1 &pcfg_pull_none>,
 492                                                 <RK_GPIO1 19 RK_FUNC_1 &pcfg_pull_none>,
 493                                                 <RK_GPIO1 20 RK_FUNC_1 &pcfg_pull_none>,
 494                                                 <RK_GPIO1 21 RK_FUNC_1 &pcfg_pull_none>;
 495                         };
 496                 };
 497
 498                 spdif {
 499                         spdif_tx: spdif-tx {
 500                                 rockchip,pins = <RK_GPIO1 14 RK_FUNC_1 &pcfg_pull_none>;
 501                         };
 502                 };
 503         };
 504 };
 505
 506 &emac {
 507         compatible = "rockchip,rk3188-emac";
 508 };
 509
 510 &global_timer {
 511         interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
 512         status = "disabled";
 513 };
 514
 515 &local_timer {
 516         interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
 517 };
 518
 519 &gpu {
 520         compatible = "rockchip,rk3188-mali", "arm,mali-400";
 521         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 522                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 523                      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 524                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 525                      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 526                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 527                      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 528                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 529                      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 530                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 531         interrupt-names = "gp",
 532                           "gpmmu",
 533                           "pp0",
 534                           "ppmmu0",
 535                           "pp1",
 536                           "ppmmu1",
 537                           "pp2",
 538                           "ppmmu2",
 539                           "pp3",
 540                           "ppmmu3";
 541 };
 542
 543 &i2c0 {
 544         compatible = "rockchip,rk3188-i2c";
 545         pinctrl-names = "default";
 546         pinctrl-0 = <&i2c0_xfer>;
 547 };
 548
 549 &i2c1 {
 550         compatible = "rockchip,rk3188-i2c";
 551         pinctrl-names = "default";
 552         pinctrl-0 = <&i2c1_xfer>;
 553 };
 554
 555 &i2c2 {
 556         compatible = "rockchip,rk3188-i2c";
 557         pinctrl-names = "default";
 558         pinctrl-0 = <&i2c2_xfer>;
 559 };
 560
 561 &i2c3 {
 562         compatible = "rockchip,rk3188-i2c";
 563         pinctrl-names = "default";
 564         pinctrl-0 = <&i2c3_xfer>;
 565 };
 566
 567 &i2c4 {
 568         compatible = "rockchip,rk3188-i2c";
 569         pinctrl-names = "default";
 570         pinctrl-0 = <&i2c4_xfer>;
 571 };
 572
 573 &pwm0 {
 574         pinctrl-names = "default";
 575         pinctrl-0 = <&pwm0_out>;
 576 };
 577
 578 &pwm1 {
 579         pinctrl-names = "default";
 580         pinctrl-0 = <&pwm1_out>;
 581 };
 582
 583 &pwm2 {
 584         pinctrl-names = "default";
 585         pinctrl-0 = <&pwm2_out>;
 586 };
 587
 588 &pwm3 {
 589         pinctrl-names = "default";
 590         pinctrl-0 = <&pwm3_out>;
 591 };
 592
 593 &spi0 {
 594         compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
 595         pinctrl-names = "default";
 596         pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 597 };
 598
 599 &spi1 {
 600         compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
 601         pinctrl-names = "default";
 602         pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 603 };
 604
 605 &uart0 {
 606         compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
 607         pinctrl-names = "default";
 608         pinctrl-0 = <&uart0_xfer>;
 609 };
 610
 611 &uart1 {
 612         compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
 613         pinctrl-names = "default";
 614         pinctrl-0 = <&uart1_xfer>;
 615 };
 616
 617 &uart2 {
 618         compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
 619         pinctrl-names = "default";
 620         pinctrl-0 = <&uart2_xfer>;
 621 };
 622
 623 &uart3 {
 624         compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
 625         pinctrl-names = "default";
 626         pinctrl-0 = <&uart3_xfer>;
 627 };
 628
 629 &wdt {
 630         compatible = "rockchip,rk3188-wdt", "snps,dw-wdt";
 631 };