GNU Linux-libre 4.19.264-gnu1
[releases.git] / arch / arm / boot / dts / rk3066a.dtsi
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3  * Copyright (c) 2013 MundoReader S.L.
4  * Author: Heiko Stuebner <heiko@sntech.de>
5  */
6
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/clock/rk3066a-cru.h>
10 #include "rk3xxx.dtsi"
11
12 / {
13         compatible = "rockchip,rk3066a";
14
15         cpus {
16                 #address-cells = <1>;
17                 #size-cells = <0>;
18                 enable-method = "rockchip,rk3066-smp";
19
20                 cpu0: cpu@0 {
21                         device_type = "cpu";
22                         compatible = "arm,cortex-a9";
23                         next-level-cache = <&L2>;
24                         reg = <0x0>;
25                         operating-points = <
26                                 /* kHz    uV */
27                                 1416000 1300000
28                                 1200000 1175000
29                                 1008000 1125000
30                                 816000  1125000
31                                 600000  1100000
32                                 504000  1100000
33                                 312000  1075000
34                         >;
35                         clock-latency = <40000>;
36                         clocks = <&cru ARMCLK>;
37                 };
38                 cpu@1 {
39                         device_type = "cpu";
40                         compatible = "arm,cortex-a9";
41                         next-level-cache = <&L2>;
42                         reg = <0x1>;
43                 };
44         };
45
46         sram: sram@10080000 {
47                 compatible = "mmio-sram";
48                 reg = <0x10080000 0x10000>;
49                 #address-cells = <1>;
50                 #size-cells = <1>;
51                 ranges = <0 0x10080000 0x10000>;
52
53                 smp-sram@0 {
54                         compatible = "rockchip,rk3066-smp-sram";
55                         reg = <0x0 0x50>;
56                 };
57         };
58
59         i2s0: i2s@10118000 {
60                 compatible = "rockchip,rk3066-i2s";
61                 reg = <0x10118000 0x2000>;
62                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
63                 #address-cells = <1>;
64                 #size-cells = <0>;
65                 pinctrl-names = "default";
66                 pinctrl-0 = <&i2s0_bus>;
67                 dmas = <&dmac1_s 4>, <&dmac1_s 5>;
68                 dma-names = "tx", "rx";
69                 clock-names = "i2s_hclk", "i2s_clk";
70                 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
71                 rockchip,playback-channels = <8>;
72                 rockchip,capture-channels = <2>;
73                 status = "disabled";
74         };
75
76         i2s1: i2s@1011a000 {
77                 compatible = "rockchip,rk3066-i2s";
78                 reg = <0x1011a000 0x2000>;
79                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
80                 #address-cells = <1>;
81                 #size-cells = <0>;
82                 pinctrl-names = "default";
83                 pinctrl-0 = <&i2s1_bus>;
84                 dmas = <&dmac1_s 6>, <&dmac1_s 7>;
85                 dma-names = "tx", "rx";
86                 clock-names = "i2s_hclk", "i2s_clk";
87                 clocks = <&cru HCLK_I2S1>, <&cru SCLK_I2S1>;
88                 rockchip,playback-channels = <2>;
89                 rockchip,capture-channels = <2>;
90                 status = "disabled";
91         };
92
93         i2s2: i2s@1011c000 {
94                 compatible = "rockchip,rk3066-i2s";
95                 reg = <0x1011c000 0x2000>;
96                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
97                 #address-cells = <1>;
98                 #size-cells = <0>;
99                 pinctrl-names = "default";
100                 pinctrl-0 = <&i2s2_bus>;
101                 dmas = <&dmac1_s 9>, <&dmac1_s 10>;
102                 dma-names = "tx", "rx";
103                 clock-names = "i2s_hclk", "i2s_clk";
104                 clocks = <&cru HCLK_I2S2>, <&cru SCLK_I2S2>;
105                 rockchip,playback-channels = <2>;
106                 rockchip,capture-channels = <2>;
107                 status = "disabled";
108         };
109
110         cru: clock-controller@20000000 {
111                 compatible = "rockchip,rk3066a-cru";
112                 reg = <0x20000000 0x1000>;
113                 rockchip,grf = <&grf>;
114
115                 #clock-cells = <1>;
116                 #reset-cells = <1>;
117                 assigned-clocks = <&cru PLL_CPLL>, <&cru PLL_GPLL>,
118                                   <&cru ACLK_CPU>, <&cru HCLK_CPU>,
119                                   <&cru PCLK_CPU>, <&cru ACLK_PERI>,
120                                   <&cru HCLK_PERI>, <&cru PCLK_PERI>;
121                 assigned-clock-rates = <400000000>, <594000000>,
122                                        <300000000>, <150000000>,
123                                        <75000000>, <300000000>,
124                                        <150000000>, <75000000>;
125         };
126
127         timer@2000e000 {
128                 compatible = "snps,dw-apb-timer-osc";
129                 reg = <0x2000e000 0x100>;
130                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
131                 clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>;
132                 clock-names = "timer", "pclk";
133         };
134
135         efuse: efuse@20010000 {
136                 compatible = "rockchip,rk3066a-efuse";
137                 reg = <0x20010000 0x4000>;
138                 #address-cells = <1>;
139                 #size-cells = <1>;
140                 clocks = <&cru PCLK_EFUSE>;
141                 clock-names = "pclk_efuse";
142
143                 cpu_leakage: cpu_leakage@17 {
144                         reg = <0x17 0x1>;
145                 };
146         };
147
148         timer@20038000 {
149                 compatible = "snps,dw-apb-timer-osc";
150                 reg = <0x20038000 0x100>;
151                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
152                 clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>;
153                 clock-names = "timer", "pclk";
154         };
155
156         timer@2003a000 {
157                 compatible = "snps,dw-apb-timer-osc";
158                 reg = <0x2003a000 0x100>;
159                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
160                 clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>;
161                 clock-names = "timer", "pclk";
162         };
163
164         tsadc: tsadc@20060000 {
165                 compatible = "rockchip,rk3066-tsadc";
166                 reg = <0x20060000 0x100>;
167                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
168                 clock-names = "saradc", "apb_pclk";
169                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
170                 #io-channel-cells = <1>;
171                 resets = <&cru SRST_TSADC>;
172                 reset-names = "saradc-apb";
173                 status = "disabled";
174         };
175
176         usbphy: phy {
177                 compatible = "rockchip,rk3066a-usb-phy", "rockchip,rk3288-usb-phy";
178                 rockchip,grf = <&grf>;
179                 #address-cells = <1>;
180                 #size-cells = <0>;
181                 status = "disabled";
182
183                 usbphy0: usb-phy@17c {
184                         #phy-cells = <0>;
185                         reg = <0x17c>;
186                         clocks = <&cru SCLK_OTGPHY0>;
187                         clock-names = "phyclk";
188                         #clock-cells = <0>;
189                 };
190
191                 usbphy1: usb-phy@188 {
192                         #phy-cells = <0>;
193                         reg = <0x188>;
194                         clocks = <&cru SCLK_OTGPHY1>;
195                         clock-names = "phyclk";
196                         #clock-cells = <0>;
197                 };
198         };
199
200         pinctrl: pinctrl {
201                 compatible = "rockchip,rk3066a-pinctrl";
202                 rockchip,grf = <&grf>;
203                 #address-cells = <1>;
204                 #size-cells = <1>;
205                 ranges;
206
207                 gpio0: gpio0@20034000 {
208                         compatible = "rockchip,gpio-bank";
209                         reg = <0x20034000 0x100>;
210                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
211                         clocks = <&cru PCLK_GPIO0>;
212
213                         gpio-controller;
214                         #gpio-cells = <2>;
215
216                         interrupt-controller;
217                         #interrupt-cells = <2>;
218                 };
219
220                 gpio1: gpio1@2003c000 {
221                         compatible = "rockchip,gpio-bank";
222                         reg = <0x2003c000 0x100>;
223                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
224                         clocks = <&cru PCLK_GPIO1>;
225
226                         gpio-controller;
227                         #gpio-cells = <2>;
228
229                         interrupt-controller;
230                         #interrupt-cells = <2>;
231                 };
232
233                 gpio2: gpio2@2003e000 {
234                         compatible = "rockchip,gpio-bank";
235                         reg = <0x2003e000 0x100>;
236                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
237                         clocks = <&cru PCLK_GPIO2>;
238
239                         gpio-controller;
240                         #gpio-cells = <2>;
241
242                         interrupt-controller;
243                         #interrupt-cells = <2>;
244                 };
245
246                 gpio3: gpio3@20080000 {
247                         compatible = "rockchip,gpio-bank";
248                         reg = <0x20080000 0x100>;
249                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
250                         clocks = <&cru PCLK_GPIO3>;
251
252                         gpio-controller;
253                         #gpio-cells = <2>;
254
255                         interrupt-controller;
256                         #interrupt-cells = <2>;
257                 };
258
259                 gpio4: gpio4@20084000 {
260                         compatible = "rockchip,gpio-bank";
261                         reg = <0x20084000 0x100>;
262                         interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
263                         clocks = <&cru PCLK_GPIO4>;
264
265                         gpio-controller;
266                         #gpio-cells = <2>;
267
268                         interrupt-controller;
269                         #interrupt-cells = <2>;
270                 };
271
272                 gpio6: gpio6@2000a000 {
273                         compatible = "rockchip,gpio-bank";
274                         reg = <0x2000a000 0x100>;
275                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
276                         clocks = <&cru PCLK_GPIO6>;
277
278                         gpio-controller;
279                         #gpio-cells = <2>;
280
281                         interrupt-controller;
282                         #interrupt-cells = <2>;
283                 };
284
285                 pcfg_pull_default: pcfg_pull_default {
286                         bias-pull-pin-default;
287                 };
288
289                 pcfg_pull_none: pcfg_pull_none {
290                         bias-disable;
291                 };
292
293                 emac {
294                         emac_xfer: emac-xfer {
295                                 rockchip,pins = <RK_GPIO1 16 RK_FUNC_2 &pcfg_pull_none>, /* mac_clk */
296                                                 <RK_GPIO1 17 RK_FUNC_2 &pcfg_pull_none>, /* tx_en */
297                                                 <RK_GPIO1 18 RK_FUNC_2 &pcfg_pull_none>, /* txd1 */
298                                                 <RK_GPIO1 19 RK_FUNC_2 &pcfg_pull_none>, /* txd0 */
299                                                 <RK_GPIO1 20 RK_FUNC_2 &pcfg_pull_none>, /* rx_err */
300                                                 <RK_GPIO1 21 RK_FUNC_2 &pcfg_pull_none>, /* crs_dvalid */
301                                                 <RK_GPIO1 22 RK_FUNC_2 &pcfg_pull_none>, /* rxd1 */
302                                                 <RK_GPIO1 23 RK_FUNC_2 &pcfg_pull_none>; /* rxd0 */
303                         };
304
305                         emac_mdio: emac-mdio {
306                                 rockchip,pins = <RK_GPIO1 24 RK_FUNC_2 &pcfg_pull_none>, /* mac_md */
307                                                 <RK_GPIO1 25 RK_FUNC_2 &pcfg_pull_none>; /* mac_mdclk */
308                         };
309                 };
310
311                 emmc {
312                         emmc_clk: emmc-clk {
313                                 rockchip,pins = <RK_GPIO3 31 RK_FUNC_2 &pcfg_pull_default>;
314                         };
315
316                         emmc_cmd: emmc-cmd {
317                                 rockchip,pins = <RK_GPIO4 9 RK_FUNC_2 &pcfg_pull_default>;
318                         };
319
320                         emmc_rst: emmc-rst {
321                                 rockchip,pins = <RK_GPIO4 10 RK_FUNC_2 &pcfg_pull_default>;
322                         };
323
324                         /*
325                          * The data pins are shared between nandc and emmc and
326                          * not accessible through pinctrl. Also they should've
327                          * been already set correctly by firmware, as
328                          * flash/emmc is the boot-device.
329                          */
330                 };
331
332                 i2c0 {
333                         i2c0_xfer: i2c0-xfer {
334                                 rockchip,pins = <RK_GPIO2 28 RK_FUNC_1 &pcfg_pull_none>,
335                                                 <RK_GPIO2 29 RK_FUNC_1 &pcfg_pull_none>;
336                         };
337                 };
338
339                 i2c1 {
340                         i2c1_xfer: i2c1-xfer {
341                                 rockchip,pins = <RK_GPIO2 30 RK_FUNC_1 &pcfg_pull_none>,
342                                                 <RK_GPIO2 31 RK_FUNC_1 &pcfg_pull_none>;
343                         };
344                 };
345
346                 i2c2 {
347                         i2c2_xfer: i2c2-xfer {
348                                 rockchip,pins = <RK_GPIO3 0 RK_FUNC_1 &pcfg_pull_none>,
349                                                 <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
350                         };
351                 };
352
353                 i2c3 {
354                         i2c3_xfer: i2c3-xfer {
355                                 rockchip,pins = <RK_GPIO3 2 RK_FUNC_2 &pcfg_pull_none>,
356                                                 <RK_GPIO3 3 RK_FUNC_2 &pcfg_pull_none>;
357                         };
358                 };
359
360                 i2c4 {
361                         i2c4_xfer: i2c4-xfer {
362                                 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
363                                                 <RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>;
364                         };
365                 };
366
367                 pwm0 {
368                         pwm0_out: pwm0-out {
369                                 rockchip,pins = <RK_GPIO0 3 RK_FUNC_1 &pcfg_pull_none>;
370                         };
371                 };
372
373                 pwm1 {
374                         pwm1_out: pwm1-out {
375                                 rockchip,pins = <RK_GPIO0 4 RK_FUNC_1 &pcfg_pull_none>;
376                         };
377                 };
378
379                 pwm2 {
380                         pwm2_out: pwm2-out {
381                                 rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_none>;
382                         };
383                 };
384
385                 pwm3 {
386                         pwm3_out: pwm3-out {
387                                 rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_none>;
388                         };
389                 };
390
391                 spi0 {
392                         spi0_clk: spi0-clk {
393                                 rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_default>;
394                         };
395                         spi0_cs0: spi0-cs0 {
396                                 rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_default>;
397                         };
398                         spi0_tx: spi0-tx {
399                                 rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_default>;
400                         };
401                         spi0_rx: spi0-rx {
402                                 rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_default>;
403                         };
404                         spi0_cs1: spi0-cs1 {
405                                 rockchip,pins = <RK_GPIO4 15 RK_FUNC_1 &pcfg_pull_default>;
406                         };
407                 };
408
409                 spi1 {
410                         spi1_clk: spi1-clk {
411                                 rockchip,pins = <RK_GPIO2 19 RK_FUNC_2 &pcfg_pull_default>;
412                         };
413                         spi1_cs0: spi1-cs0 {
414                                 rockchip,pins = <RK_GPIO2 20 RK_FUNC_2 &pcfg_pull_default>;
415                         };
416                         spi1_rx: spi1-rx {
417                                 rockchip,pins = <RK_GPIO2 22 RK_FUNC_2 &pcfg_pull_default>;
418                         };
419                         spi1_tx: spi1-tx {
420                                 rockchip,pins = <RK_GPIO2 21 RK_FUNC_2 &pcfg_pull_default>;
421                         };
422                         spi1_cs1: spi1-cs1 {
423                                 rockchip,pins = <RK_GPIO2 23 RK_FUNC_2 &pcfg_pull_default>;
424                         };
425                 };
426
427                 uart0 {
428                         uart0_xfer: uart0-xfer {
429                                 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>,
430                                                 <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_default>;
431                         };
432
433                         uart0_cts: uart0-cts {
434                                 rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_default>;
435                         };
436
437                         uart0_rts: uart0-rts {
438                                 rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_default>;
439                         };
440                 };
441
442                 uart1 {
443                         uart1_xfer: uart1-xfer {
444                                 rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_default>,
445                                                 <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_default>;
446                         };
447
448                         uart1_cts: uart1-cts {
449                                 rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_default>;
450                         };
451
452                         uart1_rts: uart1-rts {
453                                 rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_default>;
454                         };
455                 };
456
457                 uart2 {
458                         uart2_xfer: uart2-xfer {
459                                 rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_default>,
460                                                 <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_default>;
461                         };
462                         /* no rts / cts for uart2 */
463                 };
464
465                 uart3 {
466                         uart3_xfer: uart3-xfer {
467                                 rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_default>,
468                                                 <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_default>;
469                         };
470
471                         uart3_cts: uart3-cts {
472                                 rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_default>;
473                         };
474
475                         uart3_rts: uart3-rts {
476                                 rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_default>;
477                         };
478                 };
479
480                 sd0 {
481                         sd0_clk: sd0-clk {
482                                 rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_default>;
483                         };
484
485                         sd0_cmd: sd0-cmd {
486                                 rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_default>;
487                         };
488
489                         sd0_cd: sd0-cd {
490                                 rockchip,pins = <RK_GPIO3 14 RK_FUNC_1 &pcfg_pull_default>;
491                         };
492
493                         sd0_wp: sd0-wp {
494                                 rockchip,pins = <RK_GPIO3 15 RK_FUNC_1 &pcfg_pull_default>;
495                         };
496
497                         sd0_bus1: sd0-bus-width1 {
498                                 rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>;
499                         };
500
501                         sd0_bus4: sd0-bus-width4 {
502                                 rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>,
503                                                 <RK_GPIO3 11 RK_FUNC_1 &pcfg_pull_default>,
504                                                 <RK_GPIO3 12 RK_FUNC_1 &pcfg_pull_default>,
505                                                 <RK_GPIO3 13 RK_FUNC_1 &pcfg_pull_default>;
506                         };
507                 };
508
509                 sd1 {
510                         sd1_clk: sd1-clk {
511                                 rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_default>;
512                         };
513
514                         sd1_cmd: sd1-cmd {
515                                 rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_default>;
516                         };
517
518                         sd1_cd: sd1-cd {
519                                 rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_default>;
520                         };
521
522                         sd1_wp: sd1-wp {
523                                 rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_default>;
524                         };
525
526                         sd1_bus1: sd1-bus-width1 {
527                                 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>;
528                         };
529
530                         sd1_bus4: sd1-bus-width4 {
531                                 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>,
532                                                 <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_default>,
533                                                 <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_default>,
534                                                 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>;
535                         };
536                 };
537
538                 i2s0 {
539                         i2s0_bus: i2s0-bus {
540                                 rockchip,pins = <RK_GPIO0 7 RK_FUNC_1 &pcfg_pull_default>,
541                                                 <RK_GPIO0 8 RK_FUNC_1 &pcfg_pull_default>,
542                                                 <RK_GPIO0 9 RK_FUNC_1 &pcfg_pull_default>,
543                                                 <RK_GPIO0 10 RK_FUNC_1 &pcfg_pull_default>,
544                                                 <RK_GPIO0 11 RK_FUNC_1 &pcfg_pull_default>,
545                                                 <RK_GPIO0 12 RK_FUNC_1 &pcfg_pull_default>,
546                                                 <RK_GPIO0 13 RK_FUNC_1 &pcfg_pull_default>,
547                                                 <RK_GPIO0 14 RK_FUNC_1 &pcfg_pull_default>,
548                                                 <RK_GPIO0 15 RK_FUNC_1 &pcfg_pull_default>;
549                         };
550                 };
551
552                 i2s1 {
553                         i2s1_bus: i2s1-bus {
554                                 rockchip,pins = <RK_GPIO0 16 RK_FUNC_1 &pcfg_pull_default>,
555                                                 <RK_GPIO0 17 RK_FUNC_1 &pcfg_pull_default>,
556                                                 <RK_GPIO0 18 RK_FUNC_1 &pcfg_pull_default>,
557                                                 <RK_GPIO0 19 RK_FUNC_1 &pcfg_pull_default>,
558                                                 <RK_GPIO0 20 RK_FUNC_1 &pcfg_pull_default>,
559                                                 <RK_GPIO0 21 RK_FUNC_1 &pcfg_pull_default>;
560                         };
561                 };
562
563                 i2s2 {
564                         i2s2_bus: i2s2-bus {
565                                 rockchip,pins = <RK_GPIO0 24 RK_FUNC_1 &pcfg_pull_default>,
566                                                 <RK_GPIO0 25 RK_FUNC_1 &pcfg_pull_default>,
567                                                 <RK_GPIO0 26 RK_FUNC_1 &pcfg_pull_default>,
568                                                 <RK_GPIO0 27 RK_FUNC_1 &pcfg_pull_default>,
569                                                 <RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_default>,
570                                                 <RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_default>;
571                         };
572                 };
573         };
574 };
575
576 &gpu {
577         compatible = "rockchip,rk3066-mali", "arm,mali-400";
578         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
579                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
580                      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
581                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
582                      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
583                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
584                      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
585                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
586                      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
587                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
588         interrupt-names = "gp",
589                           "gpmmu",
590                           "pp0",
591                           "ppmmu0",
592                           "pp1",
593                           "ppmmu1",
594                           "pp2",
595                           "ppmmu2",
596                           "pp3",
597                           "ppmmu3";
598 };
599
600 &i2c0 {
601         pinctrl-names = "default";
602         pinctrl-0 = <&i2c0_xfer>;
603 };
604
605 &i2c1 {
606         pinctrl-names = "default";
607         pinctrl-0 = <&i2c1_xfer>;
608 };
609
610 &i2c2 {
611         pinctrl-names = "default";
612         pinctrl-0 = <&i2c2_xfer>;
613 };
614
615 &i2c3 {
616         pinctrl-names = "default";
617         pinctrl-0 = <&i2c3_xfer>;
618 };
619
620 &i2c4 {
621         pinctrl-names = "default";
622         pinctrl-0 = <&i2c4_xfer>;
623 };
624
625 &mmc0 {
626         clock-frequency = <50000000>;
627         dmas = <&dmac2 1>;
628         dma-names = "rx-tx";
629         max-frequency = <50000000>;
630         pinctrl-names = "default";
631         pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>;
632 };
633
634 &mmc1 {
635         dmas = <&dmac2 3>;
636         dma-names = "rx-tx";
637         pinctrl-names = "default";
638         pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>;
639 };
640
641 &emmc {
642         dmas = <&dmac2 4>;
643         dma-names = "rx-tx";
644 };
645
646 &pwm0 {
647         pinctrl-names = "default";
648         pinctrl-0 = <&pwm0_out>;
649 };
650
651 &pwm1 {
652         pinctrl-names = "default";
653         pinctrl-0 = <&pwm1_out>;
654 };
655
656 &pwm2 {
657         pinctrl-names = "default";
658         pinctrl-0 = <&pwm2_out>;
659 };
660
661 &pwm3 {
662         pinctrl-names = "default";
663         pinctrl-0 = <&pwm3_out>;
664 };
665
666 &spi0 {
667         pinctrl-names = "default";
668         pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
669 };
670
671 &spi1 {
672         pinctrl-names = "default";
673         pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
674 };
675
676 &uart0 {
677         compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
678         dmas = <&dmac1_s 0>, <&dmac1_s 1>;
679         dma-names = "tx", "rx";
680         pinctrl-names = "default";
681         pinctrl-0 = <&uart0_xfer>;
682 };
683
684 &uart1 {
685         compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
686         dmas = <&dmac1_s 2>, <&dmac1_s 3>;
687         dma-names = "tx", "rx";
688         pinctrl-names = "default";
689         pinctrl-0 = <&uart1_xfer>;
690 };
691
692 &uart2 {
693         compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
694         dmas = <&dmac2 6>, <&dmac2 7>;
695         dma-names = "tx", "rx";
696         pinctrl-names = "default";
697         pinctrl-0 = <&uart2_xfer>;
698 };
699
700 &uart3 {
701         compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
702         dmas = <&dmac2 8>, <&dmac2 9>;
703         dma-names = "tx", "rx";
704         pinctrl-names = "default";
705         pinctrl-0 = <&uart3_xfer>;
706 };
707
708 &wdt {
709         compatible = "rockchip,rk3066-wdt", "snps,dw-wdt";
710 };
711
712 &emac {
713         compatible = "rockchip,rk3066-emac";
714 };