2 * Copyright (c) 2013 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
10 * a) This file is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
15 * This file is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
22 * b) Permission is hereby granted, free of charge, to any person
23 * obtaining a copy of this software and associated documentation
24 * files (the "Software"), to deal in the Software without
25 * restriction, including without limitation the rights to use,
26 * copy, modify, merge, publish, distribute, sublicense, and/or
27 * sell copies of the Software, and to permit persons to whom the
28 * Software is furnished to do so, subject to the following
31 * The above copyright notice and this permission notice shall be
32 * included in all copies or substantial portions of the Software.
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 * OTHER DEALINGS IN THE SOFTWARE.
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/pinctrl/rockchip.h>
46 #include <dt-bindings/clock/rk3066a-cru.h>
47 #include "rk3xxx.dtsi"
50 compatible = "rockchip,rk3066a";
55 enable-method = "rockchip,rk3066-smp";
59 compatible = "arm,cortex-a9";
60 next-level-cache = <&L2>;
72 clock-latency = <40000>;
73 clocks = <&cru ARMCLK>;
77 compatible = "arm,cortex-a9";
78 next-level-cache = <&L2>;
84 compatible = "mmio-sram";
85 reg = <0x10080000 0x10000>;
88 ranges = <0 0x10080000 0x10000>;
91 compatible = "rockchip,rk3066-smp-sram";
97 compatible = "rockchip,rk3066-i2s";
98 reg = <0x10118000 0x2000>;
99 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
100 #address-cells = <1>;
102 pinctrl-names = "default";
103 pinctrl-0 = <&i2s0_bus>;
104 dmas = <&dmac1_s 4>, <&dmac1_s 5>;
105 dma-names = "tx", "rx";
106 clock-names = "i2s_hclk", "i2s_clk";
107 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
108 rockchip,playback-channels = <8>;
109 rockchip,capture-channels = <2>;
114 compatible = "rockchip,rk3066-i2s";
115 reg = <0x1011a000 0x2000>;
116 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
117 #address-cells = <1>;
119 pinctrl-names = "default";
120 pinctrl-0 = <&i2s1_bus>;
121 dmas = <&dmac1_s 6>, <&dmac1_s 7>;
122 dma-names = "tx", "rx";
123 clock-names = "i2s_hclk", "i2s_clk";
124 clocks = <&cru HCLK_I2S1>, <&cru SCLK_I2S1>;
125 rockchip,playback-channels = <2>;
126 rockchip,capture-channels = <2>;
131 compatible = "rockchip,rk3066-i2s";
132 reg = <0x1011c000 0x2000>;
133 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
134 #address-cells = <1>;
136 pinctrl-names = "default";
137 pinctrl-0 = <&i2s2_bus>;
138 dmas = <&dmac1_s 9>, <&dmac1_s 10>;
139 dma-names = "tx", "rx";
140 clock-names = "i2s_hclk", "i2s_clk";
141 clocks = <&cru HCLK_I2S2>, <&cru SCLK_I2S2>;
142 rockchip,playback-channels = <2>;
143 rockchip,capture-channels = <2>;
147 cru: clock-controller@20000000 {
148 compatible = "rockchip,rk3066a-cru";
149 reg = <0x20000000 0x1000>;
150 rockchip,grf = <&grf>;
157 compatible = "snps,dw-apb-timer-osc";
158 reg = <0x2000e000 0x100>;
159 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
160 clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>;
161 clock-names = "timer", "pclk";
164 efuse: efuse@20010000 {
165 compatible = "rockchip,rockchip-efuse";
166 reg = <0x20010000 0x4000>;
167 #address-cells = <1>;
169 clocks = <&cru PCLK_EFUSE>;
170 clock-names = "pclk_efuse";
172 cpu_leakage: cpu_leakage@17 {
178 compatible = "snps,dw-apb-timer-osc";
179 reg = <0x20038000 0x100>;
180 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
181 clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>;
182 clock-names = "timer", "pclk";
186 compatible = "snps,dw-apb-timer-osc";
187 reg = <0x2003a000 0x100>;
188 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
189 clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>;
190 clock-names = "timer", "pclk";
193 tsadc: tsadc@20060000 {
194 compatible = "rockchip,rk3066-tsadc";
195 reg = <0x20060000 0x100>;
196 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
197 clock-names = "saradc", "apb_pclk";
198 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
199 #io-channel-cells = <1>;
200 resets = <&cru SRST_SARADC>;
201 reset-names = "saradc-apb";
206 compatible = "rockchip,rk3066a-usb-phy", "rockchip,rk3288-usb-phy";
207 rockchip,grf = <&grf>;
208 #address-cells = <1>;
212 usbphy0: usb-phy@17c {
215 clocks = <&cru SCLK_OTGPHY0>;
216 clock-names = "phyclk";
220 usbphy1: usb-phy@188 {
223 clocks = <&cru SCLK_OTGPHY1>;
224 clock-names = "phyclk";
230 compatible = "rockchip,rk3066a-pinctrl";
231 rockchip,grf = <&grf>;
232 #address-cells = <1>;
236 gpio0: gpio0@20034000 {
237 compatible = "rockchip,gpio-bank";
238 reg = <0x20034000 0x100>;
239 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
240 clocks = <&cru PCLK_GPIO0>;
245 interrupt-controller;
246 #interrupt-cells = <2>;
249 gpio1: gpio1@2003c000 {
250 compatible = "rockchip,gpio-bank";
251 reg = <0x2003c000 0x100>;
252 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
253 clocks = <&cru PCLK_GPIO1>;
258 interrupt-controller;
259 #interrupt-cells = <2>;
262 gpio2: gpio2@2003e000 {
263 compatible = "rockchip,gpio-bank";
264 reg = <0x2003e000 0x100>;
265 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
266 clocks = <&cru PCLK_GPIO2>;
271 interrupt-controller;
272 #interrupt-cells = <2>;
275 gpio3: gpio3@20080000 {
276 compatible = "rockchip,gpio-bank";
277 reg = <0x20080000 0x100>;
278 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
279 clocks = <&cru PCLK_GPIO3>;
284 interrupt-controller;
285 #interrupt-cells = <2>;
288 gpio4: gpio4@20084000 {
289 compatible = "rockchip,gpio-bank";
290 reg = <0x20084000 0x100>;
291 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
292 clocks = <&cru PCLK_GPIO4>;
297 interrupt-controller;
298 #interrupt-cells = <2>;
301 gpio6: gpio6@2000a000 {
302 compatible = "rockchip,gpio-bank";
303 reg = <0x2000a000 0x100>;
304 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
305 clocks = <&cru PCLK_GPIO6>;
310 interrupt-controller;
311 #interrupt-cells = <2>;
314 pcfg_pull_default: pcfg_pull_default {
315 bias-pull-pin-default;
318 pcfg_pull_none: pcfg_pull_none {
323 emac_xfer: emac-xfer {
324 rockchip,pins = <RK_GPIO1 16 RK_FUNC_2 &pcfg_pull_none>, /* mac_clk */
325 <RK_GPIO1 17 RK_FUNC_2 &pcfg_pull_none>, /* tx_en */
326 <RK_GPIO1 18 RK_FUNC_2 &pcfg_pull_none>, /* txd1 */
327 <RK_GPIO1 19 RK_FUNC_2 &pcfg_pull_none>, /* txd0 */
328 <RK_GPIO1 20 RK_FUNC_2 &pcfg_pull_none>, /* rx_err */
329 <RK_GPIO1 21 RK_FUNC_2 &pcfg_pull_none>, /* crs_dvalid */
330 <RK_GPIO1 22 RK_FUNC_2 &pcfg_pull_none>, /* rxd1 */
331 <RK_GPIO1 23 RK_FUNC_2 &pcfg_pull_none>; /* rxd0 */
334 emac_mdio: emac-mdio {
335 rockchip,pins = <RK_GPIO1 24 RK_FUNC_2 &pcfg_pull_none>, /* mac_md */
336 <RK_GPIO1 25 RK_FUNC_2 &pcfg_pull_none>; /* mac_mdclk */
342 rockchip,pins = <RK_GPIO3 31 RK_FUNC_2 &pcfg_pull_default>;
346 rockchip,pins = <RK_GPIO4 9 RK_FUNC_2 &pcfg_pull_default>;
350 rockchip,pins = <RK_GPIO4 10 RK_FUNC_2 &pcfg_pull_default>;
354 * The data pins are shared between nandc and emmc and
355 * not accessible through pinctrl. Also they should've
356 * been already set correctly by firmware, as
357 * flash/emmc is the boot-device.
362 i2c0_xfer: i2c0-xfer {
363 rockchip,pins = <RK_GPIO2 28 RK_FUNC_1 &pcfg_pull_none>,
364 <RK_GPIO2 29 RK_FUNC_1 &pcfg_pull_none>;
369 i2c1_xfer: i2c1-xfer {
370 rockchip,pins = <RK_GPIO2 30 RK_FUNC_1 &pcfg_pull_none>,
371 <RK_GPIO2 31 RK_FUNC_1 &pcfg_pull_none>;
376 i2c2_xfer: i2c2-xfer {
377 rockchip,pins = <RK_GPIO3 0 RK_FUNC_1 &pcfg_pull_none>,
378 <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
383 i2c3_xfer: i2c3-xfer {
384 rockchip,pins = <RK_GPIO3 2 RK_FUNC_2 &pcfg_pull_none>,
385 <RK_GPIO3 3 RK_FUNC_2 &pcfg_pull_none>;
390 i2c4_xfer: i2c4-xfer {
391 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
392 <RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>;
398 rockchip,pins = <RK_GPIO0 3 RK_FUNC_1 &pcfg_pull_none>;
404 rockchip,pins = <RK_GPIO0 4 RK_FUNC_1 &pcfg_pull_none>;
410 rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_none>;
416 rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_none>;
422 rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_default>;
425 rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_default>;
428 rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_default>;
431 rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_default>;
434 rockchip,pins = <RK_GPIO4 15 RK_FUNC_1 &pcfg_pull_default>;
440 rockchip,pins = <RK_GPIO2 19 RK_FUNC_2 &pcfg_pull_default>;
443 rockchip,pins = <RK_GPIO2 20 RK_FUNC_2 &pcfg_pull_default>;
446 rockchip,pins = <RK_GPIO2 22 RK_FUNC_2 &pcfg_pull_default>;
449 rockchip,pins = <RK_GPIO2 21 RK_FUNC_2 &pcfg_pull_default>;
452 rockchip,pins = <RK_GPIO2 23 RK_FUNC_2 &pcfg_pull_default>;
457 uart0_xfer: uart0-xfer {
458 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>,
459 <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_default>;
462 uart0_cts: uart0-cts {
463 rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_default>;
466 uart0_rts: uart0-rts {
467 rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_default>;
472 uart1_xfer: uart1-xfer {
473 rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_default>,
474 <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_default>;
477 uart1_cts: uart1-cts {
478 rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_default>;
481 uart1_rts: uart1-rts {
482 rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_default>;
487 uart2_xfer: uart2-xfer {
488 rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_default>,
489 <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_default>;
491 /* no rts / cts for uart2 */
495 uart3_xfer: uart3-xfer {
496 rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_default>,
497 <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_default>;
500 uart3_cts: uart3-cts {
501 rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_default>;
504 uart3_rts: uart3-rts {
505 rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_default>;
511 rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_default>;
515 rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_default>;
519 rockchip,pins = <RK_GPIO3 14 RK_FUNC_1 &pcfg_pull_default>;
523 rockchip,pins = <RK_GPIO3 15 RK_FUNC_1 &pcfg_pull_default>;
526 sd0_bus1: sd0-bus-width1 {
527 rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>;
530 sd0_bus4: sd0-bus-width4 {
531 rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>,
532 <RK_GPIO3 11 RK_FUNC_1 &pcfg_pull_default>,
533 <RK_GPIO3 12 RK_FUNC_1 &pcfg_pull_default>,
534 <RK_GPIO3 13 RK_FUNC_1 &pcfg_pull_default>;
540 rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_default>;
544 rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_default>;
548 rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_default>;
552 rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_default>;
555 sd1_bus1: sd1-bus-width1 {
556 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>;
559 sd1_bus4: sd1-bus-width4 {
560 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>,
561 <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_default>,
562 <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_default>,
563 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>;
569 rockchip,pins = <RK_GPIO0 7 RK_FUNC_1 &pcfg_pull_default>,
570 <RK_GPIO0 8 RK_FUNC_1 &pcfg_pull_default>,
571 <RK_GPIO0 9 RK_FUNC_1 &pcfg_pull_default>,
572 <RK_GPIO0 10 RK_FUNC_1 &pcfg_pull_default>,
573 <RK_GPIO0 11 RK_FUNC_1 &pcfg_pull_default>,
574 <RK_GPIO0 12 RK_FUNC_1 &pcfg_pull_default>,
575 <RK_GPIO0 13 RK_FUNC_1 &pcfg_pull_default>,
576 <RK_GPIO0 14 RK_FUNC_1 &pcfg_pull_default>,
577 <RK_GPIO0 15 RK_FUNC_1 &pcfg_pull_default>;
583 rockchip,pins = <RK_GPIO0 16 RK_FUNC_1 &pcfg_pull_default>,
584 <RK_GPIO0 17 RK_FUNC_1 &pcfg_pull_default>,
585 <RK_GPIO0 18 RK_FUNC_1 &pcfg_pull_default>,
586 <RK_GPIO0 19 RK_FUNC_1 &pcfg_pull_default>,
587 <RK_GPIO0 20 RK_FUNC_1 &pcfg_pull_default>,
588 <RK_GPIO0 21 RK_FUNC_1 &pcfg_pull_default>;
594 rockchip,pins = <RK_GPIO0 24 RK_FUNC_1 &pcfg_pull_default>,
595 <RK_GPIO0 25 RK_FUNC_1 &pcfg_pull_default>,
596 <RK_GPIO0 26 RK_FUNC_1 &pcfg_pull_default>,
597 <RK_GPIO0 27 RK_FUNC_1 &pcfg_pull_default>,
598 <RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_default>,
599 <RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_default>;
606 pinctrl-names = "default";
607 pinctrl-0 = <&i2c0_xfer>;
611 pinctrl-names = "default";
612 pinctrl-0 = <&i2c1_xfer>;
616 pinctrl-names = "default";
617 pinctrl-0 = <&i2c2_xfer>;
621 pinctrl-names = "default";
622 pinctrl-0 = <&i2c3_xfer>;
626 pinctrl-names = "default";
627 pinctrl-0 = <&i2c4_xfer>;
631 pinctrl-names = "default";
632 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>;
636 pinctrl-names = "default";
637 pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>;
641 pinctrl-names = "default";
642 pinctrl-0 = <&pwm0_out>;
646 pinctrl-names = "default";
647 pinctrl-0 = <&pwm1_out>;
651 pinctrl-names = "default";
652 pinctrl-0 = <&pwm2_out>;
656 pinctrl-names = "default";
657 pinctrl-0 = <&pwm3_out>;
661 pinctrl-names = "default";
662 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
666 pinctrl-names = "default";
667 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
671 pinctrl-names = "default";
672 pinctrl-0 = <&uart0_xfer>;
676 pinctrl-names = "default";
677 pinctrl-0 = <&uart1_xfer>;
681 pinctrl-names = "default";
682 pinctrl-0 = <&uart2_xfer>;
686 pinctrl-names = "default";
687 pinctrl-0 = <&uart3_xfer>;
691 compatible = "rockchip,rk3066-wdt", "snps,dw-wdt";
695 compatible = "rockchip,rk3066-emac";