1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3036-cru.h>
8 #include <dt-bindings/soc/rockchip,boot-mode.h>
14 compatible = "rockchip,rk3036";
16 interrupt-parent = <&gic>;
34 enable-method = "rockchip,rk3036-smp";
38 compatible = "arm,cortex-a7";
40 resets = <&cru SRST_CORE0>;
45 clock-latency = <40000>;
46 clocks = <&cru ARMCLK>;
51 compatible = "arm,cortex-a7";
53 resets = <&cru SRST_CORE1>;
58 compatible = "simple-bus";
64 compatible = "arm,pl330", "arm,primecell";
65 reg = <0x20078000 0x4000>;
66 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
67 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
69 arm,pl330-broken-no-flushp;
70 clocks = <&cru ACLK_DMAC2>;
71 clock-names = "apb_pclk";
76 compatible = "arm,cortex-a7-pmu";
77 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
78 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
79 interrupt-affinity = <&cpu0>, <&cpu1>;
83 compatible = "rockchip,display-subsystem";
88 compatible = "arm,armv7-timer";
89 arm,cpu-registers-not-fw-configured;
90 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
91 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
92 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
93 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
94 clock-frequency = <24000000>;
98 compatible = "fixed-clock";
99 clock-frequency = <24000000>;
100 clock-output-names = "xin24m";
104 bus_intmem@10080000 {
105 compatible = "mmio-sram";
106 reg = <0x10080000 0x2000>;
107 #address-cells = <1>;
109 ranges = <0 0x10080000 0x2000>;
112 compatible = "rockchip,rk3066-smp-sram";
118 compatible = "rockchip,rk3036-mali", "arm,mali-400";
119 reg = <0x10090000 0x10000>;
120 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
121 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
122 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
123 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
124 interrupt-names = "gp",
128 assigned-clocks = <&cru SCLK_GPU>;
129 assigned-clock-rates = <100000000>;
130 clocks = <&cru SCLK_GPU>, <&cru SCLK_GPU>;
131 clock-names = "bus", "core";
132 resets = <&cru SRST_GPU>;
137 compatible = "rockchip,rk3036-vop";
138 reg = <0x10118000 0x19c>;
139 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
140 clocks = <&cru ACLK_LCDC>, <&cru SCLK_LCDC>, <&cru HCLK_LCDC>;
141 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
142 resets = <&cru SRST_LCDC1_A>, <&cru SRST_LCDC1_H>, <&cru SRST_LCDC1_D>;
143 reset-names = "axi", "ahb", "dclk";
148 #address-cells = <1>;
150 vop_out_hdmi: endpoint@0 {
152 remote-endpoint = <&hdmi_in_vop>;
157 vop_mmu: iommu@10118300 {
158 compatible = "rockchip,iommu";
159 reg = <0x10118300 0x100>;
160 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
161 interrupt-names = "vop_mmu";
162 clocks = <&cru ACLK_LCDC>, <&cru HCLK_LCDC>;
163 clock-names = "aclk", "iface";
168 gic: interrupt-controller@10139000 {
169 compatible = "arm,gic-400";
170 interrupt-controller;
171 #interrupt-cells = <3>;
172 #address-cells = <0>;
174 reg = <0x10139000 0x1000>,
178 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
181 usb_otg: usb@10180000 {
182 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
184 reg = <0x10180000 0x40000>;
185 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
186 clocks = <&cru HCLK_OTG0>;
189 g-np-tx-fifo-size = <16>;
190 g-rx-fifo-size = <275>;
191 g-tx-fifo-size = <256 128 128 64 64 32>;
195 usb_host: usb@101c0000 {
196 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
198 reg = <0x101c0000 0x40000>;
199 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
200 clocks = <&cru HCLK_OTG1>;
206 emac: ethernet@10200000 {
207 compatible = "rockchip,rk3036-emac", "snps,arc-emac";
208 reg = <0x10200000 0x4000>;
209 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
210 #address-cells = <1>;
212 rockchip,grf = <&grf>;
213 clocks = <&cru HCLK_MAC>, <&cru SCLK_MACREF>, <&cru SCLK_MAC>;
214 clock-names = "hclk", "macref", "macclk";
216 * Fix the emac parent clock is DPLL instead of APLL.
217 * since that will cause some unstable things if the cpufreq
218 * is working. (e.g: the accurate 50MHz what mac_ref need)
220 assigned-clocks = <&cru SCLK_MACPLL>;
221 assigned-clock-parents = <&cru PLL_DPLL>;
227 sdmmc: dwmmc@10214000 {
228 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
229 reg = <0x10214000 0x4000>;
230 clock-frequency = <37500000>;
231 max-frequency = <37500000>;
232 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
233 clock-names = "biu", "ciu";
234 fifo-depth = <0x100>;
235 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
236 resets = <&cru SRST_MMC0>;
237 reset-names = "reset";
241 sdio: dwmmc@10218000 {
242 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
243 reg = <0x10218000 0x4000>;
244 max-frequency = <37500000>;
245 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
246 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
247 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
248 fifo-depth = <0x100>;
249 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
250 resets = <&cru SRST_SDIO>;
251 reset-names = "reset";
255 emmc: dwmmc@1021c000 {
256 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
257 reg = <0x1021c000 0x4000>;
258 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
261 clock-frequency = <37500000>;
262 max-frequency = <37500000>;
263 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
264 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
265 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
266 default-sample-phase = <158>;
270 fifo-depth = <0x100>;
273 pinctrl-names = "default";
274 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
275 resets = <&cru SRST_EMMC>;
276 reset-names = "reset";
281 compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s";
282 reg = <0x10220000 0x4000>;
283 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
284 #address-cells = <1>;
286 clock-names = "i2s_clk", "i2s_hclk";
287 clocks = <&cru SCLK_I2S>, <&cru HCLK_I2S>;
288 dmas = <&pdma 0>, <&pdma 1>;
289 dma-names = "tx", "rx";
290 pinctrl-names = "default";
291 pinctrl-0 = <&i2s_bus>;
292 #sound-dai-cells = <0>;
296 cru: clock-controller@20000000 {
297 compatible = "rockchip,rk3036-cru";
298 reg = <0x20000000 0x1000>;
299 rockchip,grf = <&grf>;
302 assigned-clocks = <&cru PLL_GPLL>;
303 assigned-clock-rates = <594000000>;
306 grf: syscon@20008000 {
307 compatible = "rockchip,rk3036-grf", "syscon", "simple-mfd";
308 reg = <0x20008000 0x1000>;
311 compatible = "syscon-reboot-mode";
313 mode-normal = <BOOT_NORMAL>;
314 mode-recovery = <BOOT_RECOVERY>;
315 mode-bootloader = <BOOT_FASTBOOT>;
316 mode-loader = <BOOT_BL_DOWNLOAD>;
320 acodec: acodec-ana@20030000 {
321 compatible = "rk3036-codec";
322 reg = <0x20030000 0x4000>;
323 rockchip,grf = <&grf>;
324 clock-names = "acodec_pclk";
325 clocks = <&cru PCLK_ACODEC>;
329 hdmi: hdmi@20034000 {
330 compatible = "rockchip,rk3036-inno-hdmi";
331 reg = <0x20034000 0x4000>;
332 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
333 clocks = <&cru PCLK_HDMI>;
334 clock-names = "pclk";
335 rockchip,grf = <&grf>;
336 pinctrl-names = "default";
337 pinctrl-0 = <&hdmi_ctl>;
341 #address-cells = <1>;
347 hdmi_in_vop: endpoint {
348 remote-endpoint = <&vop_out_hdmi>;
358 timer: timer@20044000 {
359 compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer";
360 reg = <0x20044000 0x20>;
361 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
362 clocks = <&xin24m>, <&cru PCLK_TIMER>;
363 clock-names = "timer", "pclk";
367 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
368 reg = <0x20050000 0x10>;
370 clocks = <&cru PCLK_PWM>;
372 pinctrl-names = "default";
373 pinctrl-0 = <&pwm0_pin>;
378 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
379 reg = <0x20050010 0x10>;
381 clocks = <&cru PCLK_PWM>;
383 pinctrl-names = "default";
384 pinctrl-0 = <&pwm1_pin>;
389 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
390 reg = <0x20050020 0x10>;
392 clocks = <&cru PCLK_PWM>;
394 pinctrl-names = "default";
395 pinctrl-0 = <&pwm2_pin>;
400 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
401 reg = <0x20050030 0x10>;
403 clocks = <&cru PCLK_PWM>;
405 pinctrl-names = "default";
406 pinctrl-0 = <&pwm3_pin>;
411 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
412 reg = <0x20056000 0x1000>;
413 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
414 #address-cells = <1>;
417 clocks = <&cru PCLK_I2C1>;
418 pinctrl-names = "default";
419 pinctrl-0 = <&i2c1_xfer>;
424 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
425 reg = <0x2005a000 0x1000>;
426 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
427 #address-cells = <1>;
430 clocks = <&cru PCLK_I2C2>;
431 pinctrl-names = "default";
432 pinctrl-0 = <&i2c2_xfer>;
436 uart0: serial@20060000 {
437 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
438 reg = <0x20060000 0x100>;
439 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
442 clock-frequency = <24000000>;
443 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
444 clock-names = "baudclk", "apb_pclk";
445 pinctrl-names = "default";
446 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
450 uart1: serial@20064000 {
451 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
452 reg = <0x20064000 0x100>;
453 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
456 clock-frequency = <24000000>;
457 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
458 clock-names = "baudclk", "apb_pclk";
459 pinctrl-names = "default";
460 pinctrl-0 = <&uart1_xfer>;
464 uart2: serial@20068000 {
465 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
466 reg = <0x20068000 0x100>;
467 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
470 clock-frequency = <24000000>;
471 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
472 clock-names = "baudclk", "apb_pclk";
473 pinctrl-names = "default";
474 pinctrl-0 = <&uart2_xfer>;
479 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
480 reg = <0x20072000 0x1000>;
481 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
482 #address-cells = <1>;
485 clocks = <&cru PCLK_I2C0>;
486 pinctrl-names = "default";
487 pinctrl-0 = <&i2c0_xfer>;
492 compatible = "rockchip,rockchip-spi";
493 reg = <0x20074000 0x1000>;
494 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
495 clocks = <&cru PCLK_SPI>, <&cru SCLK_SPI>;
496 clock-names = "apb-pclk","spi_pclk";
497 dmas = <&pdma 8>, <&pdma 9>;
498 dma-names = "tx", "rx";
499 pinctrl-names = "default";
500 pinctrl-0 = <&spi_txd &spi_rxd &spi_clk &spi_cs0>;
501 #address-cells = <1>;
507 compatible = "rockchip,rk3036-pinctrl";
508 rockchip,grf = <&grf>;
509 #address-cells = <1>;
513 gpio0: gpio0@2007c000 {
514 compatible = "rockchip,gpio-bank";
515 reg = <0x2007c000 0x100>;
516 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
517 clocks = <&cru PCLK_GPIO0>;
522 interrupt-controller;
523 #interrupt-cells = <2>;
526 gpio1: gpio1@20080000 {
527 compatible = "rockchip,gpio-bank";
528 reg = <0x20080000 0x100>;
529 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
530 clocks = <&cru PCLK_GPIO1>;
535 interrupt-controller;
536 #interrupt-cells = <2>;
539 gpio2: gpio2@20084000 {
540 compatible = "rockchip,gpio-bank";
541 reg = <0x20084000 0x100>;
542 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
543 clocks = <&cru PCLK_GPIO2>;
548 interrupt-controller;
549 #interrupt-cells = <2>;
552 pcfg_pull_default: pcfg_pull_default {
553 bias-pull-pin-default;
556 pcfg_pull_none: pcfg-pull-none {
562 rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>;
568 rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>;
574 rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>;
580 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
585 sdmmc_clk: sdmmc-clk {
586 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>;
589 sdmmc_cmd: sdmmc-cmd {
590 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>;
594 rockchip,pins = <1 RK_PC1 1 &pcfg_pull_default>;
597 sdmmc_bus1: sdmmc-bus1 {
598 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>;
601 sdmmc_bus4: sdmmc-bus4 {
602 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>,
603 <1 RK_PC3 1 &pcfg_pull_default>,
604 <1 RK_PC4 1 &pcfg_pull_default>,
605 <1 RK_PC5 1 &pcfg_pull_default>;
610 sdio_bus1: sdio-bus1 {
611 rockchip,pins = <0 RK_PB3 1 &pcfg_pull_default>;
614 sdio_bus4: sdio-bus4 {
615 rockchip,pins = <0 RK_PB3 1 &pcfg_pull_default>,
616 <0 RK_PB4 1 &pcfg_pull_default>,
617 <0 RK_PB5 1 &pcfg_pull_default>,
618 <0 RK_PB6 1 &pcfg_pull_default>;
622 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_default>;
626 rockchip,pins = <0 RK_PB1 1 &pcfg_pull_none>;
632 * We run eMMC at max speed; bump up drive strength.
633 * We also have external pulls, so disable the internal ones.
636 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
640 rockchip,pins = <2 RK_PA1 2 &pcfg_pull_default>;
643 emmc_bus8: emmc-bus8 {
644 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>,
645 <1 RK_PD1 2 &pcfg_pull_default>,
646 <1 RK_PD2 2 &pcfg_pull_default>,
647 <1 RK_PD3 2 &pcfg_pull_default>,
648 <1 RK_PD4 2 &pcfg_pull_default>,
649 <1 RK_PD5 2 &pcfg_pull_default>,
650 <1 RK_PD6 2 &pcfg_pull_default>,
651 <1 RK_PD7 2 &pcfg_pull_default>;
656 emac_xfer: emac-xfer {
657 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_default>, /* crs_dvalid */
658 <2 RK_PB5 1 &pcfg_pull_default>, /* tx_en */
659 <2 RK_PB6 1 &pcfg_pull_default>, /* mac_clk */
660 <2 RK_PB7 1 &pcfg_pull_default>, /* rx_err */
661 <2 RK_PC0 1 &pcfg_pull_default>, /* rxd1 */
662 <2 RK_PC1 1 &pcfg_pull_default>, /* rxd0 */
663 <2 RK_PC2 1 &pcfg_pull_default>, /* txd1 */
664 <2 RK_PC3 1 &pcfg_pull_default>; /* txd0 */
667 emac_mdio: emac-mdio {
668 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_default>, /* mac_md */
669 <2 RK_PD1 1 &pcfg_pull_default>; /* mac_mdclk */
674 i2c0_xfer: i2c0-xfer {
675 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
676 <0 RK_PA1 1 &pcfg_pull_none>;
681 i2c1_xfer: i2c1-xfer {
682 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,
683 <0 RK_PA3 1 &pcfg_pull_none>;
688 i2c2_xfer: i2c2-xfer {
689 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>,
690 <2 RK_PC5 1 &pcfg_pull_none>;
696 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_default>,
697 <1 RK_PA1 1 &pcfg_pull_default>,
698 <1 RK_PA2 1 &pcfg_pull_default>,
699 <1 RK_PA3 1 &pcfg_pull_default>,
700 <1 RK_PA4 1 &pcfg_pull_default>,
701 <1 RK_PA5 1 &pcfg_pull_default>;
707 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>,
708 <1 RK_PB1 1 &pcfg_pull_none>,
709 <1 RK_PB2 1 &pcfg_pull_none>,
710 <1 RK_PB3 1 &pcfg_pull_none>;
715 uart0_xfer: uart0-xfer {
716 rockchip,pins = <0 RK_PC0 1 &pcfg_pull_default>,
717 <0 RK_PC1 1 &pcfg_pull_none>;
720 uart0_cts: uart0-cts {
721 rockchip,pins = <0 RK_PC2 1 &pcfg_pull_default>;
724 uart0_rts: uart0-rts {
725 rockchip,pins = <0 RK_PC3 1 &pcfg_pull_none>;
730 uart1_xfer: uart1-xfer {
731 rockchip,pins = <2 RK_PC6 1 &pcfg_pull_default>,
732 <2 RK_PC7 1 &pcfg_pull_none>;
734 /* no rts / cts for uart1 */
738 uart2_xfer: uart2-xfer {
739 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>,
740 <1 RK_PC3 2 &pcfg_pull_none>;
742 /* no rts / cts for uart2 */
747 rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>;
751 rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>;
755 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>;
759 rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>;
764 rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>;