arch/arm/boot/dts/rk3036.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2
   3 #include <dt-bindings/gpio/gpio.h>
   4 #include <dt-bindings/interrupt-controller/irq.h>
   5 #include <dt-bindings/interrupt-controller/arm-gic.h>
   6 #include <dt-bindings/pinctrl/rockchip.h>
   7 #include <dt-bindings/clock/rk3036-cru.h>
   8 #include <dt-bindings/soc/rockchip,boot-mode.h>
   9 #include <dt-bindings/power/rk3036-power.h>
  10
  11 / {
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14
  15         compatible = "rockchip,rk3036";
  16
  17         interrupt-parent = <&gic>;
  18
  19         aliases {
  20                 i2c0 = &i2c0;
  21                 i2c1 = &i2c1;
  22                 i2c2 = &i2c2;
  23                 mshc0 = &emmc;
  24                 mshc1 = &sdmmc;
  25                 mshc2 = &sdio;
  26                 serial0 = &uart0;
  27                 serial1 = &uart1;
  28                 serial2 = &uart2;
  29                 spi = &spi;
  30         };
  31
  32         cpus {
  33                 #address-cells = <1>;
  34                 #size-cells = <0>;
  35                 enable-method = "rockchip,rk3036-smp";
  36
  37                 cpu0: cpu@f00 {
  38                         device_type = "cpu";
  39                         compatible = "arm,cortex-a7";
  40                         reg = <0xf00>;
  41                         resets = <&cru SRST_CORE0>;
  42                         operating-points = <
  43                                 /* KHz    uV */
  44                                  816000 1000000
  45                         >;
  46                         clock-latency = <40000>;
  47                         clocks = <&cru ARMCLK>;
  48                 };
  49
  50                 cpu1: cpu@f01 {
  51                         device_type = "cpu";
  52                         compatible = "arm,cortex-a7";
  53                         reg = <0xf01>;
  54                         resets = <&cru SRST_CORE1>;
  55                 };
  56         };
  57
  58         arm-pmu {
  59                 compatible = "arm,cortex-a7-pmu";
  60                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
  61                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
  62                 interrupt-affinity = <&cpu0>, <&cpu1>;
  63         };
  64
  65         display-subsystem {
  66                 compatible = "rockchip,display-subsystem";
  67                 ports = <&vop_out>;
  68         };
  69
  70         timer {
  71                 compatible = "arm,armv7-timer";
  72                 arm,cpu-registers-not-fw-configured;
  73                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
  74                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
  75                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
  76                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
  77                 clock-frequency = <24000000>;
  78         };
  79
  80         xin24m: oscillator {
  81                 compatible = "fixed-clock";
  82                 clock-frequency = <24000000>;
  83                 clock-output-names = "xin24m";
  84                 #clock-cells = <0>;
  85         };
  86
  87         bus_intmem: sram@10080000 {
  88                 compatible = "mmio-sram";
  89                 reg = <0x10080000 0x2000>;
  90                 #address-cells = <1>;
  91                 #size-cells = <1>;
  92                 ranges = <0 0x10080000 0x2000>;
  93
  94                 smp-sram@0 {
  95                         compatible = "rockchip,rk3066-smp-sram";
  96                         reg = <0x00 0x10>;
  97                 };
  98         };
  99
 100         gpu: gpu@10090000 {
 101                 compatible = "rockchip,rk3036-mali", "arm,mali-400";
 102                 reg = <0x10090000 0x10000>;
 103                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 104                              <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 105                              <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 106                              <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 107                 interrupt-names = "gp",
 108                                   "gpmmu",
 109                                   "pp0",
 110                                   "ppmmu0";
 111                 assigned-clocks = <&cru SCLK_GPU>;
 112                 assigned-clock-rates = <100000000>;
 113                 clocks = <&cru SCLK_GPU>, <&cru SCLK_GPU>;
 114                 clock-names = "bus", "core";
 115                 power-domains = <&power RK3036_PD_GPU>;
 116                 resets = <&cru SRST_GPU>;
 117                 status = "disabled";
 118         };
 119
 120         vpu: video-codec@10108000 {
 121                 compatible = "rockchip,rk3036-vpu";
 122                 reg = <0x10108000 0x800>;
 123                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 124                 interrupt-names = "vdpu";
 125                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
 126                 clock-names = "aclk", "hclk";
 127                 iommus = <&vpu_mmu>;
 128                 power-domains = <&power RK3036_PD_VPU>;
 129         };
 130
 131         vpu_mmu: iommu@10108800 {
 132                 compatible = "rockchip,iommu";
 133                 reg = <0x10108800 0x100>;
 134                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 135                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
 136                 clock-names = "aclk", "iface";
 137                 power-domains = <&power RK3036_PD_VPU>;
 138                 #iommu-cells = <0>;
 139         };
 140
 141         vop: vop@10118000 {
 142                 compatible = "rockchip,rk3036-vop";
 143                 reg = <0x10118000 0x19c>;
 144                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 145                 clocks = <&cru ACLK_LCDC>, <&cru SCLK_LCDC>, <&cru HCLK_LCDC>;
 146                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 147                 resets = <&cru SRST_LCDC1_A>, <&cru SRST_LCDC1_H>, <&cru SRST_LCDC1_D>;
 148                 reset-names = "axi", "ahb", "dclk";
 149                 iommus = <&vop_mmu>;
 150                 power-domains = <&power RK3036_PD_VIO>;
 151                 status = "disabled";
 152
 153                 vop_out: port {
 154                         #address-cells = <1>;
 155                         #size-cells = <0>;
 156                         vop_out_hdmi: endpoint@0 {
 157                                 reg = <0>;
 158                                 remote-endpoint = <&hdmi_in_vop>;
 159                         };
 160                 };
 161         };
 162
 163         vop_mmu: iommu@10118300 {
 164                 compatible = "rockchip,iommu";
 165                 reg = <0x10118300 0x100>;
 166                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 167                 clocks = <&cru ACLK_LCDC>, <&cru HCLK_LCDC>;
 168                 clock-names = "aclk", "iface";
 169                 power-domains = <&power RK3036_PD_VIO>;
 170                 #iommu-cells = <0>;
 171                 status = "disabled";
 172         };
 173
 174         qos_gpu: qos@1012d000 {
 175                 compatible = "rockchip,rk3036-qos", "syscon";
 176                 reg = <0x1012d000 0x20>;
 177         };
 178
 179         qos_vpu: qos@1012e000 {
 180                 compatible = "rockchip,rk3036-qos", "syscon";
 181                 reg = <0x1012e000 0x20>;
 182         };
 183
 184         qos_vio: qos@1012f000 {
 185                 compatible = "rockchip,rk3036-qos", "syscon";
 186                 reg = <0x1012f000 0x20>;
 187         };
 188
 189         gic: interrupt-controller@10139000 {
 190                 compatible = "arm,gic-400";
 191                 interrupt-controller;
 192                 #interrupt-cells = <3>;
 193                 #address-cells = <0>;
 194
 195                 reg = <0x10139000 0x1000>,
 196                       <0x1013a000 0x2000>,
 197                       <0x1013c000 0x2000>,
 198                       <0x1013e000 0x2000>;
 199                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 200         };
 201
 202         usb_otg: usb@10180000 {
 203                 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
 204                                 "snps,dwc2";
 205                 reg = <0x10180000 0x40000>;
 206                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 207                 clocks = <&cru HCLK_OTG0>;
 208                 clock-names = "otg";
 209                 dr_mode = "otg";
 210                 g-np-tx-fifo-size = <16>;
 211                 g-rx-fifo-size = <275>;
 212                 g-tx-fifo-size = <256 128 128 64 64 32>;
 213                 status = "disabled";
 214         };
 215
 216         usb_host: usb@101c0000 {
 217                 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
 218                                 "snps,dwc2";
 219                 reg = <0x101c0000 0x40000>;
 220                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 221                 clocks = <&cru HCLK_OTG1>;
 222                 clock-names = "otg";
 223                 dr_mode = "host";
 224                 status = "disabled";
 225         };
 226
 227         emac: ethernet@10200000 {
 228                 compatible = "rockchip,rk3036-emac";
 229                 reg = <0x10200000 0x4000>;
 230                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 231                 rockchip,grf = <&grf>;
 232                 clocks = <&cru HCLK_MAC>, <&cru SCLK_MACREF>, <&cru SCLK_MAC>;
 233                 clock-names = "hclk", "macref", "macclk";
 234                 /*
 235                  * Fix the emac parent clock is DPLL instead of APLL.
 236                  * since that will cause some unstable things if the cpufreq
 237                  * is working. (e.g: the accurate 50MHz what mac_ref need)
 238                  */
 239                 assigned-clocks = <&cru SCLK_MACPLL>;
 240                 assigned-clock-parents = <&cru PLL_DPLL>;
 241                 max-speed = <100>;
 242                 phy-mode = "rmii";
 243                 status = "disabled";
 244         };
 245
 246         sdmmc: mmc@10214000 {
 247                 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
 248                 reg = <0x10214000 0x4000>;
 249                 clock-frequency = <37500000>;
 250                 max-frequency = <37500000>;
 251                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 252                 clock-names = "biu", "ciu";
 253                 fifo-depth = <0x100>;
 254                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 255                 resets = <&cru SRST_MMC0>;
 256                 reset-names = "reset";
 257                 status = "disabled";
 258         };
 259
 260         sdio: mmc@10218000 {
 261                 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
 262                 reg = <0x10218000 0x4000>;
 263                 max-frequency = <37500000>;
 264                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 265                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 266                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 267                 fifo-depth = <0x100>;
 268                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 269                 resets = <&cru SRST_SDIO>;
 270                 reset-names = "reset";
 271                 status = "disabled";
 272         };
 273
 274         emmc: mmc@1021c000 {
 275                 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
 276                 reg = <0x1021c000 0x4000>;
 277                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 278                 bus-width = <8>;
 279                 cap-mmc-highspeed;
 280                 clock-frequency = <37500000>;
 281                 max-frequency = <37500000>;
 282                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 283                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 284                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 285                 rockchip,default-sample-phase = <158>;
 286                 disable-wp;
 287                 dmas = <&pdma 12>;
 288                 dma-names = "rx-tx";
 289                 fifo-depth = <0x100>;
 290                 mmc-ddr-1_8v;
 291                 non-removable;
 292                 pinctrl-names = "default";
 293                 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
 294                 resets = <&cru SRST_EMMC>;
 295                 reset-names = "reset";
 296                 status = "disabled";
 297         };
 298
 299         i2s: i2s@10220000 {
 300                 compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s";
 301                 reg = <0x10220000 0x4000>;
 302                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 303                 clock-names = "i2s_clk", "i2s_hclk";
 304                 clocks = <&cru SCLK_I2S>, <&cru HCLK_I2S>;
 305                 dmas = <&pdma 0>, <&pdma 1>;
 306                 dma-names = "tx", "rx";
 307                 pinctrl-names = "default";
 308                 pinctrl-0 = <&i2s_bus>;
 309                 #sound-dai-cells = <0>;
 310                 status = "disabled";
 311         };
 312
 313         nfc: nand-controller@10500000 {
 314                 compatible = "rockchip,rk3036-nfc",
 315                              "rockchip,rk2928-nfc";
 316                 reg = <0x10500000 0x4000>;
 317                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 318                 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
 319                 clock-names = "ahb", "nfc";
 320                 assigned-clocks = <&cru SCLK_NANDC>;
 321                 assigned-clock-rates = <150000000>;
 322                 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_csn0
 323                              &flash_rdn &flash_rdy &flash_wrn>;
 324                 pinctrl-names = "default";
 325                 status = "disabled";
 326         };
 327
 328         cru: clock-controller@20000000 {
 329                 compatible = "rockchip,rk3036-cru";
 330                 reg = <0x20000000 0x1000>;
 331                 clocks = <&xin24m>;
 332                 clock-names = "xin24m";
 333                 rockchip,grf = <&grf>;
 334                 #clock-cells = <1>;
 335                 #reset-cells = <1>;
 336                 assigned-clocks = <&cru PLL_GPLL>;
 337                 assigned-clock-rates = <594000000>;
 338         };
 339
 340         grf: syscon@20008000 {
 341                 compatible = "rockchip,rk3036-grf", "syscon", "simple-mfd";
 342                 reg = <0x20008000 0x1000>;
 343
 344                 power: power-controller {
 345                         compatible = "rockchip,rk3036-power-controller";
 346                         #power-domain-cells = <1>;
 347                         #address-cells = <1>;
 348                         #size-cells = <0>;
 349
 350                         power-domain@RK3036_PD_VIO {
 351                                 reg = <RK3036_PD_VIO>;
 352                                 clocks = <&cru ACLK_LCDC>,
 353                                          <&cru HCLK_LCDC>,
 354                                          <&cru SCLK_LCDC>;
 355                                 pm_qos = <&qos_vio>;
 356                                 #power-domain-cells = <0>;
 357                         };
 358
 359                         power-domain@RK3036_PD_VPU {
 360                                 reg = <RK3036_PD_VPU>;
 361                                 clocks = <&cru ACLK_VCODEC>,
 362                                          <&cru HCLK_VCODEC>;
 363                                 pm_qos = <&qos_vpu>;
 364                                 #power-domain-cells = <0>;
 365                         };
 366
 367                         power-domain@RK3036_PD_GPU {
 368                                 reg = <RK3036_PD_GPU>;
 369                                 clocks = <&cru SCLK_GPU>;
 370                                 pm_qos = <&qos_gpu>;
 371                                 #power-domain-cells = <0>;
 372                         };
 373                 };
 374
 375                 reboot-mode {
 376                         compatible = "syscon-reboot-mode";
 377                         offset = <0x1d8>;
 378                         mode-normal = <BOOT_NORMAL>;
 379                         mode-recovery = <BOOT_RECOVERY>;
 380                         mode-bootloader = <BOOT_FASTBOOT>;
 381                         mode-loader = <BOOT_BL_DOWNLOAD>;
 382                 };
 383         };
 384
 385         acodec: acodec-ana@20030000 {
 386                 compatible = "rk3036-codec";
 387                 reg = <0x20030000 0x4000>;
 388                 rockchip,grf = <&grf>;
 389                 clock-names = "acodec_pclk";
 390                 clocks = <&cru PCLK_ACODEC>;
 391                 status = "disabled";
 392         };
 393
 394         hdmi: hdmi@20034000 {
 395                 compatible = "rockchip,rk3036-inno-hdmi";
 396                 reg = <0x20034000 0x4000>;
 397                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 398                 clocks = <&cru  PCLK_HDMI>;
 399                 clock-names = "pclk";
 400                 rockchip,grf = <&grf>;
 401                 pinctrl-names = "default";
 402                 pinctrl-0 = <&hdmi_ctl>;
 403                 status = "disabled";
 404
 405                 ports {
 406                         #address-cells = <1>;
 407                         #size-cells = <0>;
 408
 409                         hdmi_in: port@0 {
 410                                 reg = <0>;
 411
 412                                 hdmi_in_vop: endpoint {
 413                                         remote-endpoint = <&vop_out_hdmi>;
 414                                 };
 415                         };
 416
 417                         hdmi_out: port@1 {
 418                                 reg = <1>;
 419                         };
 420                 };
 421         };
 422
 423         timer: timer@20044000 {
 424                 compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer";
 425                 reg = <0x20044000 0x20>;
 426                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 427                 clocks = <&cru PCLK_TIMER>, <&xin24m>;
 428                 clock-names = "pclk", "timer";
 429         };
 430
 431         pwm0: pwm@20050000 {
 432                 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
 433                 reg = <0x20050000 0x10>;
 434                 #pwm-cells = <3>;
 435                 clocks = <&cru PCLK_PWM>;
 436                 pinctrl-names = "default";
 437                 pinctrl-0 = <&pwm0_pin>;
 438                 status = "disabled";
 439         };
 440
 441         pwm1: pwm@20050010 {
 442                 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
 443                 reg = <0x20050010 0x10>;
 444                 #pwm-cells = <3>;
 445                 clocks = <&cru PCLK_PWM>;
 446                 pinctrl-names = "default";
 447                 pinctrl-0 = <&pwm1_pin>;
 448                 status = "disabled";
 449         };
 450
 451         pwm2: pwm@20050020 {
 452                 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
 453                 reg = <0x20050020 0x10>;
 454                 #pwm-cells = <3>;
 455                 clocks = <&cru PCLK_PWM>;
 456                 pinctrl-names = "default";
 457                 pinctrl-0 = <&pwm2_pin>;
 458                 status = "disabled";
 459         };
 460
 461         pwm3: pwm@20050030 {
 462                 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
 463                 reg = <0x20050030 0x10>;
 464                 #pwm-cells = <2>;
 465                 clocks = <&cru PCLK_PWM>;
 466                 pinctrl-names = "default";
 467                 pinctrl-0 = <&pwm3_pin>;
 468                 status = "disabled";
 469         };
 470
 471         i2c1: i2c@20056000 {
 472                 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
 473                 reg = <0x20056000 0x1000>;
 474                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 475                 #address-cells = <1>;
 476                 #size-cells = <0>;
 477                 clock-names = "i2c";
 478                 clocks = <&cru PCLK_I2C1>;
 479                 pinctrl-names = "default";
 480                 pinctrl-0 = <&i2c1_xfer>;
 481                 status = "disabled";
 482         };
 483
 484         i2c2: i2c@2005a000 {
 485                 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
 486                 reg = <0x2005a000 0x1000>;
 487                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 488                 #address-cells = <1>;
 489                 #size-cells = <0>;
 490                 clock-names = "i2c";
 491                 clocks = <&cru PCLK_I2C2>;
 492                 pinctrl-names = "default";
 493                 pinctrl-0 = <&i2c2_xfer>;
 494                 status = "disabled";
 495         };
 496
 497         uart0: serial@20060000 {
 498                 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
 499                 reg = <0x20060000 0x100>;
 500                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 501                 reg-shift = <2>;
 502                 reg-io-width = <4>;
 503                 clock-frequency = <24000000>;
 504                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 505                 clock-names = "baudclk", "apb_pclk";
 506                 pinctrl-names = "default";
 507                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 508                 status = "disabled";
 509         };
 510
 511         uart1: serial@20064000 {
 512                 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
 513                 reg = <0x20064000 0x100>;
 514                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 515                 reg-shift = <2>;
 516                 reg-io-width = <4>;
 517                 clock-frequency = <24000000>;
 518                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 519                 clock-names = "baudclk", "apb_pclk";
 520                 pinctrl-names = "default";
 521                 pinctrl-0 = <&uart1_xfer>;
 522                 status = "disabled";
 523         };
 524
 525         uart2: serial@20068000 {
 526                 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
 527                 reg = <0x20068000 0x100>;
 528                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 529                 reg-shift = <2>;
 530                 reg-io-width = <4>;
 531                 clock-frequency = <24000000>;
 532                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 533                 clock-names = "baudclk", "apb_pclk";
 534                 pinctrl-names = "default";
 535                 pinctrl-0 = <&uart2_xfer>;
 536                 status = "disabled";
 537         };
 538
 539         i2c0: i2c@20072000 {
 540                 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
 541                 reg = <0x20072000 0x1000>;
 542                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 543                 #address-cells = <1>;
 544                 #size-cells = <0>;
 545                 clock-names = "i2c";
 546                 clocks = <&cru PCLK_I2C0>;
 547                 pinctrl-names = "default";
 548                 pinctrl-0 = <&i2c0_xfer>;
 549                 status = "disabled";
 550         };
 551
 552         spi: spi@20074000 {
 553                 compatible = "rockchip,rockchip-spi";
 554                 reg = <0x20074000 0x1000>;
 555                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 556                 clocks = <&cru PCLK_SPI>, <&cru SCLK_SPI>;
 557                 clock-names = "apb-pclk","spi_pclk";
 558                 dmas = <&pdma 8>, <&pdma 9>;
 559                 dma-names = "tx", "rx";
 560                 pinctrl-names = "default";
 561                 pinctrl-0 = <&spi_txd &spi_rxd &spi_clk &spi_cs0>;
 562                 #address-cells = <1>;
 563                 #size-cells = <0>;
 564                 status = "disabled";
 565         };
 566
 567         pdma: dma-controller@20078000 {
 568                 compatible = "arm,pl330", "arm,primecell";
 569                 reg = <0x20078000 0x4000>;
 570                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 571                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 572                 #dma-cells = <1>;
 573                 arm,pl330-broken-no-flushp;
 574                 arm,pl330-periph-burst;
 575                 clocks = <&cru ACLK_DMAC2>;
 576                 clock-names = "apb_pclk";
 577         };
 578
 579         pinctrl: pinctrl {
 580                 compatible = "rockchip,rk3036-pinctrl";
 581                 rockchip,grf = <&grf>;
 582                 #address-cells = <1>;
 583                 #size-cells = <1>;
 584                 ranges;
 585
 586                 gpio0: gpio@2007c000 {
 587                         compatible = "rockchip,gpio-bank";
 588                         reg = <0x2007c000 0x100>;
 589                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 590                         clocks = <&cru PCLK_GPIO0>;
 591
 592                         gpio-controller;
 593                         #gpio-cells = <2>;
 594
 595                         interrupt-controller;
 596                         #interrupt-cells = <2>;
 597                 };
 598
 599                 gpio1: gpio@20080000 {
 600                         compatible = "rockchip,gpio-bank";
 601                         reg = <0x20080000 0x100>;
 602                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 603                         clocks = <&cru PCLK_GPIO1>;
 604
 605                         gpio-controller;
 606                         #gpio-cells = <2>;
 607
 608                         interrupt-controller;
 609                         #interrupt-cells = <2>;
 610                 };
 611
 612                 gpio2: gpio@20084000 {
 613                         compatible = "rockchip,gpio-bank";
 614                         reg = <0x20084000 0x100>;
 615                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 616                         clocks = <&cru PCLK_GPIO2>;
 617
 618                         gpio-controller;
 619                         #gpio-cells = <2>;
 620
 621                         interrupt-controller;
 622                         #interrupt-cells = <2>;
 623                 };
 624
 625                 pcfg_pull_default: pcfg-pull-default {
 626                         bias-pull-pin-default;
 627                 };
 628
 629                 pcfg_pull_none: pcfg-pull-none {
 630                         bias-disable;
 631                 };
 632
 633                 pwm0 {
 634                         pwm0_pin: pwm0-pin {
 635                                 rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>;
 636                         };
 637                 };
 638
 639                 pwm1 {
 640                         pwm1_pin: pwm1-pin {
 641                                 rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>;
 642                         };
 643                 };
 644
 645                 pwm2 {
 646                         pwm2_pin: pwm2-pin {
 647                                 rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>;
 648                         };
 649                 };
 650
 651                 pwm3 {
 652                         pwm3_pin: pwm3-pin {
 653                                 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
 654                         };
 655                 };
 656
 657                 sdmmc {
 658                         sdmmc_clk: sdmmc-clk {
 659                                 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>;
 660                         };
 661
 662                         sdmmc_cmd: sdmmc-cmd {
 663                                 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>;
 664                         };
 665
 666                         sdmmc_cd: sdmmc-cd {
 667                                 rockchip,pins = <1 RK_PC1 1 &pcfg_pull_default>;
 668                         };
 669
 670                         sdmmc_bus1: sdmmc-bus1 {
 671                                 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>;
 672                         };
 673
 674                         sdmmc_bus4: sdmmc-bus4 {
 675                                 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>,
 676                                                 <1 RK_PC3 1 &pcfg_pull_default>,
 677                                                 <1 RK_PC4 1 &pcfg_pull_default>,
 678                                                 <1 RK_PC5 1 &pcfg_pull_default>;
 679                         };
 680                 };
 681
 682                 sdio {
 683                         sdio_bus1: sdio-bus1 {
 684                                 rockchip,pins = <0 RK_PB3 1 &pcfg_pull_default>;
 685                         };
 686
 687                         sdio_bus4: sdio-bus4 {
 688                                 rockchip,pins = <0 RK_PB3 1 &pcfg_pull_default>,
 689                                                 <0 RK_PB4 1 &pcfg_pull_default>,
 690                                                 <0 RK_PB5 1 &pcfg_pull_default>,
 691                                                 <0 RK_PB6 1 &pcfg_pull_default>;
 692                         };
 693
 694                         sdio_cmd: sdio-cmd {
 695                                 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_default>;
 696                         };
 697
 698                         sdio_clk: sdio-clk {
 699                                 rockchip,pins = <0 RK_PB1 1 &pcfg_pull_none>;
 700                         };
 701                 };
 702
 703                 emmc {
 704                         /*
 705                          * We run eMMC at max speed; bump up drive strength.
 706                          * We also have external pulls, so disable the internal ones.
 707                          */
 708                         emmc_clk: emmc-clk {
 709                                 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
 710                         };
 711
 712                         emmc_cmd: emmc-cmd {
 713                                 rockchip,pins = <2 RK_PA1 2 &pcfg_pull_default>;
 714                         };
 715
 716                         emmc_bus8: emmc-bus8 {
 717                                 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>,
 718                                                 <1 RK_PD1 2 &pcfg_pull_default>,
 719                                                 <1 RK_PD2 2 &pcfg_pull_default>,
 720                                                 <1 RK_PD3 2 &pcfg_pull_default>,
 721                                                 <1 RK_PD4 2 &pcfg_pull_default>,
 722                                                 <1 RK_PD5 2 &pcfg_pull_default>,
 723                                                 <1 RK_PD6 2 &pcfg_pull_default>,
 724                                                 <1 RK_PD7 2 &pcfg_pull_default>;
 725                         };
 726                 };
 727
 728                 nfc {
 729                         flash_ale: flash-ale {
 730                                 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_default>;
 731                         };
 732
 733                         flash_bus8: flash-bus8 {
 734                                 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_default>,
 735                                                 <1 RK_PD1 1 &pcfg_pull_default>,
 736                                                 <1 RK_PD2 1 &pcfg_pull_default>,
 737                                                 <1 RK_PD3 1 &pcfg_pull_default>,
 738                                                 <1 RK_PD4 1 &pcfg_pull_default>,
 739                                                 <1 RK_PD5 1 &pcfg_pull_default>,
 740                                                 <1 RK_PD6 1 &pcfg_pull_default>,
 741                                                 <1 RK_PD7 1 &pcfg_pull_default>;
 742                         };
 743
 744                         flash_cle: flash-cle {
 745                                 rockchip,pins = <2 RK_PA1 1 &pcfg_pull_default>;
 746                         };
 747
 748                         flash_csn0: flash-csn0 {
 749                                 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_default>;
 750                         };
 751
 752                         flash_rdn: flash-rdn {
 753                                 rockchip,pins = <2 RK_PA3 1 &pcfg_pull_default>;
 754                         };
 755
 756                         flash_rdy: flash-rdy {
 757                                 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_default>;
 758                         };
 759
 760                         flash_wrn: flash-wrn {
 761                                 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_default>;
 762                         };
 763                 };
 764
 765                 emac {
 766                         emac_xfer: emac-xfer {
 767                                 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_default>, /* crs_dvalid */
 768                                                 <2 RK_PB5 1 &pcfg_pull_default>, /* tx_en */
 769                                                 <2 RK_PB6 1 &pcfg_pull_default>, /* mac_clk */
 770                                                 <2 RK_PB7 1 &pcfg_pull_default>, /* rx_err */
 771                                                 <2 RK_PC0 1 &pcfg_pull_default>, /* rxd1 */
 772                                                 <2 RK_PC1 1 &pcfg_pull_default>, /* rxd0 */
 773                                                 <2 RK_PC2 1 &pcfg_pull_default>, /* txd1 */
 774                                                 <2 RK_PC3 1 &pcfg_pull_default>; /* txd0 */
 775                         };
 776
 777                         emac_mdio: emac-mdio {
 778                                 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_default>, /* mac_md */
 779                                                 <2 RK_PD1 1 &pcfg_pull_default>; /* mac_mdclk */
 780                         };
 781                 };
 782
 783                 i2c0 {
 784                         i2c0_xfer: i2c0-xfer {
 785                                 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
 786                                                 <0 RK_PA1 1 &pcfg_pull_none>;
 787                         };
 788                 };
 789
 790                 i2c1 {
 791                         i2c1_xfer: i2c1-xfer {
 792                                 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,
 793                                                 <0 RK_PA3 1 &pcfg_pull_none>;
 794                         };
 795                 };
 796
 797                 i2c2 {
 798                         i2c2_xfer: i2c2-xfer {
 799                                 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>,
 800                                                 <2 RK_PC5 1 &pcfg_pull_none>;
 801                         };
 802                 };
 803
 804                 i2s {
 805                         i2s_bus: i2s-bus {
 806                                 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_default>,
 807                                                 <1 RK_PA1 1 &pcfg_pull_default>,
 808                                                 <1 RK_PA2 1 &pcfg_pull_default>,
 809                                                 <1 RK_PA3 1 &pcfg_pull_default>,
 810                                                 <1 RK_PA4 1 &pcfg_pull_default>,
 811                                                 <1 RK_PA5 1 &pcfg_pull_default>;
 812                         };
 813                 };
 814
 815                 hdmi {
 816                         hdmi_ctl: hdmi-ctl {
 817                                 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>,
 818                                                 <1 RK_PB1 1 &pcfg_pull_none>,
 819                                                 <1 RK_PB2 1 &pcfg_pull_none>,
 820                                                 <1 RK_PB3 1 &pcfg_pull_none>;
 821                         };
 822                 };
 823
 824                 uart0 {
 825                         uart0_xfer: uart0-xfer {
 826                                 rockchip,pins = <0 RK_PC0 1 &pcfg_pull_default>,
 827                                                 <0 RK_PC1 1 &pcfg_pull_none>;
 828                         };
 829
 830                         uart0_cts: uart0-cts {
 831                                 rockchip,pins = <0 RK_PC2 1 &pcfg_pull_default>;
 832                         };
 833
 834                         uart0_rts: uart0-rts {
 835                                 rockchip,pins = <0 RK_PC3 1 &pcfg_pull_none>;
 836                         };
 837                 };
 838
 839                 uart1 {
 840                         uart1_xfer: uart1-xfer {
 841                                 rockchip,pins = <2 RK_PC6 1 &pcfg_pull_default>,
 842                                                 <2 RK_PC7 1 &pcfg_pull_none>;
 843                         };
 844                         /* no rts / cts for uart1 */
 845                 };
 846
 847                 uart2 {
 848                         uart2_xfer: uart2-xfer {
 849                                 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>,
 850                                                 <1 RK_PC3 2 &pcfg_pull_none>;
 851                         };
 852                         /* no rts / cts for uart2 */
 853                 };
 854
 855                 spi-pins {
 856                         spi_txd:spi-txd {
 857                                 rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>;
 858                         };
 859
 860                         spi_rxd:spi-rxd {
 861                                 rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>;
 862                         };
 863
 864                         spi_clk:spi-clk {
 865                                 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>;
 866                         };
 867
 868                         spi_cs0:spi-cs0 {
 869                                 rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>;
 870
 871                         };
 872
 873                         spi_cs1:spi-cs1 {
 874                                 rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>;
 875
 876                         };
 877                 };
 878         };
 879 };