1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3036-cru.h>
8 #include <dt-bindings/soc/rockchip,boot-mode.h>
9 #include <dt-bindings/power/rk3036-power.h>
15 compatible = "rockchip,rk3036";
17 interrupt-parent = <&gic>;
35 enable-method = "rockchip,rk3036-smp";
39 compatible = "arm,cortex-a7";
41 resets = <&cru SRST_CORE0>;
46 clock-latency = <40000>;
47 clocks = <&cru ARMCLK>;
52 compatible = "arm,cortex-a7";
54 resets = <&cru SRST_CORE1>;
59 compatible = "arm,cortex-a7-pmu";
60 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
61 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
62 interrupt-affinity = <&cpu0>, <&cpu1>;
66 compatible = "rockchip,display-subsystem";
71 compatible = "arm,armv7-timer";
72 arm,cpu-registers-not-fw-configured;
73 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
74 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
75 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
76 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
77 clock-frequency = <24000000>;
81 compatible = "fixed-clock";
82 clock-frequency = <24000000>;
83 clock-output-names = "xin24m";
87 bus_intmem: sram@10080000 {
88 compatible = "mmio-sram";
89 reg = <0x10080000 0x2000>;
92 ranges = <0 0x10080000 0x2000>;
95 compatible = "rockchip,rk3066-smp-sram";
101 compatible = "rockchip,rk3036-mali", "arm,mali-400";
102 reg = <0x10090000 0x10000>;
103 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
104 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
105 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
106 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
107 interrupt-names = "gp",
111 assigned-clocks = <&cru SCLK_GPU>;
112 assigned-clock-rates = <100000000>;
113 clocks = <&cru SCLK_GPU>, <&cru SCLK_GPU>;
114 clock-names = "bus", "core";
115 power-domains = <&power RK3036_PD_GPU>;
116 resets = <&cru SRST_GPU>;
120 vpu: video-codec@10108000 {
121 compatible = "rockchip,rk3036-vpu";
122 reg = <0x10108000 0x800>;
123 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
124 interrupt-names = "vdpu";
125 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
126 clock-names = "aclk", "hclk";
128 power-domains = <&power RK3036_PD_VPU>;
131 vpu_mmu: iommu@10108800 {
132 compatible = "rockchip,iommu";
133 reg = <0x10108800 0x100>;
134 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
135 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
136 clock-names = "aclk", "iface";
137 power-domains = <&power RK3036_PD_VPU>;
142 compatible = "rockchip,rk3036-vop";
143 reg = <0x10118000 0x19c>;
144 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
145 clocks = <&cru ACLK_LCDC>, <&cru SCLK_LCDC>, <&cru HCLK_LCDC>;
146 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
147 resets = <&cru SRST_LCDC1_A>, <&cru SRST_LCDC1_H>, <&cru SRST_LCDC1_D>;
148 reset-names = "axi", "ahb", "dclk";
150 power-domains = <&power RK3036_PD_VIO>;
154 #address-cells = <1>;
156 vop_out_hdmi: endpoint@0 {
158 remote-endpoint = <&hdmi_in_vop>;
163 vop_mmu: iommu@10118300 {
164 compatible = "rockchip,iommu";
165 reg = <0x10118300 0x100>;
166 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
167 clocks = <&cru ACLK_LCDC>, <&cru HCLK_LCDC>;
168 clock-names = "aclk", "iface";
169 power-domains = <&power RK3036_PD_VIO>;
174 qos_gpu: qos@1012d000 {
175 compatible = "rockchip,rk3036-qos", "syscon";
176 reg = <0x1012d000 0x20>;
179 qos_vpu: qos@1012e000 {
180 compatible = "rockchip,rk3036-qos", "syscon";
181 reg = <0x1012e000 0x20>;
184 qos_vio: qos@1012f000 {
185 compatible = "rockchip,rk3036-qos", "syscon";
186 reg = <0x1012f000 0x20>;
189 gic: interrupt-controller@10139000 {
190 compatible = "arm,gic-400";
191 interrupt-controller;
192 #interrupt-cells = <3>;
193 #address-cells = <0>;
195 reg = <0x10139000 0x1000>,
199 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
202 usb_otg: usb@10180000 {
203 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
205 reg = <0x10180000 0x40000>;
206 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
207 clocks = <&cru HCLK_OTG0>;
210 g-np-tx-fifo-size = <16>;
211 g-rx-fifo-size = <275>;
212 g-tx-fifo-size = <256 128 128 64 64 32>;
216 usb_host: usb@101c0000 {
217 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
219 reg = <0x101c0000 0x40000>;
220 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
221 clocks = <&cru HCLK_OTG1>;
227 emac: ethernet@10200000 {
228 compatible = "rockchip,rk3036-emac", "snps,arc-emac";
229 reg = <0x10200000 0x4000>;
230 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
231 #address-cells = <1>;
233 rockchip,grf = <&grf>;
234 clocks = <&cru HCLK_MAC>, <&cru SCLK_MACREF>, <&cru SCLK_MAC>;
235 clock-names = "hclk", "macref", "macclk";
237 * Fix the emac parent clock is DPLL instead of APLL.
238 * since that will cause some unstable things if the cpufreq
239 * is working. (e.g: the accurate 50MHz what mac_ref need)
241 assigned-clocks = <&cru SCLK_MACPLL>;
242 assigned-clock-parents = <&cru PLL_DPLL>;
248 sdmmc: mmc@10214000 {
249 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
250 reg = <0x10214000 0x4000>;
251 clock-frequency = <37500000>;
252 max-frequency = <37500000>;
253 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
254 clock-names = "biu", "ciu";
255 fifo-depth = <0x100>;
256 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
257 resets = <&cru SRST_MMC0>;
258 reset-names = "reset";
263 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
264 reg = <0x10218000 0x4000>;
265 max-frequency = <37500000>;
266 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
267 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
268 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
269 fifo-depth = <0x100>;
270 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
271 resets = <&cru SRST_SDIO>;
272 reset-names = "reset";
277 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
278 reg = <0x1021c000 0x4000>;
279 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
282 clock-frequency = <37500000>;
283 max-frequency = <37500000>;
284 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
285 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
286 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
287 rockchip,default-sample-phase = <158>;
291 fifo-depth = <0x100>;
294 pinctrl-names = "default";
295 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
296 resets = <&cru SRST_EMMC>;
297 reset-names = "reset";
302 compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s";
303 reg = <0x10220000 0x4000>;
304 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
305 clock-names = "i2s_clk", "i2s_hclk";
306 clocks = <&cru SCLK_I2S>, <&cru HCLK_I2S>;
307 dmas = <&pdma 0>, <&pdma 1>;
308 dma-names = "tx", "rx";
309 pinctrl-names = "default";
310 pinctrl-0 = <&i2s_bus>;
311 #sound-dai-cells = <0>;
315 nfc: nand-controller@10500000 {
316 compatible = "rockchip,rk3036-nfc",
317 "rockchip,rk2928-nfc";
318 reg = <0x10500000 0x4000>;
319 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
320 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
321 clock-names = "ahb", "nfc";
322 assigned-clocks = <&cru SCLK_NANDC>;
323 assigned-clock-rates = <150000000>;
324 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_csn0
325 &flash_rdn &flash_rdy &flash_wrn>;
326 pinctrl-names = "default";
330 cru: clock-controller@20000000 {
331 compatible = "rockchip,rk3036-cru";
332 reg = <0x20000000 0x1000>;
334 clock-names = "xin24m";
335 rockchip,grf = <&grf>;
338 assigned-clocks = <&cru PLL_GPLL>;
339 assigned-clock-rates = <594000000>;
342 grf: syscon@20008000 {
343 compatible = "rockchip,rk3036-grf", "syscon", "simple-mfd";
344 reg = <0x20008000 0x1000>;
346 power: power-controller {
347 compatible = "rockchip,rk3036-power-controller";
348 #power-domain-cells = <1>;
349 #address-cells = <1>;
352 power-domain@RK3036_PD_VIO {
353 reg = <RK3036_PD_VIO>;
354 clocks = <&cru ACLK_LCDC>,
358 #power-domain-cells = <0>;
361 power-domain@RK3036_PD_VPU {
362 reg = <RK3036_PD_VPU>;
363 clocks = <&cru ACLK_VCODEC>,
366 #power-domain-cells = <0>;
369 power-domain@RK3036_PD_GPU {
370 reg = <RK3036_PD_GPU>;
371 clocks = <&cru SCLK_GPU>;
373 #power-domain-cells = <0>;
378 compatible = "syscon-reboot-mode";
380 mode-normal = <BOOT_NORMAL>;
381 mode-recovery = <BOOT_RECOVERY>;
382 mode-bootloader = <BOOT_FASTBOOT>;
383 mode-loader = <BOOT_BL_DOWNLOAD>;
387 acodec: acodec-ana@20030000 {
388 compatible = "rk3036-codec";
389 reg = <0x20030000 0x4000>;
390 rockchip,grf = <&grf>;
391 clock-names = "acodec_pclk";
392 clocks = <&cru PCLK_ACODEC>;
396 hdmi: hdmi@20034000 {
397 compatible = "rockchip,rk3036-inno-hdmi";
398 reg = <0x20034000 0x4000>;
399 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
400 clocks = <&cru PCLK_HDMI>;
401 clock-names = "pclk";
402 rockchip,grf = <&grf>;
403 pinctrl-names = "default";
404 pinctrl-0 = <&hdmi_ctl>;
408 #address-cells = <1>;
410 hdmi_in_vop: endpoint@0 {
412 remote-endpoint = <&vop_out_hdmi>;
417 timer: timer@20044000 {
418 compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer";
419 reg = <0x20044000 0x20>;
420 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
421 clocks = <&cru PCLK_TIMER>, <&xin24m>;
422 clock-names = "pclk", "timer";
426 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
427 reg = <0x20050000 0x10>;
429 clocks = <&cru PCLK_PWM>;
430 pinctrl-names = "default";
431 pinctrl-0 = <&pwm0_pin>;
436 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
437 reg = <0x20050010 0x10>;
439 clocks = <&cru PCLK_PWM>;
440 pinctrl-names = "default";
441 pinctrl-0 = <&pwm1_pin>;
446 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
447 reg = <0x20050020 0x10>;
449 clocks = <&cru PCLK_PWM>;
450 pinctrl-names = "default";
451 pinctrl-0 = <&pwm2_pin>;
456 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
457 reg = <0x20050030 0x10>;
459 clocks = <&cru PCLK_PWM>;
460 pinctrl-names = "default";
461 pinctrl-0 = <&pwm3_pin>;
466 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
467 reg = <0x20056000 0x1000>;
468 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
469 #address-cells = <1>;
472 clocks = <&cru PCLK_I2C1>;
473 pinctrl-names = "default";
474 pinctrl-0 = <&i2c1_xfer>;
479 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
480 reg = <0x2005a000 0x1000>;
481 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
482 #address-cells = <1>;
485 clocks = <&cru PCLK_I2C2>;
486 pinctrl-names = "default";
487 pinctrl-0 = <&i2c2_xfer>;
491 uart0: serial@20060000 {
492 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
493 reg = <0x20060000 0x100>;
494 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
497 clock-frequency = <24000000>;
498 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
499 clock-names = "baudclk", "apb_pclk";
500 pinctrl-names = "default";
501 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
505 uart1: serial@20064000 {
506 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
507 reg = <0x20064000 0x100>;
508 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
511 clock-frequency = <24000000>;
512 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
513 clock-names = "baudclk", "apb_pclk";
514 pinctrl-names = "default";
515 pinctrl-0 = <&uart1_xfer>;
519 uart2: serial@20068000 {
520 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
521 reg = <0x20068000 0x100>;
522 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
525 clock-frequency = <24000000>;
526 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
527 clock-names = "baudclk", "apb_pclk";
528 pinctrl-names = "default";
529 pinctrl-0 = <&uart2_xfer>;
534 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
535 reg = <0x20072000 0x1000>;
536 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
537 #address-cells = <1>;
540 clocks = <&cru PCLK_I2C0>;
541 pinctrl-names = "default";
542 pinctrl-0 = <&i2c0_xfer>;
547 compatible = "rockchip,rockchip-spi";
548 reg = <0x20074000 0x1000>;
549 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
550 clocks = <&cru PCLK_SPI>, <&cru SCLK_SPI>;
551 clock-names = "apb-pclk","spi_pclk";
552 dmas = <&pdma 8>, <&pdma 9>;
553 dma-names = "tx", "rx";
554 pinctrl-names = "default";
555 pinctrl-0 = <&spi_txd &spi_rxd &spi_clk &spi_cs0>;
556 #address-cells = <1>;
561 pdma: dma-controller@20078000 {
562 compatible = "arm,pl330", "arm,primecell";
563 reg = <0x20078000 0x4000>;
564 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
565 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
567 arm,pl330-broken-no-flushp;
568 arm,pl330-periph-burst;
569 clocks = <&cru ACLK_DMAC2>;
570 clock-names = "apb_pclk";
574 compatible = "rockchip,rk3036-pinctrl";
575 rockchip,grf = <&grf>;
576 #address-cells = <1>;
580 gpio0: gpio@2007c000 {
581 compatible = "rockchip,gpio-bank";
582 reg = <0x2007c000 0x100>;
583 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
584 clocks = <&cru PCLK_GPIO0>;
589 interrupt-controller;
590 #interrupt-cells = <2>;
593 gpio1: gpio@20080000 {
594 compatible = "rockchip,gpio-bank";
595 reg = <0x20080000 0x100>;
596 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
597 clocks = <&cru PCLK_GPIO1>;
602 interrupt-controller;
603 #interrupt-cells = <2>;
606 gpio2: gpio@20084000 {
607 compatible = "rockchip,gpio-bank";
608 reg = <0x20084000 0x100>;
609 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
610 clocks = <&cru PCLK_GPIO2>;
615 interrupt-controller;
616 #interrupt-cells = <2>;
619 pcfg_pull_default: pcfg-pull-default {
620 bias-pull-pin-default;
623 pcfg_pull_none: pcfg-pull-none {
629 rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>;
635 rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>;
641 rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>;
647 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
652 sdmmc_clk: sdmmc-clk {
653 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>;
656 sdmmc_cmd: sdmmc-cmd {
657 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>;
661 rockchip,pins = <1 RK_PC1 1 &pcfg_pull_default>;
664 sdmmc_bus1: sdmmc-bus1 {
665 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>;
668 sdmmc_bus4: sdmmc-bus4 {
669 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>,
670 <1 RK_PC3 1 &pcfg_pull_default>,
671 <1 RK_PC4 1 &pcfg_pull_default>,
672 <1 RK_PC5 1 &pcfg_pull_default>;
677 sdio_bus1: sdio-bus1 {
678 rockchip,pins = <0 RK_PB3 1 &pcfg_pull_default>;
681 sdio_bus4: sdio-bus4 {
682 rockchip,pins = <0 RK_PB3 1 &pcfg_pull_default>,
683 <0 RK_PB4 1 &pcfg_pull_default>,
684 <0 RK_PB5 1 &pcfg_pull_default>,
685 <0 RK_PB6 1 &pcfg_pull_default>;
689 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_default>;
693 rockchip,pins = <0 RK_PB1 1 &pcfg_pull_none>;
699 * We run eMMC at max speed; bump up drive strength.
700 * We also have external pulls, so disable the internal ones.
703 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
707 rockchip,pins = <2 RK_PA1 2 &pcfg_pull_default>;
710 emmc_bus8: emmc-bus8 {
711 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>,
712 <1 RK_PD1 2 &pcfg_pull_default>,
713 <1 RK_PD2 2 &pcfg_pull_default>,
714 <1 RK_PD3 2 &pcfg_pull_default>,
715 <1 RK_PD4 2 &pcfg_pull_default>,
716 <1 RK_PD5 2 &pcfg_pull_default>,
717 <1 RK_PD6 2 &pcfg_pull_default>,
718 <1 RK_PD7 2 &pcfg_pull_default>;
723 flash_ale: flash-ale {
724 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_default>;
727 flash_bus8: flash-bus8 {
728 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_default>,
729 <1 RK_PD1 1 &pcfg_pull_default>,
730 <1 RK_PD2 1 &pcfg_pull_default>,
731 <1 RK_PD3 1 &pcfg_pull_default>,
732 <1 RK_PD4 1 &pcfg_pull_default>,
733 <1 RK_PD5 1 &pcfg_pull_default>,
734 <1 RK_PD6 1 &pcfg_pull_default>,
735 <1 RK_PD7 1 &pcfg_pull_default>;
738 flash_cle: flash-cle {
739 rockchip,pins = <2 RK_PA1 1 &pcfg_pull_default>;
742 flash_csn0: flash-csn0 {
743 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_default>;
746 flash_rdn: flash-rdn {
747 rockchip,pins = <2 RK_PA3 1 &pcfg_pull_default>;
750 flash_rdy: flash-rdy {
751 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_default>;
754 flash_wrn: flash-wrn {
755 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_default>;
760 emac_xfer: emac-xfer {
761 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_default>, /* crs_dvalid */
762 <2 RK_PB5 1 &pcfg_pull_default>, /* tx_en */
763 <2 RK_PB6 1 &pcfg_pull_default>, /* mac_clk */
764 <2 RK_PB7 1 &pcfg_pull_default>, /* rx_err */
765 <2 RK_PC0 1 &pcfg_pull_default>, /* rxd1 */
766 <2 RK_PC1 1 &pcfg_pull_default>, /* rxd0 */
767 <2 RK_PC2 1 &pcfg_pull_default>, /* txd1 */
768 <2 RK_PC3 1 &pcfg_pull_default>; /* txd0 */
771 emac_mdio: emac-mdio {
772 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_default>, /* mac_md */
773 <2 RK_PD1 1 &pcfg_pull_default>; /* mac_mdclk */
778 i2c0_xfer: i2c0-xfer {
779 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
780 <0 RK_PA1 1 &pcfg_pull_none>;
785 i2c1_xfer: i2c1-xfer {
786 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,
787 <0 RK_PA3 1 &pcfg_pull_none>;
792 i2c2_xfer: i2c2-xfer {
793 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>,
794 <2 RK_PC5 1 &pcfg_pull_none>;
800 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_default>,
801 <1 RK_PA1 1 &pcfg_pull_default>,
802 <1 RK_PA2 1 &pcfg_pull_default>,
803 <1 RK_PA3 1 &pcfg_pull_default>,
804 <1 RK_PA4 1 &pcfg_pull_default>,
805 <1 RK_PA5 1 &pcfg_pull_default>;
811 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>,
812 <1 RK_PB1 1 &pcfg_pull_none>,
813 <1 RK_PB2 1 &pcfg_pull_none>,
814 <1 RK_PB3 1 &pcfg_pull_none>;
819 uart0_xfer: uart0-xfer {
820 rockchip,pins = <0 RK_PC0 1 &pcfg_pull_default>,
821 <0 RK_PC1 1 &pcfg_pull_none>;
824 uart0_cts: uart0-cts {
825 rockchip,pins = <0 RK_PC2 1 &pcfg_pull_default>;
828 uart0_rts: uart0-rts {
829 rockchip,pins = <0 RK_PC3 1 &pcfg_pull_none>;
834 uart1_xfer: uart1-xfer {
835 rockchip,pins = <2 RK_PC6 1 &pcfg_pull_default>,
836 <2 RK_PC7 1 &pcfg_pull_none>;
838 /* no rts / cts for uart1 */
842 uart2_xfer: uart2-xfer {
843 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>,
844 <1 RK_PC3 2 &pcfg_pull_none>;
846 /* no rts / cts for uart2 */
851 rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>;
855 rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>;
859 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>;
863 rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>;
868 rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>;