1 // SPDX-License-Identifier: GPL-2.0
3 * Base Device Tree Source for the Renesas RZ/N1D (R9A06G032)
5 * Copyright (C) 2018 Renesas Electronics Europe Limited
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/r9a06g032-sysctrl.h>
13 compatible = "renesas,r9a06g032";
23 compatible = "arm,cortex-a7";
25 clocks = <&sysctrl R9A06G032_CLK_A7MP>;
30 compatible = "arm,cortex-a7";
32 clocks = <&sysctrl R9A06G032_CLK_A7MP>;
33 enable-method = "renesas,r9a06g032-smp";
34 cpu-release-addr = <0 0x4000c204>;
38 ext_jtag_clk: extjtagclk {
40 compatible = "fixed-clock";
41 clock-frequency = <0>;
46 compatible = "fixed-clock";
47 clock-frequency = <40000000>;
50 ext_rgmii_ref: extrgmiiref {
52 compatible = "fixed-clock";
53 clock-frequency = <0>;
56 ext_rtc_clk: extrtcclk {
58 compatible = "fixed-clock";
59 clock-frequency = <0>;
63 compatible = "simple-bus";
66 interrupt-parent = <&gic>;
70 compatible = "renesas,r9a06g032-rtc", "renesas,rzn1-rtc";
71 reg = <0x40006000 0x1000>;
72 interrupts = <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>,
73 <GIC_SPI 67 IRQ_TYPE_EDGE_RISING>,
74 <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>;
75 interrupt-names = "alarm", "timer", "pps";
76 clocks = <&sysctrl R9A06G032_HCLK_RTC>;
78 power-domains = <&sysctrl>;
82 wdt0: watchdog@40008000 {
83 compatible = "renesas,r9a06g032-wdt", "renesas,rzn1-wdt";
84 reg = <0x40008000 0x1000>;
85 interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
86 clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>;
90 wdt1: watchdog@40009000 {
91 compatible = "renesas,r9a06g032-wdt", "renesas,rzn1-wdt";
92 reg = <0x40009000 0x1000>;
93 interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>;
94 clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>;
98 sysctrl: system-controller@4000c000 {
99 compatible = "renesas,r9a06g032-sysctrl";
100 reg = <0x4000c000 0x1000>;
103 #power-domain-cells = <0>;
105 clocks = <&ext_mclk>, <&ext_rtc_clk>,
106 <&ext_jtag_clk>, <&ext_rgmii_ref>;
107 clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";
108 #address-cells = <1>;
111 dmamux: dma-router@a0 {
112 compatible = "renesas,rzn1-dmamux";
116 dma-masters = <&dma0 &dma1>;
120 pci_usb: pci@40030000 {
121 compatible = "renesas,pci-r9a06g032", "renesas,pci-rzn1";
123 clocks = <&sysctrl R9A06G032_HCLK_USBH>,
124 <&sysctrl R9A06G032_HCLK_USBPM>,
125 <&sysctrl R9A06G032_CLK_PCI_USB>;
126 clock-names = "hclkh", "hclkpm", "pciclk";
127 power-domains = <&sysctrl>;
128 reg = <0x40030000 0xc00>,
130 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
134 #address-cells = <3>;
136 #interrupt-cells = <1>;
137 ranges = <0x02000000 0 0x40020000 0x40020000 0 0x00010000>;
138 /* Should map all possible DDR as inbound ranges, but
139 * the IP only supports a 256MB, 512MB, or 1GB window.
140 * flags, PCI addr (64-bit), CPU addr, PCI size (64-bit)
142 dma-ranges = <0x42000000 0 0x80000000 0x80000000 0 0x40000000>;
143 interrupt-map-mask = <0xf800 0 0 0x7>;
144 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH
145 0x0800 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH
146 0x1000 0 0 2 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
149 reg = <0x800 0 0 0 0>;
155 reg = <0x1000 0 0 0 0>;
161 uart0: serial@40060000 {
162 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart";
163 reg = <0x40060000 0x400>;
164 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
167 clocks = <&sysctrl R9A06G032_CLK_UART0>, <&sysctrl R9A06G032_HCLK_UART0>;
168 clock-names = "baudclk", "apb_pclk";
172 uart1: serial@40061000 {
173 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart";
174 reg = <0x40061000 0x400>;
175 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
178 clocks = <&sysctrl R9A06G032_CLK_UART1>, <&sysctrl R9A06G032_HCLK_UART1>;
179 clock-names = "baudclk", "apb_pclk";
183 uart2: serial@40062000 {
184 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart";
185 reg = <0x40062000 0x400>;
186 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
189 clocks = <&sysctrl R9A06G032_CLK_UART2>, <&sysctrl R9A06G032_HCLK_UART2>;
190 clock-names = "baudclk", "apb_pclk";
194 uart3: serial@50000000 {
195 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
196 reg = <0x50000000 0x400>;
197 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
200 clocks = <&sysctrl R9A06G032_CLK_UART3>, <&sysctrl R9A06G032_HCLK_UART3>;
201 clock-names = "baudclk", "apb_pclk";
202 dmas = <&dmamux 0 0 0 0 0 1>, <&dmamux 1 0 0 0 1 1>;
203 dma-names = "rx", "tx";
207 uart4: serial@50001000 {
208 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
209 reg = <0x50001000 0x400>;
210 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
213 clocks = <&sysctrl R9A06G032_CLK_UART4>, <&sysctrl R9A06G032_HCLK_UART4>;
214 clock-names = "baudclk", "apb_pclk";
215 dmas = <&dmamux 2 0 0 0 2 1>, <&dmamux 3 0 0 0 3 1>;
216 dma-names = "rx", "tx";
220 uart5: serial@50002000 {
221 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
222 reg = <0x50002000 0x400>;
223 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
226 clocks = <&sysctrl R9A06G032_CLK_UART5>, <&sysctrl R9A06G032_HCLK_UART5>;
227 clock-names = "baudclk", "apb_pclk";
228 dmas = <&dmamux 4 0 0 0 4 1>, <&dmamux 5 0 0 0 5 1>;
229 dma-names = "rx", "tx";
233 uart6: serial@50003000 {
234 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
235 reg = <0x50003000 0x400>;
236 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
239 clocks = <&sysctrl R9A06G032_CLK_UART6>, <&sysctrl R9A06G032_HCLK_UART6>;
240 clock-names = "baudclk", "apb_pclk";
241 dmas = <&dmamux 6 0 0 0 6 1>, <&dmamux 7 0 0 0 7 1>;
242 dma-names = "rx", "tx";
246 uart7: serial@50004000 {
247 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
248 reg = <0x50004000 0x400>;
249 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
252 clocks = <&sysctrl R9A06G032_CLK_UART7>, <&sysctrl R9A06G032_HCLK_UART7>;
253 clock-names = "baudclk", "apb_pclk";
254 dmas = <&dmamux 4 0 0 0 20 1>, <&dmamux 5 0 0 0 21 1>;
255 dma-names = "rx", "tx";
259 pinctrl: pinctrl@40067000 {
260 compatible = "renesas,r9a06g032-pinctrl", "renesas,rzn1-pinctrl";
261 reg = <0x40067000 0x1000>, <0x51000000 0x480>;
262 clocks = <&sysctrl R9A06G032_HCLK_PINCONFIG>;
267 nand_controller: nand-controller@40102000 {
268 compatible = "renesas,r9a06g032-nandc", "renesas,rzn1-nandc";
269 reg = <0x40102000 0x2000>;
270 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
271 clocks = <&sysctrl R9A06G032_HCLK_NAND>, <&sysctrl R9A06G032_CLK_NAND>;
272 clock-names = "hclk", "eclk";
273 power-domains = <&sysctrl>;
274 #address-cells = <1>;
279 dma0: dma-controller@40104000 {
280 compatible = "renesas,r9a06g032-dma", "renesas,rzn1-dma";
281 reg = <0x40104000 0x1000>;
282 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
283 clock-names = "hclk";
284 clocks = <&sysctrl R9A06G032_HCLK_DMA0>;
289 block_size = <0xfff>;
293 dma1: dma-controller@40105000 {
294 compatible = "renesas,r9a06g032-dma", "renesas,rzn1-dma";
295 reg = <0x40105000 0x1000>;
296 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
297 clock-names = "hclk";
298 clocks = <&sysctrl R9A06G032_HCLK_DMA1>;
303 block_size = <0xfff>;
307 gic: interrupt-controller@44101000 {
308 compatible = "arm,gic-400", "arm,cortex-a7-gic";
309 interrupt-controller;
310 #interrupt-cells = <3>;
311 reg = <0x44101000 0x1000>, /* Distributer */
312 <0x44102000 0x2000>, /* CPU interface */
313 <0x44104000 0x2000>, /* Virt interface control */
314 <0x44106000 0x2000>; /* Virt CPU interface */
316 <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
321 compatible = "arm,armv7-timer";
322 interrupt-parent = <&gic>;
323 arm,cpu-registers-not-fw-configured;
326 <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
327 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
328 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
329 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
334 compatible = "usb-nop-xceiv";