arch/arm/boot/dts/r8a7794.dtsi

   1 /*
   2  * Device Tree Source for the r8a7794 SoC
   3  *
   4  * Copyright (C) 2014 Renesas Electronics Corporation
   5  * Copyright (C) 2014 Ulrich Hecht
   6  *
   7  * This file is licensed under the terms of the GNU General Public License
   8  * version 2.  This program is licensed "as is" without any warranty of any
   9  * kind, whether express or implied.
  10  */
  11
  12 #include <dt-bindings/clock/r8a7794-clock.h>
  13 #include <dt-bindings/interrupt-controller/arm-gic.h>
  14 #include <dt-bindings/interrupt-controller/irq.h>
  15 #include <dt-bindings/power/r8a7794-sysc.h>
  16
  17 / {
  18         compatible = "renesas,r8a7794";
  19         interrupt-parent = <&gic>;
  20         #address-cells = <2>;
  21         #size-cells = <2>;
  22
  23         aliases {
  24                 i2c0 = &i2c0;
  25                 i2c1 = &i2c1;
  26                 i2c2 = &i2c2;
  27                 i2c3 = &i2c3;
  28                 i2c4 = &i2c4;
  29                 i2c5 = &i2c5;
  30                 i2c6 = &i2c6;
  31                 i2c7 = &i2c7;
  32                 spi0 = &qspi;
  33                 vin0 = &vin0;
  34                 vin1 = &vin1;
  35         };
  36
  37         cpus {
  38                 #address-cells = <1>;
  39                 #size-cells = <0>;
  40
  41                 cpu0: cpu@0 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a7";
  44                         reg = <0>;
  45                         clock-frequency = <1000000000>;
  46                         power-domains = <&sysc R8A7794_PD_CA7_CPU0>;
  47                         next-level-cache = <&L2_CA7>;
  48                 };
  49
  50                 cpu1: cpu@1 {
  51                         device_type = "cpu";
  52                         compatible = "arm,cortex-a7";
  53                         reg = <1>;
  54                         clock-frequency = <1000000000>;
  55                         power-domains = <&sysc R8A7794_PD_CA7_CPU1>;
  56                         next-level-cache = <&L2_CA7>;
  57                 };
  58
  59                 L2_CA7: cache-controller-0 {
  60                         compatible = "cache";
  61                         power-domains = <&sysc R8A7794_PD_CA7_SCU>;
  62                         cache-unified;
  63                         cache-level = <2>;
  64                 };
  65         };
  66
  67         gic: interrupt-controller@f1001000 {
  68                 compatible = "arm,gic-400";
  69                 #interrupt-cells = <3>;
  70                 #address-cells = <0>;
  71                 interrupt-controller;
  72                 reg = <0 0xf1001000 0 0x1000>,
  73                         <0 0xf1002000 0 0x1000>,
  74                         <0 0xf1004000 0 0x2000>,
  75                         <0 0xf1006000 0 0x2000>;
  76                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
  77         };
  78
  79         gpio0: gpio@e6050000 {
  80                 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
  81                 reg = <0 0xe6050000 0 0x50>;
  82                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
  83                 #gpio-cells = <2>;
  84                 gpio-controller;
  85                 gpio-ranges = <&pfc 0 0 32>;
  86                 #interrupt-cells = <2>;
  87                 interrupt-controller;
  88                 clocks = <&mstp9_clks R8A7794_CLK_GPIO0>;
  89                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
  90         };
  91
  92         gpio1: gpio@e6051000 {
  93                 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
  94                 reg = <0 0xe6051000 0 0x50>;
  95                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
  96                 #gpio-cells = <2>;
  97                 gpio-controller;
  98                 gpio-ranges = <&pfc 0 32 26>;
  99                 #interrupt-cells = <2>;
 100                 interrupt-controller;
 101                 clocks = <&mstp9_clks R8A7794_CLK_GPIO1>;
 102                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 103         };
 104
 105         gpio2: gpio@e6052000 {
 106                 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
 107                 reg = <0 0xe6052000 0 0x50>;
 108                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 109                 #gpio-cells = <2>;
 110                 gpio-controller;
 111                 gpio-ranges = <&pfc 0 64 32>;
 112                 #interrupt-cells = <2>;
 113                 interrupt-controller;
 114                 clocks = <&mstp9_clks R8A7794_CLK_GPIO2>;
 115                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 116         };
 117
 118         gpio3: gpio@e6053000 {
 119                 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
 120                 reg = <0 0xe6053000 0 0x50>;
 121                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 122                 #gpio-cells = <2>;
 123                 gpio-controller;
 124                 gpio-ranges = <&pfc 0 96 32>;
 125                 #interrupt-cells = <2>;
 126                 interrupt-controller;
 127                 clocks = <&mstp9_clks R8A7794_CLK_GPIO3>;
 128                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 129         };
 130
 131         gpio4: gpio@e6054000 {
 132                 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
 133                 reg = <0 0xe6054000 0 0x50>;
 134                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 135                 #gpio-cells = <2>;
 136                 gpio-controller;
 137                 gpio-ranges = <&pfc 0 128 32>;
 138                 #interrupt-cells = <2>;
 139                 interrupt-controller;
 140                 clocks = <&mstp9_clks R8A7794_CLK_GPIO4>;
 141                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 142         };
 143
 144         gpio5: gpio@e6055000 {
 145                 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
 146                 reg = <0 0xe6055000 0 0x50>;
 147                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 148                 #gpio-cells = <2>;
 149                 gpio-controller;
 150                 gpio-ranges = <&pfc 0 160 28>;
 151                 #interrupt-cells = <2>;
 152                 interrupt-controller;
 153                 clocks = <&mstp9_clks R8A7794_CLK_GPIO5>;
 154                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 155         };
 156
 157         gpio6: gpio@e6055400 {
 158                 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
 159                 reg = <0 0xe6055400 0 0x50>;
 160                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 161                 #gpio-cells = <2>;
 162                 gpio-controller;
 163                 gpio-ranges = <&pfc 0 192 26>;
 164                 #interrupt-cells = <2>;
 165                 interrupt-controller;
 166                 clocks = <&mstp9_clks R8A7794_CLK_GPIO6>;
 167                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 168         };
 169
 170         cmt0: timer@ffca0000 {
 171                 compatible = "renesas,cmt-48-gen2";
 172                 reg = <0 0xffca0000 0 0x1004>;
 173                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 174                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 175                 clocks = <&mstp1_clks R8A7794_CLK_CMT0>;
 176                 clock-names = "fck";
 177                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 178
 179                 renesas,channels-mask = <0x60>;
 180
 181                 status = "disabled";
 182         };
 183
 184         cmt1: timer@e6130000 {
 185                 compatible = "renesas,cmt-48-gen2";
 186                 reg = <0 0xe6130000 0 0x1004>;
 187                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 188                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 189                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
 190                              <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 191                              <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
 192                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
 193                              <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
 194                              <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 195                 clocks = <&mstp3_clks R8A7794_CLK_CMT1>;
 196                 clock-names = "fck";
 197                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 198
 199                 renesas,channels-mask = <0xff>;
 200
 201                 status = "disabled";
 202         };
 203
 204         timer {
 205                 compatible = "arm,armv7-timer";
 206                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 207                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 208                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 209                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
 210         };
 211
 212         irqc0: interrupt-controller@e61c0000 {
 213                 compatible = "renesas,irqc-r8a7794", "renesas,irqc";
 214                 #interrupt-cells = <2>;
 215                 interrupt-controller;
 216                 reg = <0 0xe61c0000 0 0x200>;
 217                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 218                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 219                              <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 220                              <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 221                              <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 222                              <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 223                              <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 224                              <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 225                              <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 226                              <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 227                 clocks = <&mstp4_clks R8A7794_CLK_IRQC>;
 228                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 229         };
 230
 231         pfc: pin-controller@e6060000 {
 232                 compatible = "renesas,pfc-r8a7794";
 233                 reg = <0 0xe6060000 0 0x11c>;
 234         };
 235
 236         dmac0: dma-controller@e6700000 {
 237                 compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac";
 238                 reg = <0 0xe6700000 0 0x20000>;
 239                 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
 240                               GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
 241                               GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
 242                               GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
 243                               GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
 244                               GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
 245                               GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
 246                               GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
 247                               GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
 248                               GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
 249                               GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
 250                               GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
 251                               GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
 252                               GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
 253                               GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
 254                               GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
 255                 interrupt-names = "error",
 256                                 "ch0", "ch1", "ch2", "ch3",
 257                                 "ch4", "ch5", "ch6", "ch7",
 258                                 "ch8", "ch9", "ch10", "ch11",
 259                                 "ch12", "ch13", "ch14";
 260                 clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC0>;
 261                 clock-names = "fck";
 262                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 263                 #dma-cells = <1>;
 264                 dma-channels = <15>;
 265         };
 266
 267         dmac1: dma-controller@e6720000 {
 268                 compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac";
 269                 reg = <0 0xe6720000 0 0x20000>;
 270                 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
 271                               GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
 272                               GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
 273                               GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
 274                               GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
 275                               GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
 276                               GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
 277                               GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
 278                               GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
 279                               GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
 280                               GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
 281                               GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
 282                               GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
 283                               GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
 284                               GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
 285                               GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
 286                 interrupt-names = "error",
 287                                 "ch0", "ch1", "ch2", "ch3",
 288                                 "ch4", "ch5", "ch6", "ch7",
 289                                 "ch8", "ch9", "ch10", "ch11",
 290                                 "ch12", "ch13", "ch14";
 291                 clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC1>;
 292                 clock-names = "fck";
 293                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 294                 #dma-cells = <1>;
 295                 dma-channels = <15>;
 296         };
 297
 298         audma0: dma-controller@ec700000 {
 299                 compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac";
 300                 reg = <0 0xec700000 0 0x10000>;
 301                 interrupts =    <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
 302                                  GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
 303                                  GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
 304                                  GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
 305                                  GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
 306                                  GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
 307                                  GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
 308                                  GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
 309                                  GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
 310                                  GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
 311                                  GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
 312                                  GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
 313                                  GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
 314                                  GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
 315                 interrupt-names = "error",
 316                                   "ch0", "ch1", "ch2", "ch3", "ch4", "ch5",
 317                                   "ch6", "ch7", "ch8", "ch9", "ch10", "ch11",
 318                                   "ch12";
 319                 clocks = <&mstp5_clks R8A7794_CLK_AUDIO_DMAC0>;
 320                 clock-names = "fck";
 321                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 322                 #dma-cells = <1>;
 323                 dma-channels = <13>;
 324         };
 325
 326         scifa0: serial@e6c40000 {
 327                 compatible = "renesas,scifa-r8a7794",
 328                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 329                 reg = <0 0xe6c40000 0 64>;
 330                 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 331                 clocks = <&mstp2_clks R8A7794_CLK_SCIFA0>;
 332                 clock-names = "fck";
 333                 dmas = <&dmac0 0x21>, <&dmac0 0x22>,
 334                        <&dmac1 0x21>, <&dmac1 0x22>;
 335                 dma-names = "tx", "rx", "tx", "rx";
 336                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 337                 status = "disabled";
 338         };
 339
 340         scifa1: serial@e6c50000 {
 341                 compatible = "renesas,scifa-r8a7794",
 342                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 343                 reg = <0 0xe6c50000 0 64>;
 344                 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
 345                 clocks = <&mstp2_clks R8A7794_CLK_SCIFA1>;
 346                 clock-names = "fck";
 347                 dmas = <&dmac0 0x25>, <&dmac0 0x26>,
 348                        <&dmac1 0x25>, <&dmac1 0x26>;
 349                 dma-names = "tx", "rx", "tx", "rx";
 350                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 351                 status = "disabled";
 352         };
 353
 354         scifa2: serial@e6c60000 {
 355                 compatible = "renesas,scifa-r8a7794",
 356                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 357                 reg = <0 0xe6c60000 0 64>;
 358                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
 359                 clocks = <&mstp2_clks R8A7794_CLK_SCIFA2>;
 360                 clock-names = "fck";
 361                 dmas = <&dmac0 0x27>, <&dmac0 0x28>,
 362                        <&dmac1 0x27>, <&dmac1 0x28>;
 363                 dma-names = "tx", "rx", "tx", "rx";
 364                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 365                 status = "disabled";
 366         };
 367
 368         scifa3: serial@e6c70000 {
 369                 compatible = "renesas,scifa-r8a7794",
 370                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 371                 reg = <0 0xe6c70000 0 64>;
 372                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 373                 clocks = <&mstp11_clks R8A7794_CLK_SCIFA3>;
 374                 clock-names = "fck";
 375                 dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
 376                        <&dmac1 0x1b>, <&dmac1 0x1c>;
 377                 dma-names = "tx", "rx", "tx", "rx";
 378                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 379                 status = "disabled";
 380         };
 381
 382         scifa4: serial@e6c78000 {
 383                 compatible = "renesas,scifa-r8a7794",
 384                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 385                 reg = <0 0xe6c78000 0 64>;
 386                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 387                 clocks = <&mstp11_clks R8A7794_CLK_SCIFA4>;
 388                 clock-names = "fck";
 389                 dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
 390                        <&dmac1 0x1f>, <&dmac1 0x20>;
 391                 dma-names = "tx", "rx", "tx", "rx";
 392                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 393                 status = "disabled";
 394         };
 395
 396         scifa5: serial@e6c80000 {
 397                 compatible = "renesas,scifa-r8a7794",
 398                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 399                 reg = <0 0xe6c80000 0 64>;
 400                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 401                 clocks = <&mstp11_clks R8A7794_CLK_SCIFA5>;
 402                 clock-names = "fck";
 403                 dmas = <&dmac0 0x23>, <&dmac0 0x24>,
 404                        <&dmac1 0x23>, <&dmac1 0x24>;
 405                 dma-names = "tx", "rx", "tx", "rx";
 406                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 407                 status = "disabled";
 408         };
 409
 410         scifb0: serial@e6c20000 {
 411                 compatible = "renesas,scifb-r8a7794",
 412                              "renesas,rcar-gen2-scifb", "renesas,scifb";
 413                 reg = <0 0xe6c20000 0 64>;
 414                 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
 415                 clocks = <&mstp2_clks R8A7794_CLK_SCIFB0>;
 416                 clock-names = "fck";
 417                 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
 418                        <&dmac1 0x3d>, <&dmac1 0x3e>;
 419                 dma-names = "tx", "rx", "tx", "rx";
 420                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 421                 status = "disabled";
 422         };
 423
 424         scifb1: serial@e6c30000 {
 425                 compatible = "renesas,scifb-r8a7794",
 426                              "renesas,rcar-gen2-scifb", "renesas,scifb";
 427                 reg = <0 0xe6c30000 0 64>;
 428                 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 429                 clocks = <&mstp2_clks R8A7794_CLK_SCIFB1>;
 430                 clock-names = "fck";
 431                 dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
 432                        <&dmac1 0x19>, <&dmac1 0x1a>;
 433                 dma-names = "tx", "rx", "tx", "rx";
 434                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 435                 status = "disabled";
 436         };
 437
 438         scifb2: serial@e6ce0000 {
 439                 compatible = "renesas,scifb-r8a7794",
 440                              "renesas,rcar-gen2-scifb", "renesas,scifb";
 441                 reg = <0 0xe6ce0000 0 64>;
 442                 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
 443                 clocks = <&mstp2_clks R8A7794_CLK_SCIFB2>;
 444                 clock-names = "fck";
 445                 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
 446                        <&dmac1 0x1d>, <&dmac1 0x1e>;
 447                 dma-names = "tx", "rx", "tx", "rx";
 448                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 449                 status = "disabled";
 450         };
 451
 452         scif0: serial@e6e60000 {
 453                 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
 454                              "renesas,scif";
 455                 reg = <0 0xe6e60000 0 64>;
 456                 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
 457                 clocks = <&mstp7_clks R8A7794_CLK_SCIF0>, <&zs_clk>,
 458                          <&scif_clk>;
 459                 clock-names = "fck", "brg_int", "scif_clk";
 460                 dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
 461                        <&dmac1 0x29>, <&dmac1 0x2a>;
 462                 dma-names = "tx", "rx", "tx", "rx";
 463                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 464                 status = "disabled";
 465         };
 466
 467         scif1: serial@e6e68000 {
 468                 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
 469                              "renesas,scif";
 470                 reg = <0 0xe6e68000 0 64>;
 471                 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 472                 clocks = <&mstp7_clks R8A7794_CLK_SCIF1>, <&zs_clk>,
 473                          <&scif_clk>;
 474                 clock-names = "fck", "brg_int", "scif_clk";
 475                 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
 476                        <&dmac1 0x2d>, <&dmac1 0x2e>;
 477                 dma-names = "tx", "rx", "tx", "rx";
 478                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 479                 status = "disabled";
 480         };
 481
 482         scif2: serial@e6e58000 {
 483                 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
 484                              "renesas,scif";
 485                 reg = <0 0xe6e58000 0 64>;
 486                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 487                 clocks = <&mstp7_clks R8A7794_CLK_SCIF2>, <&zs_clk>,
 488                          <&scif_clk>;
 489                 clock-names = "fck", "brg_int", "scif_clk";
 490                 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
 491                        <&dmac1 0x2b>, <&dmac1 0x2c>;
 492                 dma-names = "tx", "rx", "tx", "rx";
 493                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 494                 status = "disabled";
 495         };
 496
 497         scif3: serial@e6ea8000 {
 498                 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
 499                              "renesas,scif";
 500                 reg = <0 0xe6ea8000 0 64>;
 501                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 502                 clocks = <&mstp7_clks R8A7794_CLK_SCIF3>, <&zs_clk>,
 503                          <&scif_clk>;
 504                 clock-names = "fck", "brg_int", "scif_clk";
 505                 dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
 506                        <&dmac1 0x2f>, <&dmac1 0x30>;
 507                 dma-names = "tx", "rx", "tx", "rx";
 508                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 509                 status = "disabled";
 510         };
 511
 512         scif4: serial@e6ee0000 {
 513                 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
 514                              "renesas,scif";
 515                 reg = <0 0xe6ee0000 0 64>;
 516                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 517                 clocks = <&mstp7_clks R8A7794_CLK_SCIF4>, <&zs_clk>,
 518                          <&scif_clk>;
 519                 clock-names = "fck", "brg_int", "scif_clk";
 520                 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
 521                        <&dmac1 0xfb>, <&dmac1 0xfc>;
 522                 dma-names = "tx", "rx", "tx", "rx";
 523                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 524                 status = "disabled";
 525         };
 526
 527         scif5: serial@e6ee8000 {
 528                 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
 529                              "renesas,scif";
 530                 reg = <0 0xe6ee8000 0 64>;
 531                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 532                 clocks = <&mstp7_clks R8A7794_CLK_SCIF5>, <&zs_clk>,
 533                          <&scif_clk>;
 534                 clock-names = "fck", "brg_int", "scif_clk";
 535                 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
 536                        <&dmac1 0xfd>, <&dmac1 0xfe>;
 537                 dma-names = "tx", "rx", "tx", "rx";
 538                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 539                 status = "disabled";
 540         };
 541
 542         hscif0: serial@e62c0000 {
 543                 compatible = "renesas,hscif-r8a7794",
 544                              "renesas,rcar-gen2-hscif", "renesas,hscif";
 545                 reg = <0 0xe62c0000 0 96>;
 546                 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 547                 clocks = <&mstp7_clks R8A7794_CLK_HSCIF0>, <&zs_clk>,
 548                          <&scif_clk>;
 549                 clock-names = "fck", "brg_int", "scif_clk";
 550                 dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
 551                        <&dmac1 0x39>, <&dmac1 0x3a>;
 552                 dma-names = "tx", "rx", "tx", "rx";
 553                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 554                 status = "disabled";
 555         };
 556
 557         hscif1: serial@e62c8000 {
 558                 compatible = "renesas,hscif-r8a7794",
 559                              "renesas,rcar-gen2-hscif", "renesas,hscif";
 560                 reg = <0 0xe62c8000 0 96>;
 561                 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
 562                 clocks = <&mstp7_clks R8A7794_CLK_HSCIF1>, <&zs_clk>,
 563                          <&scif_clk>;
 564                 clock-names = "fck", "brg_int", "scif_clk";
 565                 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
 566                        <&dmac1 0x4d>, <&dmac1 0x4e>;
 567                 dma-names = "tx", "rx", "tx", "rx";
 568                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 569                 status = "disabled";
 570         };
 571
 572         hscif2: serial@e62d0000 {
 573                 compatible = "renesas,hscif-r8a7794",
 574                              "renesas,rcar-gen2-hscif", "renesas,hscif";
 575                 reg = <0 0xe62d0000 0 96>;
 576                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 577                 clocks = <&mstp7_clks R8A7794_CLK_HSCIF2>, <&zs_clk>,
 578                          <&scif_clk>;
 579                 clock-names = "fck", "brg_int", "scif_clk";
 580                 dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
 581                        <&dmac1 0x3b>, <&dmac1 0x3c>;
 582                 dma-names = "tx", "rx", "tx", "rx";
 583                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 584                 status = "disabled";
 585         };
 586
 587         ether: ethernet@ee700000 {
 588                 compatible = "renesas,ether-r8a7794";
 589                 reg = <0 0xee700000 0 0x400>;
 590                 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
 591                 clocks = <&mstp8_clks R8A7794_CLK_ETHER>;
 592                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 593                 phy-mode = "rmii";
 594                 #address-cells = <1>;
 595                 #size-cells = <0>;
 596                 status = "disabled";
 597         };
 598
 599         avb: ethernet@e6800000 {
 600                 compatible = "renesas,etheravb-r8a7794",
 601                              "renesas,etheravb-rcar-gen2";
 602                 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
 603                 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
 604                 clocks = <&mstp8_clks R8A7794_CLK_ETHERAVB>;
 605                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 606                 #address-cells = <1>;
 607                 #size-cells = <0>;
 608                 status = "disabled";
 609         };
 610
 611         /* The memory map in the User's Manual maps the cores to bus numbers */
 612         i2c0: i2c@e6508000 {
 613                 compatible = "renesas,i2c-r8a7794";
 614                 reg = <0 0xe6508000 0 0x40>;
 615                 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
 616                 clocks = <&mstp9_clks R8A7794_CLK_I2C0>;
 617                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 618                 #address-cells = <1>;
 619                 #size-cells = <0>;
 620                 i2c-scl-internal-delay-ns = <6>;
 621                 status = "disabled";
 622         };
 623
 624         i2c1: i2c@e6518000 {
 625                 compatible = "renesas,i2c-r8a7794";
 626                 reg = <0 0xe6518000 0 0x40>;
 627                 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
 628                 clocks = <&mstp9_clks R8A7794_CLK_I2C1>;
 629                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 630                 #address-cells = <1>;
 631                 #size-cells = <0>;
 632                 i2c-scl-internal-delay-ns = <6>;
 633                 status = "disabled";
 634         };
 635
 636         i2c2: i2c@e6530000 {
 637                 compatible = "renesas,i2c-r8a7794";
 638                 reg = <0 0xe6530000 0 0x40>;
 639                 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
 640                 clocks = <&mstp9_clks R8A7794_CLK_I2C2>;
 641                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 642                 #address-cells = <1>;
 643                 #size-cells = <0>;
 644                 i2c-scl-internal-delay-ns = <6>;
 645                 status = "disabled";
 646         };
 647
 648         i2c3: i2c@e6540000 {
 649                 compatible = "renesas,i2c-r8a7794";
 650                 reg = <0 0xe6540000 0 0x40>;
 651                 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
 652                 clocks = <&mstp9_clks R8A7794_CLK_I2C3>;
 653                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 654                 #address-cells = <1>;
 655                 #size-cells = <0>;
 656                 i2c-scl-internal-delay-ns = <6>;
 657                 status = "disabled";
 658         };
 659
 660         i2c4: i2c@e6520000 {
 661                 compatible = "renesas,i2c-r8a7794";
 662                 reg = <0 0xe6520000 0 0x40>;
 663                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 664                 clocks = <&mstp9_clks R8A7794_CLK_I2C4>;
 665                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 666                 #address-cells = <1>;
 667                 #size-cells = <0>;
 668                 i2c-scl-internal-delay-ns = <6>;
 669                 status = "disabled";
 670         };
 671
 672         i2c5: i2c@e6528000 {
 673                 compatible = "renesas,i2c-r8a7794";
 674                 reg = <0 0xe6528000 0 0x40>;
 675                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 676                 clocks = <&mstp9_clks R8A7794_CLK_I2C5>;
 677                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 678                 #address-cells = <1>;
 679                 #size-cells = <0>;
 680                 i2c-scl-internal-delay-ns = <6>;
 681                 status = "disabled";
 682         };
 683
 684         i2c6: i2c@e6500000 {
 685                 compatible = "renesas,iic-r8a7794", "renesas,rmobile-iic";
 686                 reg = <0 0xe6500000 0 0x425>;
 687                 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
 688                 clocks = <&mstp3_clks R8A7794_CLK_IIC0>;
 689                 dmas = <&dmac0 0x61>, <&dmac0 0x62>,
 690                        <&dmac1 0x61>, <&dmac1 0x62>;
 691                 dma-names = "tx", "rx", "tx", "rx";
 692                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 693                 #address-cells = <1>;
 694                 #size-cells = <0>;
 695                 status = "disabled";
 696         };
 697
 698         i2c7: i2c@e6510000 {
 699                 compatible = "renesas,iic-r8a7794", "renesas,rmobile-iic";
 700                 reg = <0 0xe6510000 0 0x425>;
 701                 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
 702                 clocks = <&mstp3_clks R8A7794_CLK_IIC1>;
 703                 dmas = <&dmac0 0x65>, <&dmac0 0x66>,
 704                        <&dmac1 0x65>, <&dmac1 0x66>;
 705                 dma-names = "tx", "rx", "tx", "rx";
 706                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 707                 #address-cells = <1>;
 708                 #size-cells = <0>;
 709                 status = "disabled";
 710         };
 711
 712         mmcif0: mmc@ee200000 {
 713                 compatible = "renesas,mmcif-r8a7794", "renesas,sh-mmcif";
 714                 reg = <0 0xee200000 0 0x80>;
 715                 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
 716                 clocks = <&mstp3_clks R8A7794_CLK_MMCIF0>;
 717                 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
 718                        <&dmac1 0xd1>, <&dmac1 0xd2>;
 719                 dma-names = "tx", "rx", "tx", "rx";
 720                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 721                 reg-io-width = <4>;
 722                 status = "disabled";
 723         };
 724
 725         sdhi0: sd@ee100000 {
 726                 compatible = "renesas,sdhi-r8a7794";
 727                 reg = <0 0xee100000 0 0x328>;
 728                 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
 729                 clocks = <&mstp3_clks R8A7794_CLK_SDHI0>;
 730                 dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
 731                        <&dmac1 0xcd>, <&dmac1 0xce>;
 732                 dma-names = "tx", "rx", "tx", "rx";
 733                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 734                 status = "disabled";
 735         };
 736
 737         sdhi1: sd@ee140000 {
 738                 compatible = "renesas,sdhi-r8a7794";
 739                 reg = <0 0xee140000 0 0x100>;
 740                 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
 741                 clocks = <&mstp3_clks R8A7794_CLK_SDHI1>;
 742                 dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
 743                        <&dmac1 0xc1>, <&dmac1 0xc2>;
 744                 dma-names = "tx", "rx", "tx", "rx";
 745                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 746                 status = "disabled";
 747         };
 748
 749         sdhi2: sd@ee160000 {
 750                 compatible = "renesas,sdhi-r8a7794";
 751                 reg = <0 0xee160000 0 0x100>;
 752                 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
 753                 clocks = <&mstp3_clks R8A7794_CLK_SDHI2>;
 754                 dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
 755                        <&dmac1 0xd3>, <&dmac1 0xd4>;
 756                 dma-names = "tx", "rx", "tx", "rx";
 757                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 758                 status = "disabled";
 759         };
 760
 761         qspi: spi@e6b10000 {
 762                 compatible = "renesas,qspi-r8a7794", "renesas,qspi";
 763                 reg = <0 0xe6b10000 0 0x2c>;
 764                 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
 765                 clocks = <&mstp9_clks R8A7794_CLK_QSPI_MOD>;
 766                 dmas = <&dmac0 0x17>, <&dmac0 0x18>,
 767                        <&dmac1 0x17>, <&dmac1 0x18>;
 768                 dma-names = "tx", "rx", "tx", "rx";
 769                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 770                 num-cs = <1>;
 771                 #address-cells = <1>;
 772                 #size-cells = <0>;
 773                 status = "disabled";
 774         };
 775
 776         vin0: video@e6ef0000 {
 777                 compatible = "renesas,vin-r8a7794";
 778                 reg = <0 0xe6ef0000 0 0x1000>;
 779                 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
 780                 clocks = <&mstp8_clks R8A7794_CLK_VIN0>;
 781                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 782                 status = "disabled";
 783         };
 784
 785         vin1: video@e6ef1000 {
 786                 compatible = "renesas,vin-r8a7794";
 787                 reg = <0 0xe6ef1000 0 0x1000>;
 788                 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
 789                 clocks = <&mstp8_clks R8A7794_CLK_VIN1>;
 790                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 791                 status = "disabled";
 792         };
 793
 794         pci0: pci@ee090000 {
 795                 compatible = "renesas,pci-r8a7794", "renesas,pci-rcar-gen2";
 796                 device_type = "pci";
 797                 reg = <0 0xee090000 0 0xc00>,
 798                       <0 0xee080000 0 0x1100>;
 799                 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 800                 clocks = <&mstp7_clks R8A7794_CLK_EHCI>;
 801                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 802                 status = "disabled";
 803
 804                 bus-range = <0 0>;
 805                 #address-cells = <3>;
 806                 #size-cells = <2>;
 807                 #interrupt-cells = <1>;
 808                 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
 809                 interrupt-map-mask = <0xff00 0 0 0x7>;
 810                 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
 811                                  0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
 812                                  0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 813
 814                 usb@0,1 {
 815                         reg = <0x800 0 0 0 0>;
 816                         device_type = "pci";
 817                         phys = <&usb0 0>;
 818                         phy-names = "usb";
 819                 };
 820
 821                 usb@0,2 {
 822                         reg = <0x1000 0 0 0 0>;
 823                         device_type = "pci";
 824                         phys = <&usb0 0>;
 825                         phy-names = "usb";
 826                 };
 827         };
 828
 829         pci1: pci@ee0d0000 {
 830                 compatible = "renesas,pci-r8a7794", "renesas,pci-rcar-gen2";
 831                 device_type = "pci";
 832                 reg = <0 0xee0d0000 0 0xc00>,
 833                       <0 0xee0c0000 0 0x1100>;
 834                 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 835                 clocks = <&mstp7_clks R8A7794_CLK_EHCI>;
 836                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 837                 status = "disabled";
 838
 839                 bus-range = <1 1>;
 840                 #address-cells = <3>;
 841                 #size-cells = <2>;
 842                 #interrupt-cells = <1>;
 843                 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
 844                 interrupt-map-mask = <0xff00 0 0 0x7>;
 845                 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
 846                                  0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
 847                                  0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 848
 849                 usb@0,1 {
 850                         reg = <0x800 0 0 0 0>;
 851                         device_type = "pci";
 852                         phys = <&usb2 0>;
 853                         phy-names = "usb";
 854                 };
 855
 856                 usb@0,2 {
 857                         reg = <0x1000 0 0 0 0>;
 858                         device_type = "pci";
 859                         phys = <&usb2 0>;
 860                         phy-names = "usb";
 861                 };
 862         };
 863
 864         hsusb: usb@e6590000 {
 865                 compatible = "renesas,usbhs-r8a7794", "renesas,rcar-gen2-usbhs";
 866                 reg = <0 0xe6590000 0 0x100>;
 867                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 868                 clocks = <&mstp7_clks R8A7794_CLK_HSUSB>;
 869                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 870                 renesas,buswait = <4>;
 871                 phys = <&usb0 1>;
 872                 phy-names = "usb";
 873                 status = "disabled";
 874         };
 875
 876         usbphy: usb-phy@e6590100 {
 877                 compatible = "renesas,usb-phy-r8a7794";
 878                 reg = <0 0xe6590100 0 0x100>;
 879                 #address-cells = <1>;
 880                 #size-cells = <0>;
 881                 clocks = <&mstp7_clks R8A7794_CLK_HSUSB>;
 882                 clock-names = "usbhs";
 883                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 884                 status = "disabled";
 885
 886                 usb0: usb-channel@0 {
 887                         reg = <0>;
 888                         #phy-cells = <1>;
 889                 };
 890                 usb2: usb-channel@2 {
 891                         reg = <2>;
 892                         #phy-cells = <1>;
 893                 };
 894         };
 895
 896         vsp1@fe928000 {
 897                 compatible = "renesas,vsp1";
 898                 reg = <0 0xfe928000 0 0x8000>;
 899                 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
 900                 clocks = <&mstp1_clks R8A7794_CLK_VSP1_S>;
 901                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 902         };
 903
 904         vsp1@fe930000 {
 905                 compatible = "renesas,vsp1";
 906                 reg = <0 0xfe930000 0 0x8000>;
 907                 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
 908                 clocks = <&mstp1_clks R8A7794_CLK_VSP1_DU0>;
 909                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 910         };
 911
 912         du: display@feb00000 {
 913                 compatible = "renesas,du-r8a7794";
 914                 reg = <0 0xfeb00000 0 0x40000>;
 915                 reg-names = "du";
 916                 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
 917                              <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
 918                 clocks = <&mstp7_clks R8A7794_CLK_DU0>,
 919                          <&mstp7_clks R8A7794_CLK_DU1>;
 920                 clock-names = "du.0", "du.1";
 921                 status = "disabled";
 922
 923                 ports {
 924                         #address-cells = <1>;
 925                         #size-cells = <0>;
 926
 927                         port@0 {
 928                                 reg = <0>;
 929                                 du_out_rgb0: endpoint {
 930                                 };
 931                         };
 932                         port@1 {
 933                                 reg = <1>;
 934                                 du_out_rgb1: endpoint {
 935                                 };
 936                         };
 937                 };
 938         };
 939
 940         can0: can@e6e80000 {
 941                 compatible = "renesas,can-r8a7794", "renesas,rcar-gen2-can";
 942                 reg = <0 0xe6e80000 0 0x1000>;
 943                 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
 944                 clocks = <&mstp9_clks R8A7794_CLK_RCAN0>,
 945                          <&cpg_clocks R8A7794_CLK_RCAN>, <&can_clk>;
 946                 clock-names = "clkp1", "clkp2", "can_clk";
 947                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 948                 status = "disabled";
 949         };
 950
 951         can1: can@e6e88000 {
 952                 compatible = "renesas,can-r8a7794", "renesas,rcar-gen2-can";
 953                 reg = <0 0xe6e88000 0 0x1000>;
 954                 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
 955                 clocks = <&mstp9_clks R8A7794_CLK_RCAN1>,
 956                          <&cpg_clocks R8A7794_CLK_RCAN>, <&can_clk>;
 957                 clock-names = "clkp1", "clkp2", "can_clk";
 958                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 959                 status = "disabled";
 960         };
 961
 962         clocks {
 963                 #address-cells = <2>;
 964                 #size-cells = <2>;
 965                 ranges;
 966
 967                 /* External root clock */
 968                 extal_clk: extal {
 969                         compatible = "fixed-clock";
 970                         #clock-cells = <0>;
 971                         /* This value must be overriden by the board. */
 972                         clock-frequency = <0>;
 973                 };
 974
 975                 /* External USB clock - can be overridden by the board */
 976                 usb_extal_clk: usb_extal {
 977                         compatible = "fixed-clock";
 978                         #clock-cells = <0>;
 979                         clock-frequency = <48000000>;
 980                 };
 981
 982                 /* External CAN clock */
 983                 can_clk: can {
 984                         compatible = "fixed-clock";
 985                         #clock-cells = <0>;
 986                         /* This value must be overridden by the board. */
 987                         clock-frequency = <0>;
 988                 };
 989
 990                 /* External SCIF clock */
 991                 scif_clk: scif {
 992                         compatible = "fixed-clock";
 993                         #clock-cells = <0>;
 994                         /* This value must be overridden by the board. */
 995                         clock-frequency = <0>;
 996                 };
 997
 998                 /*
 999                  * The external audio clocks are configured  as 0 Hz fixed
1000                  * frequency clocks by default.  Boards that provide audio
1001                  * clocks should override them.
1002                  */
1003                 audio_clka: audio_clka {
1004                         compatible = "fixed-clock";
1005                         #clock-cells = <0>;
1006                         clock-frequency = <0>;
1007                 };
1008                 audio_clkb: audio_clkb {
1009                         compatible = "fixed-clock";
1010                         #clock-cells = <0>;
1011                         clock-frequency = <0>;
1012                 };
1013                 audio_clkc: audio_clkc {
1014                         compatible = "fixed-clock";
1015                         #clock-cells = <0>;
1016                         clock-frequency = <0>;
1017                 };
1018
1019                 /* Special CPG clocks */
1020                 cpg_clocks: cpg_clocks@e6150000 {
1021                         compatible = "renesas,r8a7794-cpg-clocks",
1022                                      "renesas,rcar-gen2-cpg-clocks";
1023                         reg = <0 0xe6150000 0 0x1000>;
1024                         clocks = <&extal_clk &usb_extal_clk>;
1025                         #clock-cells = <1>;
1026                         clock-output-names = "main", "pll0", "pll1", "pll3",
1027                                              "lb", "qspi", "sdh", "sd0", "rcan";
1028                         #power-domain-cells = <0>;
1029                 };
1030                 /* Variable factor clocks */
1031                 sd2_clk: sd2@e6150078 {
1032                         compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
1033                         reg = <0 0xe6150078 0 4>;
1034                         clocks = <&pll1_div2_clk>;
1035                         #clock-cells = <0>;
1036                 };
1037                 sd3_clk: sd3@e615026c {
1038                         compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
1039                         reg = <0 0xe615026c 0 4>;
1040                         clocks = <&pll1_div2_clk>;
1041                         #clock-cells = <0>;
1042                 };
1043                 mmc0_clk: mmc0@e6150240 {
1044                         compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
1045                         reg = <0 0xe6150240 0 4>;
1046                         clocks = <&pll1_div2_clk>;
1047                         #clock-cells = <0>;
1048                 };
1049
1050                 /* Fixed factor clocks */
1051                 pll1_div2_clk: pll1_div2 {
1052                         compatible = "fixed-factor-clock";
1053                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1054                         #clock-cells = <0>;
1055                         clock-div = <2>;
1056                         clock-mult = <1>;
1057                 };
1058                 zg_clk: zg {
1059                         compatible = "fixed-factor-clock";
1060                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1061                         #clock-cells = <0>;
1062                         clock-div = <6>;
1063                         clock-mult = <1>;
1064                 };
1065                 zx_clk: zx {
1066                         compatible = "fixed-factor-clock";
1067                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1068                         #clock-cells = <0>;
1069                         clock-div = <3>;
1070                         clock-mult = <1>;
1071                 };
1072                 zs_clk: zs {
1073                         compatible = "fixed-factor-clock";
1074                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1075                         #clock-cells = <0>;
1076                         clock-div = <6>;
1077                         clock-mult = <1>;
1078                 };
1079                 hp_clk: hp {
1080                         compatible = "fixed-factor-clock";
1081                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1082                         #clock-cells = <0>;
1083                         clock-div = <12>;
1084                         clock-mult = <1>;
1085                 };
1086                 i_clk: i {
1087                         compatible = "fixed-factor-clock";
1088                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1089                         #clock-cells = <0>;
1090                         clock-div = <2>;
1091                         clock-mult = <1>;
1092                 };
1093                 b_clk: b {
1094                         compatible = "fixed-factor-clock";
1095                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1096                         #clock-cells = <0>;
1097                         clock-div = <12>;
1098                         clock-mult = <1>;
1099                 };
1100                 p_clk: p {
1101                         compatible = "fixed-factor-clock";
1102                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1103                         #clock-cells = <0>;
1104                         clock-div = <24>;
1105                         clock-mult = <1>;
1106                 };
1107                 cl_clk: cl {
1108                         compatible = "fixed-factor-clock";
1109                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1110                         #clock-cells = <0>;
1111                         clock-div = <48>;
1112                         clock-mult = <1>;
1113                 };
1114                 m2_clk: m2 {
1115                         compatible = "fixed-factor-clock";
1116                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1117                         #clock-cells = <0>;
1118                         clock-div = <8>;
1119                         clock-mult = <1>;
1120                 };
1121                 rclk_clk: rclk {
1122                         compatible = "fixed-factor-clock";
1123                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1124                         #clock-cells = <0>;
1125                         clock-div = <(48 * 1024)>;
1126                         clock-mult = <1>;
1127                 };
1128                 oscclk_clk: oscclk {
1129                         compatible = "fixed-factor-clock";
1130                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1131                         #clock-cells = <0>;
1132                         clock-div = <(12 * 1024)>;
1133                         clock-mult = <1>;
1134                 };
1135                 zb3_clk: zb3 {
1136                         compatible = "fixed-factor-clock";
1137                         clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
1138                         #clock-cells = <0>;
1139                         clock-div = <4>;
1140                         clock-mult = <1>;
1141                 };
1142                 zb3d2_clk: zb3d2 {
1143                         compatible = "fixed-factor-clock";
1144                         clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
1145                         #clock-cells = <0>;
1146                         clock-div = <8>;
1147                         clock-mult = <1>;
1148                 };
1149                 ddr_clk: ddr {
1150                         compatible = "fixed-factor-clock";
1151                         clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
1152                         #clock-cells = <0>;
1153                         clock-div = <8>;
1154                         clock-mult = <1>;
1155                 };
1156                 mp_clk: mp {
1157                         compatible = "fixed-factor-clock";
1158                         clocks = <&pll1_div2_clk>;
1159                         #clock-cells = <0>;
1160                         clock-div = <15>;
1161                         clock-mult = <1>;
1162                 };
1163                 cp_clk: cp {
1164                         compatible = "fixed-factor-clock";
1165                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1166                         #clock-cells = <0>;
1167                         clock-div = <48>;
1168                         clock-mult = <1>;
1169                 };
1170
1171                 acp_clk: acp {
1172                         compatible = "fixed-factor-clock";
1173                         clocks = <&extal_clk>;
1174                         #clock-cells = <0>;
1175                         clock-div = <2>;
1176                         clock-mult = <1>;
1177                 };
1178
1179                 /* Gate clocks */
1180                 mstp0_clks: mstp0_clks@e6150130 {
1181                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1182                         reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
1183                         clocks = <&mp_clk>;
1184                         #clock-cells = <1>;
1185                         clock-indices = <R8A7794_CLK_MSIOF0>;
1186                         clock-output-names = "msiof0";
1187                 };
1188                 mstp1_clks: mstp1_clks@e6150134 {
1189                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1190                         reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
1191                         clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>,
1192                                  <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>,
1193                                  <&zs_clk>, <&zs_clk>;
1194                         #clock-cells = <1>;
1195                         clock-indices = <
1196                                 R8A7794_CLK_VCP0 R8A7794_CLK_VPC0 R8A7794_CLK_TMU1
1197                                 R8A7794_CLK_3DG R8A7794_CLK_2DDMAC R8A7794_CLK_FDP1_0
1198                                 R8A7794_CLK_TMU3 R8A7794_CLK_TMU2 R8A7794_CLK_CMT0
1199                                 R8A7794_CLK_TMU0 R8A7794_CLK_VSP1_DU0 R8A7794_CLK_VSP1_S
1200                         >;
1201                         clock-output-names =
1202                                 "vcp0", "vpc0", "tmu1", "3dg", "2ddmac", "fdp1-0",
1203                                 "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du0", "vsps";
1204                 };
1205                 mstp2_clks: mstp2_clks@e6150138 {
1206                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1207                         reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
1208                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
1209                                  <&mp_clk>, <&mp_clk>, <&mp_clk>,
1210                                  <&zs_clk>, <&zs_clk>;
1211                         #clock-cells = <1>;
1212                         clock-indices = <
1213                                 R8A7794_CLK_SCIFA2 R8A7794_CLK_SCIFA1 R8A7794_CLK_SCIFA0
1214                                 R8A7794_CLK_MSIOF2 R8A7794_CLK_SCIFB0 R8A7794_CLK_SCIFB1
1215                                 R8A7794_CLK_MSIOF1 R8A7794_CLK_SCIFB2
1216                                 R8A7794_CLK_SYS_DMAC1 R8A7794_CLK_SYS_DMAC0
1217                         >;
1218                         clock-output-names =
1219                                 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
1220                                 "scifb1", "msiof1", "scifb2",
1221                                 "sys-dmac1", "sys-dmac0";
1222                 };
1223                 mstp3_clks: mstp3_clks@e615013c {
1224                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1225                         reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
1226                         clocks = <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7794_CLK_SD0>,
1227                                  <&mmc0_clk>, <&hp_clk>, <&hp_clk>, <&rclk_clk>,
1228                                  <&hp_clk>, <&hp_clk>;
1229                         #clock-cells = <1>;
1230                         clock-indices = <
1231                                 R8A7794_CLK_SDHI2 R8A7794_CLK_SDHI1 R8A7794_CLK_SDHI0
1232                                 R8A7794_CLK_MMCIF0 R8A7794_CLK_IIC0
1233                                 R8A7794_CLK_IIC1 R8A7794_CLK_CMT1
1234                                 R8A7794_CLK_USBDMAC0 R8A7794_CLK_USBDMAC1
1235                         >;
1236                         clock-output-names =
1237                                 "sdhi2", "sdhi1", "sdhi0",
1238                                 "mmcif0", "i2c6", "i2c7",
1239                                 "cmt1", "usbdmac0", "usbdmac1";
1240                 };
1241                 mstp4_clks: mstp4_clks@e6150140 {
1242                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1243                         reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
1244                         clocks = <&cp_clk>;
1245                         #clock-cells = <1>;
1246                         clock-indices = <R8A7794_CLK_IRQC>;
1247                         clock-output-names = "irqc";
1248                 };
1249                 mstp5_clks: mstp5_clks@e6150144 {
1250                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1251                         reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
1252                         clocks = <&hp_clk>, <&p_clk>;
1253                         #clock-cells = <1>;
1254                         clock-indices = <R8A7794_CLK_AUDIO_DMAC0
1255                                          R8A7794_CLK_PWM>;
1256                         clock-output-names = "audmac0", "pwm";
1257                 };
1258                 mstp7_clks: mstp7_clks@e615014c {
1259                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1260                         reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
1261                         clocks = <&mp_clk>, <&hp_clk>,
1262                                  <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
1263                                  <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1264                                  <&zx_clk>, <&zx_clk>;
1265                         #clock-cells = <1>;
1266                         clock-indices = <
1267                                 R8A7794_CLK_EHCI R8A7794_CLK_HSUSB
1268                                 R8A7794_CLK_HSCIF2 R8A7794_CLK_SCIF5
1269                                 R8A7794_CLK_SCIF4 R8A7794_CLK_HSCIF1 R8A7794_CLK_HSCIF0
1270                                 R8A7794_CLK_SCIF3 R8A7794_CLK_SCIF2 R8A7794_CLK_SCIF1
1271                                 R8A7794_CLK_SCIF0
1272                                 R8A7794_CLK_DU1 R8A7794_CLK_DU0
1273                         >;
1274                         clock-output-names =
1275                                 "ehci", "hsusb",
1276                                 "hscif2", "scif5", "scif4", "hscif1", "hscif0",
1277                                 "scif3", "scif2", "scif1", "scif0",
1278                                 "du1", "du0";
1279                 };
1280                 mstp8_clks: mstp8_clks@e6150990 {
1281                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1282                         reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
1283                         clocks = <&zg_clk>, <&zg_clk>, <&hp_clk>, <&p_clk>;
1284                         #clock-cells = <1>;
1285                         clock-indices = <
1286                                 R8A7794_CLK_VIN1 R8A7794_CLK_VIN0
1287                                 R8A7794_CLK_ETHERAVB R8A7794_CLK_ETHER
1288                         >;
1289                         clock-output-names =
1290                                 "vin1", "vin0", "etheravb", "ether";
1291                 };
1292                 mstp9_clks: mstp9_clks@e6150994 {
1293                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1294                         reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
1295                         clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1296                                  <&cp_clk>, <&cp_clk>, <&cp_clk>, <&p_clk>,
1297                                  <&p_clk>, <&cpg_clocks R8A7794_CLK_QSPI>,
1298                                  <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
1299                                  <&hp_clk>, <&hp_clk>;
1300                         #clock-cells = <1>;
1301                         clock-indices = <R8A7794_CLK_GPIO6 R8A7794_CLK_GPIO5
1302                                          R8A7794_CLK_GPIO4 R8A7794_CLK_GPIO3
1303                                          R8A7794_CLK_GPIO2 R8A7794_CLK_GPIO1
1304                                          R8A7794_CLK_GPIO0 R8A7794_CLK_RCAN1
1305                                          R8A7794_CLK_RCAN0 R8A7794_CLK_QSPI_MOD
1306                                          R8A7794_CLK_I2C5 R8A7794_CLK_I2C4
1307                                          R8A7794_CLK_I2C3 R8A7794_CLK_I2C2
1308                                          R8A7794_CLK_I2C1 R8A7794_CLK_I2C0>;
1309                         clock-output-names =
1310                                 "gpio6", "gpio5", "gpio4", "gpio3", "gpio2",
1311                                 "gpio1", "gpio0", "rcan1", "rcan0", "qspi_mod",
1312                                 "i2c5", "i2c4", "i2c3", "i2c2", "i2c1", "i2c0";
1313                 };
1314                 mstp10_clks: mstp10_clks@e6150998 {
1315                         compatible = "renesas,r8a7794-mstp-clocks",
1316                                      "renesas,cpg-mstp-clocks";
1317                         reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
1318                         clocks = <&p_clk>,
1319                                  <&mstp10_clks R8A7794_CLK_SSI_ALL>,
1320                                  <&mstp10_clks R8A7794_CLK_SSI_ALL>,
1321                                  <&mstp10_clks R8A7794_CLK_SSI_ALL>,
1322                                  <&mstp10_clks R8A7794_CLK_SSI_ALL>,
1323                                  <&mstp10_clks R8A7794_CLK_SSI_ALL>,
1324                                  <&mstp10_clks R8A7794_CLK_SSI_ALL>,
1325                                  <&mstp10_clks R8A7794_CLK_SSI_ALL>,
1326                                  <&mstp10_clks R8A7794_CLK_SSI_ALL>,
1327                                  <&mstp10_clks R8A7794_CLK_SSI_ALL>,
1328                                  <&mstp10_clks R8A7794_CLK_SSI_ALL>,
1329                                  <&p_clk>,
1330                                  <&mstp10_clks R8A7794_CLK_SCU_ALL>,
1331                                  <&mstp10_clks R8A7794_CLK_SCU_ALL>,
1332                                  <&mstp10_clks R8A7794_CLK_SCU_ALL>,
1333                                  <&mstp10_clks R8A7794_CLK_SCU_ALL>,
1334                                  <&mstp10_clks R8A7794_CLK_SCU_ALL>,
1335                                  <&mstp10_clks R8A7794_CLK_SCU_ALL>,
1336                                  <&mstp10_clks R8A7794_CLK_SCU_ALL>,
1337                                  <&mstp10_clks R8A7794_CLK_SCU_ALL>,
1338                                  <&mstp10_clks R8A7794_CLK_SCU_ALL>,
1339                                  <&mstp10_clks R8A7794_CLK_SCU_ALL>;
1340                         #clock-cells = <1>;
1341                         clock-indices = <R8A7794_CLK_SSI_ALL
1342                                          R8A7794_CLK_SSI9 R8A7794_CLK_SSI8
1343                                          R8A7794_CLK_SSI7 R8A7794_CLK_SSI6
1344                                          R8A7794_CLK_SSI5 R8A7794_CLK_SSI4
1345                                          R8A7794_CLK_SSI3 R8A7794_CLK_SSI2
1346                                          R8A7794_CLK_SSI1 R8A7794_CLK_SSI0
1347                                          R8A7794_CLK_SCU_ALL
1348                                          R8A7794_CLK_SCU_DVC1
1349                                          R8A7794_CLK_SCU_DVC0
1350                                          R8A7794_CLK_SCU_CTU1_MIX1
1351                                          R8A7794_CLK_SCU_CTU0_MIX0
1352                                          R8A7794_CLK_SCU_SRC6
1353                                          R8A7794_CLK_SCU_SRC5
1354                                          R8A7794_CLK_SCU_SRC4
1355                                          R8A7794_CLK_SCU_SRC3
1356                                          R8A7794_CLK_SCU_SRC2
1357                                          R8A7794_CLK_SCU_SRC1>;
1358                         clock-output-names = "ssi-all", "ssi9", "ssi8", "ssi7",
1359                                              "ssi6", "ssi5", "ssi4", "ssi3",
1360                                              "ssi2", "ssi1", "ssi0",
1361                                              "scu-all", "scu-dvc1", "scu-dvc0",
1362                                              "scu-ctu1-mix1", "scu-ctu0-mix0",
1363                                              "scu-src6", "scu-src5", "scu-src4",
1364                                              "scu-src3", "scu-src2", "scu-src1";
1365                 };
1366                 mstp11_clks: mstp11_clks@e615099c {
1367                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1368                         reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
1369                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
1370                         #clock-cells = <1>;
1371                         clock-indices = <
1372                                 R8A7794_CLK_SCIFA3 R8A7794_CLK_SCIFA4 R8A7794_CLK_SCIFA5
1373                         >;
1374                         clock-output-names = "scifa3", "scifa4", "scifa5";
1375                 };
1376         };
1377
1378         sysc: system-controller@e6180000 {
1379                 compatible = "renesas,r8a7794-sysc";
1380                 reg = <0 0xe6180000 0 0x0200>;
1381                 #power-domain-cells = <1>;
1382         };
1383
1384         ipmmu_sy0: mmu@e6280000 {
1385                 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1386                 reg = <0 0xe6280000 0 0x1000>;
1387                 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
1388                              <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
1389                 #iommu-cells = <1>;
1390                 status = "disabled";
1391         };
1392
1393         ipmmu_sy1: mmu@e6290000 {
1394                 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1395                 reg = <0 0xe6290000 0 0x1000>;
1396                 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1397                 #iommu-cells = <1>;
1398                 status = "disabled";
1399         };
1400
1401         ipmmu_ds: mmu@e6740000 {
1402                 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1403                 reg = <0 0xe6740000 0 0x1000>;
1404                 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
1405                              <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
1406                 #iommu-cells = <1>;
1407                 status = "disabled";
1408         };
1409
1410         ipmmu_mp: mmu@ec680000 {
1411                 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1412                 reg = <0 0xec680000 0 0x1000>;
1413                 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1414                 #iommu-cells = <1>;
1415                 status = "disabled";
1416         };
1417
1418         ipmmu_mx: mmu@fe951000 {
1419                 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1420                 reg = <0 0xfe951000 0 0x1000>;
1421                 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
1422                              <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1423                 #iommu-cells = <1>;
1424                 status = "disabled";
1425         };
1426
1427         ipmmu_gp: mmu@e62a0000 {
1428                 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1429                 reg = <0 0xe62a0000 0 0x1000>;
1430                 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
1431                              <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
1432                 #iommu-cells = <1>;
1433                 status = "disabled";
1434         };
1435
1436         rcar_sound: sound@ec500000 {
1437                 /*
1438                  * #sound-dai-cells is required
1439                  *
1440                  * Single DAI : #sound-dai-cells = <0>;         <&rcar_sound>;
1441                  * Multi  DAI : #sound-dai-cells = <1>;         <&rcar_sound N>;
1442                  */
1443                 compatible = "renesas,rcar_sound-r8a7794",
1444                              "renesas,rcar_sound-gen2";
1445                 reg =   <0 0xec500000 0 0x1000>, /* SCU */
1446                         <0 0xec5a0000 0 0x100>,  /* ADG */
1447                         <0 0xec540000 0 0x1000>, /* SSIU */
1448                         <0 0xec541000 0 0x280>,  /* SSI */
1449                         <0 0xec740000 0 0x200>;  /* Audio DMAC peri peri */
1450                 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1451
1452                 clocks = <&mstp10_clks R8A7794_CLK_SSI_ALL>,
1453                          <&mstp10_clks R8A7794_CLK_SSI9>,
1454                          <&mstp10_clks R8A7794_CLK_SSI8>,
1455                          <&mstp10_clks R8A7794_CLK_SSI7>,
1456                          <&mstp10_clks R8A7794_CLK_SSI6>,
1457                          <&mstp10_clks R8A7794_CLK_SSI5>,
1458                          <&mstp10_clks R8A7794_CLK_SSI4>,
1459                          <&mstp10_clks R8A7794_CLK_SSI3>,
1460                          <&mstp10_clks R8A7794_CLK_SSI2>,
1461                          <&mstp10_clks R8A7794_CLK_SSI1>,
1462                          <&mstp10_clks R8A7794_CLK_SSI0>,
1463                          <&mstp10_clks R8A7794_CLK_SCU_SRC6>,
1464                          <&mstp10_clks R8A7794_CLK_SCU_SRC5>,
1465                          <&mstp10_clks R8A7794_CLK_SCU_SRC4>,
1466                          <&mstp10_clks R8A7794_CLK_SCU_SRC3>,
1467                          <&mstp10_clks R8A7794_CLK_SCU_SRC2>,
1468                          <&mstp10_clks R8A7794_CLK_SCU_SRC1>,
1469                          <&mstp10_clks R8A7794_CLK_SCU_CTU0_MIX0>,
1470                          <&mstp10_clks R8A7794_CLK_SCU_CTU1_MIX1>,
1471                          <&mstp10_clks R8A7794_CLK_SCU_CTU0_MIX0>,
1472                          <&mstp10_clks R8A7794_CLK_SCU_CTU1_MIX1>,
1473                          <&mstp10_clks R8A7794_CLK_SCU_DVC0>,
1474                          <&mstp10_clks R8A7794_CLK_SCU_DVC1>,
1475                          <&audio_clka>, <&audio_clkb>, <&audio_clkc>,
1476                          <&m2_clk>;
1477                 clock-names = "ssi-all",
1478                               "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
1479                               "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
1480                               "src.6", "src.5", "src.4", "src.3", "src.2",
1481                               "src.1",
1482                               "ctu.0", "ctu.1",
1483                               "mix.0", "mix.1",
1484                               "dvc.0", "dvc.1",
1485                               "clk_a", "clk_b", "clk_c", "clk_i";
1486                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
1487
1488                 status = "disabled";
1489
1490                 rcar_sound,dvc {
1491                         dvc0: dvc@0 {
1492                                 dmas = <&audma0 0xbc>;
1493                                 dma-names = "tx";
1494                         };
1495                         dvc1: dvc@1 {
1496                                 dmas = <&audma0 0xbe>;
1497                                 dma-names = "tx";
1498                         };
1499                 };
1500
1501                 rcar_sound,mix {
1502                         mix0: mix@0 { };
1503                         mix1: mix@1 { };
1504                 };
1505
1506                 rcar_sound,ctu {
1507                         ctu00: ctu@0 { };
1508                         ctu01: ctu@1 { };
1509                         ctu02: ctu@2 { };
1510                         ctu03: ctu@3 { };
1511                         ctu10: ctu@4 { };
1512                         ctu11: ctu@5 { };
1513                         ctu12: ctu@6 { };
1514                         ctu13: ctu@7 { };
1515                 };
1516
1517                 rcar_sound,src {
1518                         src@0 {
1519                                 status = "disabled";
1520                         };
1521                         src1: src@1 {
1522                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1523                                 dmas = <&audma0 0x87>, <&audma0 0x9c>;
1524                                 dma-names = "rx", "tx";
1525                         };
1526                         src2: src@2 {
1527                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1528                                 dmas = <&audma0 0x89>, <&audma0 0x9e>;
1529                                 dma-names = "rx", "tx";
1530                         };
1531                         src3: src@3 {
1532                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1533                                 dmas = <&audma0 0x8b>, <&audma0 0xa0>;
1534                                 dma-names = "rx", "tx";
1535                         };
1536                         src4: src@4 {
1537                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1538                                 dmas = <&audma0 0x8d>, <&audma0 0xb0>;
1539                                 dma-names = "rx", "tx";
1540                         };
1541                         src5: src@5 {
1542                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1543                                 dmas = <&audma0 0x8f>, <&audma0 0xb2>;
1544                                 dma-names = "rx", "tx";
1545                         };
1546                         src6: src@6 {
1547                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1548                                 dmas = <&audma0 0x91>, <&audma0 0xb4>;
1549                                 dma-names = "rx", "tx";
1550                         };
1551                 };
1552
1553                 rcar_sound,ssi {
1554                         ssi0: ssi@0 {
1555                                 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
1556                                 dmas = <&audma0 0x01>, <&audma0 0x02>,
1557                                        <&audma0 0x15>, <&audma0 0x16>;
1558                                 dma-names = "rx", "tx", "rxu", "txu";
1559                         };
1560                         ssi1: ssi@1 {
1561                                 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1562                                 dmas = <&audma0 0x03>, <&audma0 0x04>,
1563                                        <&audma0 0x49>, <&audma0 0x4a>;
1564                                 dma-names = "rx", "tx", "rxu", "txu";
1565                         };
1566                         ssi2: ssi@2 {
1567                                 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
1568                                 dmas = <&audma0 0x05>, <&audma0 0x06>,
1569                                        <&audma0 0x63>, <&audma0 0x64>;
1570                                 dma-names = "rx", "tx", "rxu", "txu";
1571                         };
1572                         ssi3: ssi@3 {
1573                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1574                                 dmas = <&audma0 0x07>, <&audma0 0x08>,
1575                                        <&audma0 0x6f>, <&audma0 0x70>;
1576                                 dma-names = "rx", "tx", "rxu", "txu";
1577                         };
1578                         ssi4: ssi@4 {
1579                                 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1580                                 dmas = <&audma0 0x09>, <&audma0 0x0a>,
1581                                        <&audma0 0x71>, <&audma0 0x72>;
1582                                 dma-names = "rx", "tx", "rxu", "txu";
1583                         };
1584                         ssi5: ssi@5 {
1585                                 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1586                                 dmas = <&audma0 0x0b>, <&audma0 0x0c>,
1587                                        <&audma0 0x73>, <&audma0 0x74>;
1588                                 dma-names = "rx", "tx", "rxu", "txu";
1589                         };
1590                         ssi6: ssi@6 {
1591                                 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
1592                                 dmas = <&audma0 0x0d>, <&audma0 0x0e>,
1593                                        <&audma0 0x75>, <&audma0 0x76>;
1594                                 dma-names = "rx", "tx", "rxu", "txu";
1595                         };
1596                         ssi7: ssi@7 {
1597                                 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
1598                                 dmas = <&audma0 0x0f>, <&audma0 0x10>,
1599                                        <&audma0 0x79>, <&audma0 0x7a>;
1600                                 dma-names = "rx", "tx", "rxu", "txu";
1601                         };
1602                         ssi8: ssi@8 {
1603                                 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
1604                                 dmas = <&audma0 0x11>, <&audma0 0x12>,
1605                                        <&audma0 0x7b>, <&audma0 0x7c>;
1606                                 dma-names = "rx", "tx", "rxu", "txu";
1607                         };
1608                         ssi9: ssi@9 {
1609                                 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
1610                                 dmas = <&audma0 0x13>, <&audma0 0x14>,
1611                                        <&audma0 0x7d>, <&audma0 0x7e>;
1612                                 dma-names = "rx", "tx", "rxu", "txu";
1613                         };
1614                 };
1615         };
1616 };