2 * Device Tree Source for the r8a7792 SoC
4 * Copyright (C) 2016 Cogent Embedded Inc.
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
11 #include <dt-bindings/clock/r8a7792-clock.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/power/r8a7792-sysc.h>
17 compatible = "renesas,r8a7792";
40 enable-method = "renesas,apmu";
44 compatible = "arm,cortex-a15";
46 clock-frequency = <1000000000>;
47 clocks = <&cpg_clocks R8A7792_CLK_Z>;
48 power-domains = <&sysc R8A7792_PD_CA15_CPU0>;
49 next-level-cache = <&L2_CA15>;
54 compatible = "arm,cortex-a15";
56 clock-frequency = <1000000000>;
57 power-domains = <&sysc R8A7792_PD_CA15_CPU1>;
58 next-level-cache = <&L2_CA15>;
61 L2_CA15: cache-controller-0 {
65 power-domains = <&sysc R8A7792_PD_CA15_SCU>;
70 compatible = "simple-bus";
71 interrupt-parent = <&gic>;
78 compatible = "renesas,r8a7792-apmu", "renesas,apmu";
79 reg = <0 0xe6152000 0 0x188>;
83 gic: interrupt-controller@f1001000 {
84 compatible = "arm,gic-400";
85 #interrupt-cells = <3>;
87 reg = <0 0xf1001000 0 0x1000>,
88 <0 0xf1002000 0 0x1000>,
89 <0 0xf1004000 0 0x2000>,
90 <0 0xf1006000 0 0x2000>;
91 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
92 IRQ_TYPE_LEVEL_HIGH)>;
95 irqc: interrupt-controller@e61c0000 {
96 compatible = "renesas,irqc-r8a7792", "renesas,irqc";
97 #interrupt-cells = <2>;
99 reg = <0 0xe61c0000 0 0x200>;
100 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
101 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
102 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
103 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
104 clocks = <&mstp4_clks R8A7792_CLK_IRQC>;
105 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
109 compatible = "arm,armv7-timer";
110 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
111 IRQ_TYPE_LEVEL_LOW)>,
112 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
113 IRQ_TYPE_LEVEL_LOW)>,
114 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
115 IRQ_TYPE_LEVEL_LOW)>,
116 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
117 IRQ_TYPE_LEVEL_LOW)>;
120 sysc: system-controller@e6180000 {
121 compatible = "renesas,r8a7792-sysc";
122 reg = <0 0xe6180000 0 0x0200>;
123 #power-domain-cells = <1>;
126 pfc: pin-controller@e6060000 {
127 compatible = "renesas,pfc-r8a7792";
128 reg = <0 0xe6060000 0 0x144>;
131 gpio0: gpio@e6050000 {
132 compatible = "renesas,gpio-r8a7792",
134 reg = <0 0xe6050000 0 0x50>;
135 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
138 gpio-ranges = <&pfc 0 0 29>;
139 #interrupt-cells = <2>;
140 interrupt-controller;
141 clocks = <&mstp9_clks R8A7792_CLK_GPIO0>;
142 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
145 gpio1: gpio@e6051000 {
146 compatible = "renesas,gpio-r8a7792",
148 reg = <0 0xe6051000 0 0x50>;
149 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
152 gpio-ranges = <&pfc 0 32 23>;
153 #interrupt-cells = <2>;
154 interrupt-controller;
155 clocks = <&mstp9_clks R8A7792_CLK_GPIO1>;
156 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
159 gpio2: gpio@e6052000 {
160 compatible = "renesas,gpio-r8a7792",
162 reg = <0 0xe6052000 0 0x50>;
163 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
166 gpio-ranges = <&pfc 0 64 32>;
167 #interrupt-cells = <2>;
168 interrupt-controller;
169 clocks = <&mstp9_clks R8A7792_CLK_GPIO2>;
170 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
173 gpio3: gpio@e6053000 {
174 compatible = "renesas,gpio-r8a7792",
176 reg = <0 0xe6053000 0 0x50>;
177 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
180 gpio-ranges = <&pfc 0 96 28>;
181 #interrupt-cells = <2>;
182 interrupt-controller;
183 clocks = <&mstp9_clks R8A7792_CLK_GPIO3>;
184 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
187 gpio4: gpio@e6054000 {
188 compatible = "renesas,gpio-r8a7792",
190 reg = <0 0xe6054000 0 0x50>;
191 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
194 gpio-ranges = <&pfc 0 128 17>;
195 #interrupt-cells = <2>;
196 interrupt-controller;
197 clocks = <&mstp9_clks R8A7792_CLK_GPIO4>;
198 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
201 gpio5: gpio@e6055000 {
202 compatible = "renesas,gpio-r8a7792",
204 reg = <0 0xe6055000 0 0x50>;
205 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
208 gpio-ranges = <&pfc 0 160 17>;
209 #interrupt-cells = <2>;
210 interrupt-controller;
211 clocks = <&mstp9_clks R8A7792_CLK_GPIO5>;
212 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
215 gpio6: gpio@e6055100 {
216 compatible = "renesas,gpio-r8a7792",
218 reg = <0 0xe6055100 0 0x50>;
219 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
222 gpio-ranges = <&pfc 0 192 17>;
223 #interrupt-cells = <2>;
224 interrupt-controller;
225 clocks = <&mstp9_clks R8A7792_CLK_GPIO6>;
226 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
229 gpio7: gpio@e6055200 {
230 compatible = "renesas,gpio-r8a7792",
232 reg = <0 0xe6055200 0 0x50>;
233 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
236 gpio-ranges = <&pfc 0 224 17>;
237 #interrupt-cells = <2>;
238 interrupt-controller;
239 clocks = <&mstp9_clks R8A7792_CLK_GPIO7>;
240 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
243 gpio8: gpio@e6055300 {
244 compatible = "renesas,gpio-r8a7792",
246 reg = <0 0xe6055300 0 0x50>;
247 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
250 gpio-ranges = <&pfc 0 256 17>;
251 #interrupt-cells = <2>;
252 interrupt-controller;
253 clocks = <&mstp9_clks R8A7792_CLK_GPIO8>;
254 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
257 gpio9: gpio@e6055400 {
258 compatible = "renesas,gpio-r8a7792",
260 reg = <0 0xe6055400 0 0x50>;
261 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
264 gpio-ranges = <&pfc 0 288 17>;
265 #interrupt-cells = <2>;
266 interrupt-controller;
267 clocks = <&mstp9_clks R8A7792_CLK_GPIO9>;
268 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
271 gpio10: gpio@e6055500 {
272 compatible = "renesas,gpio-r8a7792",
274 reg = <0 0xe6055500 0 0x50>;
275 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
278 gpio-ranges = <&pfc 0 320 32>;
279 #interrupt-cells = <2>;
280 interrupt-controller;
281 clocks = <&mstp9_clks R8A7792_CLK_GPIO10>;
282 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
285 gpio11: gpio@e6055600 {
286 compatible = "renesas,gpio-r8a7792",
288 reg = <0 0xe6055600 0 0x50>;
289 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
292 gpio-ranges = <&pfc 0 352 30>;
293 #interrupt-cells = <2>;
294 interrupt-controller;
295 clocks = <&mstp9_clks R8A7792_CLK_GPIO11>;
296 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
299 dmac0: dma-controller@e6700000 {
300 compatible = "renesas,dmac-r8a7792",
302 reg = <0 0xe6700000 0 0x20000>;
303 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
304 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
305 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
306 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
307 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
308 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
309 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
310 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
311 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
312 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
313 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
314 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
315 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
316 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
317 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
318 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
319 interrupt-names = "error",
320 "ch0", "ch1", "ch2", "ch3",
321 "ch4", "ch5", "ch6", "ch7",
322 "ch8", "ch9", "ch10", "ch11",
323 "ch12", "ch13", "ch14";
324 clocks = <&mstp2_clks R8A7792_CLK_SYS_DMAC0>;
326 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
331 dmac1: dma-controller@e6720000 {
332 compatible = "renesas,dmac-r8a7792",
334 reg = <0 0xe6720000 0 0x20000>;
335 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
336 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
337 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
338 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
339 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
340 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
341 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
342 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
343 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
344 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
345 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
346 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
347 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
348 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
349 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
350 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
351 interrupt-names = "error",
352 "ch0", "ch1", "ch2", "ch3",
353 "ch4", "ch5", "ch6", "ch7",
354 "ch8", "ch9", "ch10", "ch11",
355 "ch12", "ch13", "ch14";
356 clocks = <&mstp2_clks R8A7792_CLK_SYS_DMAC1>;
358 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
363 scif0: serial@e6e60000 {
364 compatible = "renesas,scif-r8a7792",
365 "renesas,rcar-gen2-scif", "renesas,scif";
366 reg = <0 0xe6e60000 0 64>;
367 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
368 clocks = <&mstp7_clks R8A7792_CLK_SCIF0>, <&zs_clk>,
370 clock-names = "fck", "brg_int", "scif_clk";
371 dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
372 <&dmac1 0x29>, <&dmac1 0x2a>;
373 dma-names = "tx", "rx", "tx", "rx";
374 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
378 scif1: serial@e6e68000 {
379 compatible = "renesas,scif-r8a7792",
380 "renesas,rcar-gen2-scif", "renesas,scif";
381 reg = <0 0xe6e68000 0 64>;
382 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
383 clocks = <&mstp7_clks R8A7792_CLK_SCIF1>, <&zs_clk>,
385 clock-names = "fck", "brg_int", "scif_clk";
386 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
387 <&dmac1 0x2d>, <&dmac1 0x2e>;
388 dma-names = "tx", "rx", "tx", "rx";
389 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
393 scif2: serial@e6e58000 {
394 compatible = "renesas,scif-r8a7792",
395 "renesas,rcar-gen2-scif", "renesas,scif";
396 reg = <0 0xe6e58000 0 64>;
397 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
398 clocks = <&mstp7_clks R8A7792_CLK_SCIF2>, <&zs_clk>,
400 clock-names = "fck", "brg_int", "scif_clk";
401 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
402 <&dmac1 0x2b>, <&dmac1 0x2c>;
403 dma-names = "tx", "rx", "tx", "rx";
404 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
408 scif3: serial@e6ea8000 {
409 compatible = "renesas,scif-r8a7792",
410 "renesas,rcar-gen2-scif", "renesas,scif";
411 reg = <0 0xe6ea8000 0 64>;
412 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
413 clocks = <&mstp7_clks R8A7792_CLK_SCIF3>, <&zs_clk>,
415 clock-names = "fck", "brg_int", "scif_clk";
416 dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
417 <&dmac1 0x2f>, <&dmac1 0x30>;
418 dma-names = "tx", "rx", "tx", "rx";
419 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
423 hscif0: serial@e62c0000 {
424 compatible = "renesas,hscif-r8a7792",
425 "renesas,rcar-gen2-hscif", "renesas,hscif";
426 reg = <0 0xe62c0000 0 96>;
427 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
428 clocks = <&mstp7_clks R8A7792_CLK_HSCIF0>, <&zs_clk>,
430 clock-names = "fck", "brg_int", "scif_clk";
431 dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
432 <&dmac1 0x39>, <&dmac1 0x3a>;
433 dma-names = "tx", "rx", "tx", "rx";
434 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
438 hscif1: serial@e62c8000 {
439 compatible = "renesas,hscif-r8a7792",
440 "renesas,rcar-gen2-hscif", "renesas,hscif";
441 reg = <0 0xe62c8000 0 96>;
442 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
443 clocks = <&mstp7_clks R8A7792_CLK_HSCIF1>, <&zs_clk>,
445 clock-names = "fck", "brg_int", "scif_clk";
446 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
447 <&dmac1 0x4d>, <&dmac1 0x4e>;
448 dma-names = "tx", "rx", "tx", "rx";
449 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
454 compatible = "renesas,sdhi-r8a7792";
455 reg = <0 0xee100000 0 0x328>;
456 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
457 dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
458 <&dmac1 0xcd>, <&dmac1 0xce>;
459 dma-names = "tx", "rx", "tx", "rx";
460 clocks = <&mstp3_clks R8A7792_CLK_SDHI0>;
461 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
465 jpu: jpeg-codec@fe980000 {
466 compatible = "renesas,jpu-r8a7792",
467 "renesas,rcar-gen2-jpu";
468 reg = <0 0xfe980000 0 0x10300>;
469 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
470 clocks = <&mstp1_clks R8A7792_CLK_JPU>;
471 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
474 avb: ethernet@e6800000 {
475 compatible = "renesas,etheravb-r8a7792",
476 "renesas,etheravb-rcar-gen2";
477 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
478 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
479 clocks = <&mstp8_clks R8A7792_CLK_ETHERAVB>;
480 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
481 #address-cells = <1>;
486 /* I2C doesn't need pinmux */
488 compatible = "renesas,i2c-r8a7792";
489 reg = <0 0xe6508000 0 0x40>;
490 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
491 clocks = <&mstp9_clks R8A7792_CLK_I2C0>;
492 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
493 i2c-scl-internal-delay-ns = <6>;
494 #address-cells = <1>;
500 compatible = "renesas,i2c-r8a7792";
501 reg = <0 0xe6518000 0 0x40>;
502 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
503 clocks = <&mstp9_clks R8A7792_CLK_I2C1>;
504 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
505 i2c-scl-internal-delay-ns = <6>;
506 #address-cells = <1>;
512 compatible = "renesas,i2c-r8a7792";
513 reg = <0 0xe6530000 0 0x40>;
514 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
515 clocks = <&mstp9_clks R8A7792_CLK_I2C2>;
516 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
517 i2c-scl-internal-delay-ns = <6>;
518 #address-cells = <1>;
524 compatible = "renesas,i2c-r8a7792";
525 reg = <0 0xe6540000 0 0x40>;
526 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
527 clocks = <&mstp9_clks R8A7792_CLK_I2C3>;
528 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
529 i2c-scl-internal-delay-ns = <6>;
530 #address-cells = <1>;
536 compatible = "renesas,i2c-r8a7792";
537 reg = <0 0xe6520000 0 0x40>;
538 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
539 clocks = <&mstp9_clks R8A7792_CLK_I2C4>;
540 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
541 i2c-scl-internal-delay-ns = <6>;
542 #address-cells = <1>;
548 compatible = "renesas,i2c-r8a7792";
549 reg = <0 0xe6528000 0 0x40>;
550 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
551 clocks = <&mstp9_clks R8A7792_CLK_I2C5>;
552 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
553 i2c-scl-internal-delay-ns = <110>;
554 #address-cells = <1>;
560 compatible = "renesas,qspi-r8a7792", "renesas,qspi";
561 reg = <0 0xe6b10000 0 0x2c>;
562 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
563 clocks = <&mstp9_clks R8A7792_CLK_QSPI_MOD>;
564 dmas = <&dmac0 0x17>, <&dmac0 0x18>,
565 <&dmac1 0x17>, <&dmac1 0x18>;
566 dma-names = "tx", "rx", "tx", "rx";
567 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
569 #address-cells = <1>;
574 du: display@feb00000 {
575 compatible = "renesas,du-r8a7792";
576 reg = <0 0xfeb00000 0 0x40000>;
578 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
579 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
580 clocks = <&mstp7_clks R8A7792_CLK_DU0>,
581 <&mstp7_clks R8A7792_CLK_DU1>;
582 clock-names = "du.0", "du.1";
586 #address-cells = <1>;
591 du_out_rgb0: endpoint {
596 du_out_rgb1: endpoint {
603 compatible = "renesas,can-r8a7792",
604 "renesas,rcar-gen2-can";
605 reg = <0 0xe6e80000 0 0x1000>;
606 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
607 clocks = <&mstp9_clks R8A7792_CLK_CAN0>,
608 <&rcan_clk>, <&can_clk>;
609 clock-names = "clkp1", "clkp2", "can_clk";
610 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
615 compatible = "renesas,can-r8a7792",
616 "renesas,rcar-gen2-can";
617 reg = <0 0xe6e88000 0 0x1000>;
618 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
619 clocks = <&mstp9_clks R8A7792_CLK_CAN1>,
620 <&rcan_clk>, <&can_clk>;
621 clock-names = "clkp1", "clkp2", "can_clk";
622 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
626 vin0: video@e6ef0000 {
627 compatible = "renesas,vin-r8a7792",
628 "renesas,rcar-gen2-vin";
629 reg = <0 0xe6ef0000 0 0x1000>;
630 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
631 clocks = <&mstp8_clks R8A7792_CLK_VIN0>;
632 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
636 vin1: video@e6ef1000 {
637 compatible = "renesas,vin-r8a7792",
638 "renesas,rcar-gen2-vin";
639 reg = <0 0xe6ef1000 0 0x1000>;
640 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
641 clocks = <&mstp8_clks R8A7792_CLK_VIN1>;
642 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
646 vin2: video@e6ef2000 {
647 compatible = "renesas,vin-r8a7792",
648 "renesas,rcar-gen2-vin";
649 reg = <0 0xe6ef2000 0 0x1000>;
650 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
651 clocks = <&mstp8_clks R8A7792_CLK_VIN2>;
652 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
656 vin3: video@e6ef3000 {
657 compatible = "renesas,vin-r8a7792",
658 "renesas,rcar-gen2-vin";
659 reg = <0 0xe6ef3000 0 0x1000>;
660 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
661 clocks = <&mstp8_clks R8A7792_CLK_VIN3>;
662 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
666 vin4: video@e6ef4000 {
667 compatible = "renesas,vin-r8a7792",
668 "renesas,rcar-gen2-vin";
669 reg = <0 0xe6ef4000 0 0x1000>;
670 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
671 clocks = <&mstp8_clks R8A7792_CLK_VIN4>;
672 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
676 vin5: video@e6ef5000 {
677 compatible = "renesas,vin-r8a7792",
678 "renesas,rcar-gen2-vin";
679 reg = <0 0xe6ef5000 0 0x1000>;
680 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
681 clocks = <&mstp8_clks R8A7792_CLK_VIN5>;
682 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
687 compatible = "renesas,vsp1";
688 reg = <0 0xfe928000 0 0x8000>;
689 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
690 clocks = <&mstp1_clks R8A7792_CLK_VSP1_SY>;
691 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
695 compatible = "renesas,vsp1";
696 reg = <0 0xfe930000 0 0x8000>;
697 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
698 clocks = <&mstp1_clks R8A7792_CLK_VSP1DU0>;
699 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
703 compatible = "renesas,vsp1";
704 reg = <0 0xfe938000 0 0x8000>;
705 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
706 clocks = <&mstp1_clks R8A7792_CLK_VSP1DU1>;
707 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
710 /* Special CPG clocks */
711 cpg_clocks: cpg_clocks@e6150000 {
712 compatible = "renesas,r8a7792-cpg-clocks",
713 "renesas,rcar-gen2-cpg-clocks";
714 reg = <0 0xe6150000 0 0x1000>;
715 clocks = <&extal_clk>;
717 clock-output-names = "main", "pll0", "pll1", "pll3",
719 #power-domain-cells = <0>;
722 /* Fixed factor clocks */
723 pll1_div2_clk: pll1_div2 {
724 compatible = "fixed-factor-clock";
725 clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
731 compatible = "fixed-factor-clock";
732 clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
738 compatible = "fixed-factor-clock";
739 clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
745 compatible = "fixed-factor-clock";
746 clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
752 compatible = "fixed-factor-clock";
753 clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
759 compatible = "fixed-factor-clock";
760 clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
766 compatible = "fixed-factor-clock";
767 clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
773 compatible = "fixed-factor-clock";
774 clocks = <&pll1_div2_clk>;
780 compatible = "fixed-factor-clock";
781 clocks = <&pll1_div2_clk>;
787 compatible = "fixed-factor-clock";
788 clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
795 mstp1_clks: mstp1_clks@e6150134 {
796 compatible = "renesas,r8a7792-mstp-clocks",
797 "renesas,cpg-mstp-clocks";
798 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
799 clocks = <&m2_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
803 R8A7792_CLK_VSP1DU1 R8A7792_CLK_VSP1DU0
806 clock-output-names = "jpu", "vsp1du1", "vsp1du0",
809 mstp2_clks: mstp2_clks@e6150138 {
810 compatible = "renesas,r8a7792-mstp-clocks",
811 "renesas,cpg-mstp-clocks";
812 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
813 clocks = <&zs_clk>, <&zs_clk>;
816 R8A7792_CLK_SYS_DMAC1 R8A7792_CLK_SYS_DMAC0
818 clock-output-names = "sys-dmac1", "sys-dmac0";
820 mstp3_clks: mstp3_clks@e615013c {
821 compatible = "renesas,r8a7792-mstp-clocks",
822 "renesas,cpg-mstp-clocks";
823 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
826 renesas,clock-indices = <R8A7792_CLK_SDHI0>;
827 clock-output-names = "sdhi0";
829 mstp4_clks: mstp4_clks@e6150140 {
830 compatible = "renesas,r8a7792-mstp-clocks",
831 "renesas,cpg-mstp-clocks";
832 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
835 clock-indices = <R8A7792_CLK_IRQC>;
836 clock-output-names = "irqc";
838 mstp7_clks: mstp7_clks@e615014c {
839 compatible = "renesas,r8a7792-mstp-clocks",
840 "renesas,cpg-mstp-clocks";
841 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
842 clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>,
843 <&p_clk>, <&p_clk>, <&zx_clk>, <&zx_clk>;
846 R8A7792_CLK_HSCIF1 R8A7792_CLK_HSCIF0
847 R8A7792_CLK_SCIF3 R8A7792_CLK_SCIF2
848 R8A7792_CLK_SCIF1 R8A7792_CLK_SCIF0
849 R8A7792_CLK_DU1 R8A7792_CLK_DU0
851 clock-output-names = "hscif1", "hscif0", "scif3",
852 "scif2", "scif1", "scif0",
855 mstp8_clks: mstp8_clks@e6150990 {
856 compatible = "renesas,r8a7792-mstp-clocks",
857 "renesas,cpg-mstp-clocks";
858 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
859 clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
860 <&zg_clk>, <&zg_clk>, <&hp_clk>;
863 R8A7792_CLK_VIN5 R8A7792_CLK_VIN4
864 R8A7792_CLK_VIN3 R8A7792_CLK_VIN2
865 R8A7792_CLK_VIN1 R8A7792_CLK_VIN0
868 clock-output-names = "vin5", "vin4", "vin3", "vin2",
869 "vin1", "vin0", "etheravb";
871 mstp9_clks: mstp9_clks@e6150994 {
872 compatible = "renesas,r8a7792-mstp-clocks",
873 "renesas,cpg-mstp-clocks";
874 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
875 clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
876 <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
877 <&cp_clk>, <&cp_clk>, <&p_clk>, <&p_clk>,
878 <&cpg_clocks R8A7792_CLK_QSPI>,
879 <&cp_clk>, <&cp_clk>, <&hp_clk>, <&hp_clk>,
880 <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
883 R8A7792_CLK_GPIO7 R8A7792_CLK_GPIO6
884 R8A7792_CLK_GPIO5 R8A7792_CLK_GPIO4
885 R8A7792_CLK_GPIO3 R8A7792_CLK_GPIO2
886 R8A7792_CLK_GPIO1 R8A7792_CLK_GPIO0
887 R8A7792_CLK_GPIO11 R8A7792_CLK_GPIO10
888 R8A7792_CLK_CAN1 R8A7792_CLK_CAN0
890 R8A7792_CLK_GPIO9 R8A7792_CLK_GPIO8
891 R8A7792_CLK_I2C5 R8A7792_CLK_I2C4
892 R8A7792_CLK_I2C3 R8A7792_CLK_I2C2
893 R8A7792_CLK_I2C1 R8A7792_CLK_I2C0
896 "gpio7", "gpio6", "gpio5", "gpio4",
897 "gpio3", "gpio2", "gpio1", "gpio0",
898 "gpio11", "gpio10", "can1", "can0",
899 "qspi_mod", "gpio9", "gpio8",
900 "i2c5", "i2c4", "i2c3", "i2c2",
905 /* External root clock */
907 compatible = "fixed-clock";
909 /* This value must be overridden by the board. */
910 clock-frequency = <0>;
913 /* External SCIF clock */
915 compatible = "fixed-clock";
917 /* This value must be overridden by the board. */
918 clock-frequency = <0>;
921 /* External CAN clock */
923 compatible = "fixed-clock";
925 /* This value must be overridden by the board. */
926 clock-frequency = <0>;