arch/arm/boot/dts/r8a7779.dtsi

   1 /*
   2  * Device Tree Source for Renesas r8a7779
   3  *
   4  * Copyright (C) 2013 Renesas Solutions Corp.
   5  * Copyright (C) 2013 Simon Horman
   6  *
   7  * This file is licensed under the terms of the GNU General Public License
   8  * version 2.  This program is licensed "as is" without any warranty of any
   9  * kind, whether express or implied.
  10  */
  11
  12 #include <dt-bindings/clock/r8a7779-clock.h>
  13 #include <dt-bindings/interrupt-controller/arm-gic.h>
  14 #include <dt-bindings/interrupt-controller/irq.h>
  15 #include <dt-bindings/power/r8a7779-sysc.h>
  16
  17 / {
  18         compatible = "renesas,r8a7779";
  19         interrupt-parent = <&gic>;
  20         #address-cells = <1>;
  21         #size-cells = <1>;
  22
  23         cpus {
  24                 #address-cells = <1>;
  25                 #size-cells = <0>;
  26
  27                 cpu@0 {
  28                         device_type = "cpu";
  29                         compatible = "arm,cortex-a9";
  30                         reg = <0>;
  31                         clock-frequency = <1000000000>;
  32                 };
  33                 cpu@1 {
  34                         device_type = "cpu";
  35                         compatible = "arm,cortex-a9";
  36                         reg = <1>;
  37                         clock-frequency = <1000000000>;
  38                         power-domains = <&sysc R8A7779_PD_ARM1>;
  39                 };
  40                 cpu@2 {
  41                         device_type = "cpu";
  42                         compatible = "arm,cortex-a9";
  43                         reg = <2>;
  44                         clock-frequency = <1000000000>;
  45                         power-domains = <&sysc R8A7779_PD_ARM2>;
  46                 };
  47                 cpu@3 {
  48                         device_type = "cpu";
  49                         compatible = "arm,cortex-a9";
  50                         reg = <3>;
  51                         clock-frequency = <1000000000>;
  52                         power-domains = <&sysc R8A7779_PD_ARM3>;
  53                 };
  54         };
  55
  56         aliases {
  57                 spi0 = &hspi0;
  58                 spi1 = &hspi1;
  59                 spi2 = &hspi2;
  60         };
  61
  62         gic: interrupt-controller@f0001000 {
  63                 compatible = "arm,cortex-a9-gic";
  64                 #interrupt-cells = <3>;
  65                 interrupt-controller;
  66                 reg = <0xf0001000 0x1000>,
  67                       <0xf0000100 0x100>;
  68         };
  69
  70         timer@f0000200 {
  71                 compatible = "arm,cortex-a9-global-timer";
  72                 reg = <0xf0000200 0x100>;
  73                 interrupts = <GIC_PPI 11
  74                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
  75                 clocks = <&cpg_clocks R8A7779_CLK_ZS>;
  76         };
  77
  78         timer@f0000600 {
  79                 compatible = "arm,cortex-a9-twd-timer";
  80                 reg = <0xf0000600 0x20>;
  81                 interrupts = <GIC_PPI 13
  82                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
  83                 clocks = <&cpg_clocks R8A7779_CLK_ZS>;
  84         };
  85
  86         gpio0: gpio@ffc40000 {
  87                 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
  88                 reg = <0xffc40000 0x2c>;
  89                 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
  90                 #gpio-cells = <2>;
  91                 gpio-controller;
  92                 gpio-ranges = <&pfc 0 0 32>;
  93                 #interrupt-cells = <2>;
  94                 interrupt-controller;
  95         };
  96
  97         gpio1: gpio@ffc41000 {
  98                 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
  99                 reg = <0xffc41000 0x2c>;
 100                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
 101                 #gpio-cells = <2>;
 102                 gpio-controller;
 103                 gpio-ranges = <&pfc 0 32 32>;
 104                 #interrupt-cells = <2>;
 105                 interrupt-controller;
 106         };
 107
 108         gpio2: gpio@ffc42000 {
 109                 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
 110                 reg = <0xffc42000 0x2c>;
 111                 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 112                 #gpio-cells = <2>;
 113                 gpio-controller;
 114                 gpio-ranges = <&pfc 0 64 32>;
 115                 #interrupt-cells = <2>;
 116                 interrupt-controller;
 117         };
 118
 119         gpio3: gpio@ffc43000 {
 120                 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
 121                 reg = <0xffc43000 0x2c>;
 122                 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 123                 #gpio-cells = <2>;
 124                 gpio-controller;
 125                 gpio-ranges = <&pfc 0 96 32>;
 126                 #interrupt-cells = <2>;
 127                 interrupt-controller;
 128         };
 129
 130         gpio4: gpio@ffc44000 {
 131                 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
 132                 reg = <0xffc44000 0x2c>;
 133                 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
 134                 #gpio-cells = <2>;
 135                 gpio-controller;
 136                 gpio-ranges = <&pfc 0 128 32>;
 137                 #interrupt-cells = <2>;
 138                 interrupt-controller;
 139         };
 140
 141         gpio5: gpio@ffc45000 {
 142                 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
 143                 reg = <0xffc45000 0x2c>;
 144                 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
 145                 #gpio-cells = <2>;
 146                 gpio-controller;
 147                 gpio-ranges = <&pfc 0 160 32>;
 148                 #interrupt-cells = <2>;
 149                 interrupt-controller;
 150         };
 151
 152         gpio6: gpio@ffc46000 {
 153                 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
 154                 reg = <0xffc46000 0x2c>;
 155                 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
 156                 #gpio-cells = <2>;
 157                 gpio-controller;
 158                 gpio-ranges = <&pfc 0 192 9>;
 159                 #interrupt-cells = <2>;
 160                 interrupt-controller;
 161         };
 162
 163         irqpin0: interrupt-controller@fe78001c {
 164                 compatible = "renesas,intc-irqpin-r8a7779", "renesas,intc-irqpin";
 165                 #interrupt-cells = <2>;
 166                 status = "disabled";
 167                 interrupt-controller;
 168                 reg = <0xfe78001c 4>,
 169                         <0xfe780010 4>,
 170                         <0xfe780024 4>,
 171                         <0xfe780044 4>,
 172                         <0xfe780064 4>,
 173                         <0xfe780000 4>;
 174                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH
 175                               GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH
 176                               GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH
 177                               GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 178                 sense-bitfield-width = <2>;
 179         };
 180
 181         i2c0: i2c@ffc70000 {
 182                 #address-cells = <1>;
 183                 #size-cells = <0>;
 184                 compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c";
 185                 reg = <0xffc70000 0x1000>;
 186                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 187                 clocks = <&mstp0_clks R8A7779_CLK_I2C0>;
 188                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 189                 status = "disabled";
 190         };
 191
 192         i2c1: i2c@ffc71000 {
 193                 #address-cells = <1>;
 194                 #size-cells = <0>;
 195                 compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c";
 196                 reg = <0xffc71000 0x1000>;
 197                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 198                 clocks = <&mstp0_clks R8A7779_CLK_I2C1>;
 199                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 200                 status = "disabled";
 201         };
 202
 203         i2c2: i2c@ffc72000 {
 204                 #address-cells = <1>;
 205                 #size-cells = <0>;
 206                 compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c";
 207                 reg = <0xffc72000 0x1000>;
 208                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 209                 clocks = <&mstp0_clks R8A7779_CLK_I2C2>;
 210                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 211                 status = "disabled";
 212         };
 213
 214         i2c3: i2c@ffc73000 {
 215                 #address-cells = <1>;
 216                 #size-cells = <0>;
 217                 compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c";
 218                 reg = <0xffc73000 0x1000>;
 219                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 220                 clocks = <&mstp0_clks R8A7779_CLK_I2C3>;
 221                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 222                 status = "disabled";
 223         };
 224
 225         scif0: serial@ffe40000 {
 226                 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
 227                              "renesas,scif";
 228                 reg = <0xffe40000 0x100>;
 229                 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 230                 clocks = <&mstp0_clks R8A7779_CLK_SCIF0>,
 231                          <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
 232                 clock-names = "fck", "brg_int", "scif_clk";
 233                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 234                 status = "disabled";
 235         };
 236
 237         scif1: serial@ffe41000 {
 238                 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
 239                              "renesas,scif";
 240                 reg = <0xffe41000 0x100>;
 241                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 242                 clocks = <&mstp0_clks R8A7779_CLK_SCIF1>,
 243                          <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
 244                 clock-names = "fck", "brg_int", "scif_clk";
 245                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 246                 status = "disabled";
 247         };
 248
 249         scif2: serial@ffe42000 {
 250                 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
 251                              "renesas,scif";
 252                 reg = <0xffe42000 0x100>;
 253                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 254                 clocks = <&mstp0_clks R8A7779_CLK_SCIF2>,
 255                          <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
 256                 clock-names = "fck", "brg_int", "scif_clk";
 257                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 258                 status = "disabled";
 259         };
 260
 261         scif3: serial@ffe43000 {
 262                 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
 263                              "renesas,scif";
 264                 reg = <0xffe43000 0x100>;
 265                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 266                 clocks = <&mstp0_clks R8A7779_CLK_SCIF3>,
 267                          <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
 268                 clock-names = "fck", "brg_int", "scif_clk";
 269                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 270                 status = "disabled";
 271         };
 272
 273         scif4: serial@ffe44000 {
 274                 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
 275                              "renesas,scif";
 276                 reg = <0xffe44000 0x100>;
 277                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 278                 clocks = <&mstp0_clks R8A7779_CLK_SCIF4>,
 279                          <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
 280                 clock-names = "fck", "brg_int", "scif_clk";
 281                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 282                 status = "disabled";
 283         };
 284
 285         scif5: serial@ffe45000 {
 286                 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
 287                              "renesas,scif";
 288                 reg = <0xffe45000 0x100>;
 289                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 290                 clocks = <&mstp0_clks R8A7779_CLK_SCIF5>,
 291                          <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
 292                 clock-names = "fck", "brg_int", "scif_clk";
 293                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 294                 status = "disabled";
 295         };
 296
 297         pfc: pin-controller@fffc0000 {
 298                 compatible = "renesas,pfc-r8a7779";
 299                 reg = <0xfffc0000 0x23c>;
 300         };
 301
 302         thermal@ffc48000 {
 303                 compatible = "renesas,thermal-r8a7779", "renesas,rcar-thermal";
 304                 reg = <0xffc48000 0x38>;
 305         };
 306
 307         tmu0: timer@ffd80000 {
 308                 compatible = "renesas,tmu-r8a7779", "renesas,tmu";
 309                 reg = <0xffd80000 0x30>;
 310                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
 311                              <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 312                              <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 313                 clocks = <&mstp0_clks R8A7779_CLK_TMU0>;
 314                 clock-names = "fck";
 315                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 316
 317                 #renesas,channels = <3>;
 318
 319                 status = "disabled";
 320         };
 321
 322         tmu1: timer@ffd81000 {
 323                 compatible = "renesas,tmu-r8a7779", "renesas,tmu";
 324                 reg = <0xffd81000 0x30>;
 325                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
 326                              <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
 327                              <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 328                 clocks = <&mstp0_clks R8A7779_CLK_TMU1>;
 329                 clock-names = "fck";
 330                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 331
 332                 #renesas,channels = <3>;
 333
 334                 status = "disabled";
 335         };
 336
 337         tmu2: timer@ffd82000 {
 338                 compatible = "renesas,tmu-r8a7779", "renesas,tmu";
 339                 reg = <0xffd82000 0x30>;
 340                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 341                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 342                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 343                 clocks = <&mstp0_clks R8A7779_CLK_TMU2>;
 344                 clock-names = "fck";
 345                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 346
 347                 #renesas,channels = <3>;
 348
 349                 status = "disabled";
 350         };
 351
 352         sata: sata@fc600000 {
 353                 compatible = "renesas,sata-r8a7779", "renesas,rcar-sata";
 354                 reg = <0xfc600000 0x2000>;
 355                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 356                 clocks = <&mstp1_clks R8A7779_CLK_SATA>;
 357                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 358                 status = "disabled";
 359         };
 360
 361         sdhi0: sd@ffe4c000 {
 362                 compatible = "renesas,sdhi-r8a7779";
 363                 reg = <0xffe4c000 0x100>;
 364                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 365                 clocks = <&mstp3_clks R8A7779_CLK_SDHI0>;
 366                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 367                 status = "disabled";
 368         };
 369
 370         sdhi1: sd@ffe4d000 {
 371                 compatible = "renesas,sdhi-r8a7779";
 372                 reg = <0xffe4d000 0x100>;
 373                 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 374                 clocks = <&mstp3_clks R8A7779_CLK_SDHI1>;
 375                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 376                 status = "disabled";
 377         };
 378
 379         sdhi2: sd@ffe4e000 {
 380                 compatible = "renesas,sdhi-r8a7779";
 381                 reg = <0xffe4e000 0x100>;
 382                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 383                 clocks = <&mstp3_clks R8A7779_CLK_SDHI2>;
 384                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 385                 status = "disabled";
 386         };
 387
 388         sdhi3: sd@ffe4f000 {
 389                 compatible = "renesas,sdhi-r8a7779";
 390                 reg = <0xffe4f000 0x100>;
 391                 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 392                 clocks = <&mstp3_clks R8A7779_CLK_SDHI3>;
 393                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 394                 status = "disabled";
 395         };
 396
 397         hspi0: spi@fffc7000 {
 398                 compatible = "renesas,hspi-r8a7779", "renesas,hspi";
 399                 reg = <0xfffc7000 0x18>;
 400                 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 401                 #address-cells = <1>;
 402                 #size-cells = <0>;
 403                 clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
 404                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 405                 status = "disabled";
 406         };
 407
 408         hspi1: spi@fffc8000 {
 409                 compatible = "renesas,hspi-r8a7779", "renesas,hspi";
 410                 reg = <0xfffc8000 0x18>;
 411                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 412                 #address-cells = <1>;
 413                 #size-cells = <0>;
 414                 clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
 415                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 416                 status = "disabled";
 417         };
 418
 419         hspi2: spi@fffc6000 {
 420                 compatible = "renesas,hspi-r8a7779", "renesas,hspi";
 421                 reg = <0xfffc6000 0x18>;
 422                 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 423                 #address-cells = <1>;
 424                 #size-cells = <0>;
 425                 clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
 426                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 427                 status = "disabled";
 428         };
 429
 430         du: display@fff80000 {
 431                 compatible = "renesas,du-r8a7779";
 432                 reg = <0xfff80000 0x40000>;
 433                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 434                 clocks = <&mstp1_clks R8A7779_CLK_DU>;
 435                 clock-names = "du.0";
 436                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 437                 status = "disabled";
 438
 439                 ports {
 440                         #address-cells = <1>;
 441                         #size-cells = <0>;
 442
 443                         port@0 {
 444                                 reg = <0>;
 445                                 du_out_rgb0: endpoint {
 446                                 };
 447                         };
 448                         port@1 {
 449                                 reg = <1>;
 450                                 du_out_rgb1: endpoint {
 451                                 };
 452                         };
 453                 };
 454         };
 455
 456         clocks {
 457                 #address-cells = <1>;
 458                 #size-cells = <1>;
 459                 ranges;
 460
 461                 /* External root clock */
 462                 extal_clk: extal {
 463                         compatible = "fixed-clock";
 464                         #clock-cells = <0>;
 465                         /* This value must be overriden by the board. */
 466                         clock-frequency = <0>;
 467                 };
 468
 469                 /* External SCIF clock */
 470                 scif_clk: scif {
 471                         compatible = "fixed-clock";
 472                         #clock-cells = <0>;
 473                         /* This value must be overridden by the board. */
 474                         clock-frequency = <0>;
 475                 };
 476
 477                 /* Special CPG clocks */
 478                 cpg_clocks: clocks@ffc80000 {
 479                         compatible = "renesas,r8a7779-cpg-clocks";
 480                         reg = <0xffc80000 0x30>;
 481                         clocks = <&extal_clk>;
 482                         #clock-cells = <1>;
 483                         clock-output-names = "plla", "z", "zs", "s",
 484                                              "s1", "p", "b", "out";
 485                         #power-domain-cells = <0>;
 486                 };
 487
 488                 /* Fixed factor clocks */
 489                 i_clk: i {
 490                         compatible = "fixed-factor-clock";
 491                         clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
 492                         #clock-cells = <0>;
 493                         clock-div = <2>;
 494                         clock-mult = <1>;
 495                 };
 496                 s3_clk: s3 {
 497                         compatible = "fixed-factor-clock";
 498                         clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
 499                         #clock-cells = <0>;
 500                         clock-div = <8>;
 501                         clock-mult = <1>;
 502                 };
 503                 s4_clk: s4 {
 504                         compatible = "fixed-factor-clock";
 505                         clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
 506                         #clock-cells = <0>;
 507                         clock-div = <16>;
 508                         clock-mult = <1>;
 509                 };
 510                 g_clk: g {
 511                         compatible = "fixed-factor-clock";
 512                         clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
 513                         #clock-cells = <0>;
 514                         clock-div = <24>;
 515                         clock-mult = <1>;
 516                 };
 517
 518                 /* Gate clocks */
 519                 mstp0_clks: clocks@ffc80030 {
 520                         compatible = "renesas,r8a7779-mstp-clocks",
 521                                      "renesas,cpg-mstp-clocks";
 522                         reg = <0xffc80030 4>;
 523                         clocks = <&cpg_clocks R8A7779_CLK_S>,
 524                                  <&cpg_clocks R8A7779_CLK_P>,
 525                                  <&cpg_clocks R8A7779_CLK_P>,
 526                                  <&cpg_clocks R8A7779_CLK_P>,
 527                                  <&cpg_clocks R8A7779_CLK_S>,
 528                                  <&cpg_clocks R8A7779_CLK_S>,
 529                                  <&cpg_clocks R8A7779_CLK_P>,
 530                                  <&cpg_clocks R8A7779_CLK_P>,
 531                                  <&cpg_clocks R8A7779_CLK_P>,
 532                                  <&cpg_clocks R8A7779_CLK_P>,
 533                                  <&cpg_clocks R8A7779_CLK_P>,
 534                                  <&cpg_clocks R8A7779_CLK_P>,
 535                                  <&cpg_clocks R8A7779_CLK_P>,
 536                                  <&cpg_clocks R8A7779_CLK_P>,
 537                                  <&cpg_clocks R8A7779_CLK_P>,
 538                                  <&cpg_clocks R8A7779_CLK_P>;
 539                         #clock-cells = <1>;
 540                         clock-indices = <
 541                                 R8A7779_CLK_HSPI R8A7779_CLK_TMU2
 542                                 R8A7779_CLK_TMU1 R8A7779_CLK_TMU0
 543                                 R8A7779_CLK_HSCIF1 R8A7779_CLK_HSCIF0
 544                                 R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4
 545                                 R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2
 546                                 R8A7779_CLK_SCIF1 R8A7779_CLK_SCIF0
 547                                 R8A7779_CLK_I2C3 R8A7779_CLK_I2C2
 548                                 R8A7779_CLK_I2C1 R8A7779_CLK_I2C0
 549                         >;
 550                         clock-output-names =
 551                                 "hspi", "tmu2", "tmu1", "tmu0", "hscif1",
 552                                 "hscif0", "scif5", "scif4", "scif3", "scif2",
 553                                 "scif1", "scif0", "i2c3", "i2c2", "i2c1",
 554                                 "i2c0";
 555                 };
 556                 mstp1_clks: clocks@ffc80034 {
 557                         compatible = "renesas,r8a7779-mstp-clocks",
 558                                      "renesas,cpg-mstp-clocks";
 559                         reg = <0xffc80034 4>, <0xffc80044 4>;
 560                         clocks = <&cpg_clocks R8A7779_CLK_P>,
 561                                  <&cpg_clocks R8A7779_CLK_P>,
 562                                  <&cpg_clocks R8A7779_CLK_S>,
 563                                  <&cpg_clocks R8A7779_CLK_S>,
 564                                  <&cpg_clocks R8A7779_CLK_S>,
 565                                  <&cpg_clocks R8A7779_CLK_S>,
 566                                  <&cpg_clocks R8A7779_CLK_P>,
 567                                  <&cpg_clocks R8A7779_CLK_P>,
 568                                  <&cpg_clocks R8A7779_CLK_P>,
 569                                  <&cpg_clocks R8A7779_CLK_S>;
 570                         #clock-cells = <1>;
 571                         clock-indices = <
 572                                 R8A7779_CLK_USB01 R8A7779_CLK_USB2
 573                                 R8A7779_CLK_DU R8A7779_CLK_VIN2
 574                                 R8A7779_CLK_VIN1 R8A7779_CLK_VIN0
 575                                 R8A7779_CLK_ETHER R8A7779_CLK_SATA
 576                                 R8A7779_CLK_PCIE R8A7779_CLK_VIN3
 577                         >;
 578                         clock-output-names =
 579                                 "usb01", "usb2",
 580                                 "du", "vin2",
 581                                 "vin1", "vin0",
 582                                 "ether", "sata",
 583                                 "pcie", "vin3";
 584                 };
 585                 mstp3_clks: clocks@ffc8003c {
 586                         compatible = "renesas,r8a7779-mstp-clocks",
 587                                      "renesas,cpg-mstp-clocks";
 588                         reg = <0xffc8003c 4>;
 589                         clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>,
 590                                  <&s4_clk>, <&s4_clk>;
 591                         #clock-cells = <1>;
 592                         clock-indices = <
 593                                 R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2
 594                                 R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0
 595                                 R8A7779_CLK_MMC1 R8A7779_CLK_MMC0
 596                         >;
 597                         clock-output-names =
 598                                 "sdhi3", "sdhi2", "sdhi1", "sdhi0",
 599                                 "mmc1", "mmc0";
 600                 };
 601         };
 602
 603         prr: chipid@ff000044 {
 604                 compatible = "renesas,prr";
 605                 reg = <0xff000044 4>;
 606         };
 607
 608         rst: reset-controller@ffcc0000 {
 609                 compatible = "renesas,r8a7779-reset-wdt";
 610                 reg = <0xffcc0000 0x48>;
 611         };
 612
 613         sysc: system-controller@ffd85000 {
 614                 compatible = "renesas,r8a7779-sysc";
 615                 reg = <0xffd85000 0x0200>;
 616                 #power-domain-cells = <1>;
 617         };
 618 };