arch/arm/boot/dts/r8a7778.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for Renesas r8a7778
   4  *
   5  * Copyright (C) 2013  Renesas Solutions Corp.
   6  * Copyright (C) 2013  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
   7  *
   8  * based on r8a7779
   9  *
  10  * Copyright (C) 2013 Renesas Solutions Corp.
  11  * Copyright (C) 2013 Simon Horman
  12  */
  13
  14 #include <dt-bindings/clock/r8a7778-clock.h>
  15 #include <dt-bindings/interrupt-controller/arm-gic.h>
  16 #include <dt-bindings/interrupt-controller/irq.h>
  17
  18 / {
  19         compatible = "renesas,r8a7778";
  20         interrupt-parent = <&gic>;
  21         #address-cells = <1>;
  22         #size-cells = <1>;
  23
  24         cpus {
  25                 #address-cells = <1>;
  26                 #size-cells = <0>;
  27
  28                 cpu@0 {
  29                         device_type = "cpu";
  30                         compatible = "arm,cortex-a9";
  31                         reg = <0>;
  32                         clock-frequency = <800000000>;
  33                         clocks = <&z_clk>;
  34                 };
  35         };
  36
  37         aliases {
  38                 spi0 = &hspi0;
  39                 spi1 = &hspi1;
  40                 spi2 = &hspi2;
  41         };
  42
  43         bsc: bus@1c000000 {
  44                 compatible = "simple-bus";
  45                 #address-cells = <1>;
  46                 #size-cells = <1>;
  47                 ranges = <0 0 0x1c000000>;
  48         };
  49
  50         ether: ethernet@fde00000 {
  51                 compatible = "renesas,ether-r8a7778",
  52                              "renesas,rcar-gen1-ether";
  53                 reg = <0xfde00000 0x400>;
  54                 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
  55                 clocks = <&mstp1_clks R8A7778_CLK_ETHER>;
  56                 power-domains = <&cpg_clocks>;
  57                 phy-mode = "rmii";
  58                 #address-cells = <1>;
  59                 #size-cells = <0>;
  60                 status = "disabled";
  61         };
  62
  63         gic: interrupt-controller@fe438000 {
  64                 compatible = "arm,pl390";
  65                 #interrupt-cells = <3>;
  66                 interrupt-controller;
  67                 reg = <0xfe438000 0x1000>,
  68                       <0xfe430000 0x100>;
  69         };
  70
  71         /* irqpin: IRQ0 - IRQ3 */
  72         irqpin: interrupt-controller@fe78001c {
  73                 compatible = "renesas,intc-irqpin-r8a7778", "renesas,intc-irqpin";
  74                 #interrupt-cells = <2>;
  75                 interrupt-controller;
  76                 status = "disabled"; /* default off */
  77                 reg =   <0xfe78001c 4>,
  78                         <0xfe780010 4>,
  79                         <0xfe780024 4>,
  80                         <0xfe780044 4>,
  81                         <0xfe780064 4>;
  82                 interrupts =   <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH
  83                                 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH
  84                                 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH
  85                                 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
  86                 sense-bitfield-width = <2>;
  87         };
  88
  89         gpio0: gpio@ffc40000 {
  90                 compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio";
  91                 reg = <0xffc40000 0x2c>;
  92                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
  93                 #gpio-cells = <2>;
  94                 gpio-controller;
  95                 gpio-ranges = <&pfc 0 0 32>;
  96                 #interrupt-cells = <2>;
  97                 interrupt-controller;
  98         };
  99
 100         gpio1: gpio@ffc41000 {
 101                 compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio";
 102                 reg = <0xffc41000 0x2c>;
 103                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 104                 #gpio-cells = <2>;
 105                 gpio-controller;
 106                 gpio-ranges = <&pfc 0 32 32>;
 107                 #interrupt-cells = <2>;
 108                 interrupt-controller;
 109         };
 110
 111         gpio2: gpio@ffc42000 {
 112                 compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio";
 113                 reg = <0xffc42000 0x2c>;
 114                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 115                 #gpio-cells = <2>;
 116                 gpio-controller;
 117                 gpio-ranges = <&pfc 0 64 32>;
 118                 #interrupt-cells = <2>;
 119                 interrupt-controller;
 120         };
 121
 122         gpio3: gpio@ffc43000 {
 123                 compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio";
 124                 reg = <0xffc43000 0x2c>;
 125                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 126                 #gpio-cells = <2>;
 127                 gpio-controller;
 128                 gpio-ranges = <&pfc 0 96 32>;
 129                 #interrupt-cells = <2>;
 130                 interrupt-controller;
 131         };
 132
 133         gpio4: gpio@ffc44000 {
 134                 compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio";
 135                 reg = <0xffc44000 0x2c>;
 136                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 137                 #gpio-cells = <2>;
 138                 gpio-controller;
 139                 gpio-ranges = <&pfc 0 128 27>;
 140                 #interrupt-cells = <2>;
 141                 interrupt-controller;
 142         };
 143
 144         pfc: pin-controller@fffc0000 {
 145                 compatible = "renesas,pfc-r8a7778";
 146                 reg = <0xfffc0000 0x118>;
 147         };
 148
 149         i2c0: i2c@ffc70000 {
 150                 #address-cells = <1>;
 151                 #size-cells = <0>;
 152                 compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c";
 153                 reg = <0xffc70000 0x1000>;
 154                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 155                 clocks = <&mstp0_clks R8A7778_CLK_I2C0>;
 156                 power-domains = <&cpg_clocks>;
 157                 status = "disabled";
 158         };
 159
 160         i2c1: i2c@ffc71000 {
 161                 #address-cells = <1>;
 162                 #size-cells = <0>;
 163                 compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c";
 164                 reg = <0xffc71000 0x1000>;
 165                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 166                 clocks = <&mstp0_clks R8A7778_CLK_I2C1>;
 167                 power-domains = <&cpg_clocks>;
 168                 status = "disabled";
 169         };
 170
 171         i2c2: i2c@ffc72000 {
 172                 #address-cells = <1>;
 173                 #size-cells = <0>;
 174                 compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c";
 175                 reg = <0xffc72000 0x1000>;
 176                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 177                 clocks = <&mstp0_clks R8A7778_CLK_I2C2>;
 178                 power-domains = <&cpg_clocks>;
 179                 status = "disabled";
 180         };
 181
 182         i2c3: i2c@ffc73000 {
 183                 #address-cells = <1>;
 184                 #size-cells = <0>;
 185                 compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c";
 186                 reg = <0xffc73000 0x1000>;
 187                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 188                 clocks = <&mstp0_clks R8A7778_CLK_I2C3>;
 189                 power-domains = <&cpg_clocks>;
 190                 status = "disabled";
 191         };
 192
 193         tmu0: timer@ffd80000 {
 194                 compatible = "renesas,tmu-r8a7778", "renesas,tmu";
 195                 reg = <0xffd80000 0x30>;
 196                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
 197                              <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 198                              <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 199                 clocks = <&mstp0_clks R8A7778_CLK_TMU0>;
 200                 clock-names = "fck";
 201                 power-domains = <&cpg_clocks>;
 202
 203                 #renesas,channels = <3>;
 204
 205                 status = "disabled";
 206         };
 207
 208         tmu1: timer@ffd81000 {
 209                 compatible = "renesas,tmu-r8a7778", "renesas,tmu";
 210                 reg = <0xffd81000 0x30>;
 211                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
 212                              <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
 213                              <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 214                 clocks = <&mstp0_clks R8A7778_CLK_TMU1>;
 215                 clock-names = "fck";
 216                 power-domains = <&cpg_clocks>;
 217
 218                 #renesas,channels = <3>;
 219
 220                 status = "disabled";
 221         };
 222
 223         tmu2: timer@ffd82000 {
 224                 compatible = "renesas,tmu-r8a7778", "renesas,tmu";
 225                 reg = <0xffd82000 0x30>;
 226                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 227                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 228                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 229                 clocks = <&mstp0_clks R8A7778_CLK_TMU2>;
 230                 clock-names = "fck";
 231                 power-domains = <&cpg_clocks>;
 232
 233                 #renesas,channels = <3>;
 234
 235                 status = "disabled";
 236         };
 237
 238         rcar_sound: sound@ffd90000 {
 239                 /*
 240                  * #sound-dai-cells is required
 241                  *
 242                  * Single DAI : #sound-dai-cells = <0>;         <&rcar_sound>;
 243                  * Multi  DAI : #sound-dai-cells = <1>;         <&rcar_sound N>;
 244                  */
 245                 compatible = "renesas,rcar_sound-r8a7778", "renesas,rcar_sound-gen1";
 246                 reg =   <0xffd90000 0x1000>,    /* SRU */
 247                         <0xffd91000 0x240>,     /* SSI */
 248                         <0xfffe0000 0x24>;      /* ADG */
 249                 clocks = <&mstp3_clks R8A7778_CLK_SSI8>,
 250                         <&mstp3_clks R8A7778_CLK_SSI7>,
 251                         <&mstp3_clks R8A7778_CLK_SSI6>,
 252                         <&mstp3_clks R8A7778_CLK_SSI5>,
 253                         <&mstp3_clks R8A7778_CLK_SSI4>,
 254                         <&mstp0_clks R8A7778_CLK_SSI3>,
 255                         <&mstp0_clks R8A7778_CLK_SSI2>,
 256                         <&mstp0_clks R8A7778_CLK_SSI1>,
 257                         <&mstp0_clks R8A7778_CLK_SSI0>,
 258                         <&mstp5_clks R8A7778_CLK_SRU_SRC8>,
 259                         <&mstp5_clks R8A7778_CLK_SRU_SRC7>,
 260                         <&mstp5_clks R8A7778_CLK_SRU_SRC6>,
 261                         <&mstp5_clks R8A7778_CLK_SRU_SRC5>,
 262                         <&mstp5_clks R8A7778_CLK_SRU_SRC4>,
 263                         <&mstp5_clks R8A7778_CLK_SRU_SRC3>,
 264                         <&mstp5_clks R8A7778_CLK_SRU_SRC2>,
 265                         <&mstp5_clks R8A7778_CLK_SRU_SRC1>,
 266                         <&mstp5_clks R8A7778_CLK_SRU_SRC0>,
 267                         <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
 268                         <&cpg_clocks R8A7778_CLK_S1>;
 269                 clock-names = "ssi.8", "ssi.7", "ssi.6", "ssi.5", "ssi.4",
 270                         "ssi.3", "ssi.2", "ssi.1", "ssi.0",
 271                         "src.8", "src.7", "src.6", "src.5", "src.4",
 272                         "src.3", "src.2", "src.1", "src.0",
 273                         "clk_a", "clk_b", "clk_c", "clk_i";
 274
 275                 status = "disabled";
 276
 277                 rcar_sound,src {
 278                         src3: src-3 { };
 279                         src4: src-4 { };
 280                         src5: src-5 { };
 281                         src6: src-6 { };
 282                         src7: src-7 { };
 283                         src8: src-8 { };
 284                         src9: src-9 { };
 285                 };
 286
 287                 rcar_sound,ssi {
 288                         ssi3: ssi-3 { interrupts = <GIC_SPI 0x85 IRQ_TYPE_LEVEL_HIGH>; };
 289                         ssi4: ssi-4 { interrupts = <GIC_SPI 0x85 IRQ_TYPE_LEVEL_HIGH>; };
 290                         ssi5: ssi-5 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
 291                         ssi6: ssi-6 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
 292                         ssi7: ssi-7 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
 293                         ssi8: ssi-8 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
 294                         ssi9: ssi-9 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
 295                 };
 296         };
 297
 298         scif0: serial@ffe40000 {
 299                 compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
 300                              "renesas,scif";
 301                 reg = <0xffe40000 0x100>;
 302                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 303                 clocks = <&mstp0_clks R8A7778_CLK_SCIF0>,
 304                          <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
 305                 clock-names = "fck", "brg_int", "scif_clk";
 306                 power-domains = <&cpg_clocks>;
 307                 status = "disabled";
 308         };
 309
 310         scif1: serial@ffe41000 {
 311                 compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
 312                              "renesas,scif";
 313                 reg = <0xffe41000 0x100>;
 314                 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 315                 clocks = <&mstp0_clks R8A7778_CLK_SCIF1>,
 316                          <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
 317                 clock-names = "fck", "brg_int", "scif_clk";
 318                 power-domains = <&cpg_clocks>;
 319                 status = "disabled";
 320         };
 321
 322         scif2: serial@ffe42000 {
 323                 compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
 324                              "renesas,scif";
 325                 reg = <0xffe42000 0x100>;
 326                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 327                 clocks = <&mstp0_clks R8A7778_CLK_SCIF2>,
 328                          <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
 329                 clock-names = "fck", "brg_int", "scif_clk";
 330                 power-domains = <&cpg_clocks>;
 331                 status = "disabled";
 332         };
 333
 334         scif3: serial@ffe43000 {
 335                 compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
 336                              "renesas,scif";
 337                 reg = <0xffe43000 0x100>;
 338                 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 339                 clocks = <&mstp0_clks R8A7778_CLK_SCIF3>,
 340                          <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
 341                 clock-names = "fck", "brg_int", "scif_clk";
 342                 power-domains = <&cpg_clocks>;
 343                 status = "disabled";
 344         };
 345
 346         scif4: serial@ffe44000 {
 347                 compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
 348                              "renesas,scif";
 349                 reg = <0xffe44000 0x100>;
 350                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 351                 clocks = <&mstp0_clks R8A7778_CLK_SCIF4>,
 352                          <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
 353                 clock-names = "fck", "brg_int", "scif_clk";
 354                 power-domains = <&cpg_clocks>;
 355                 status = "disabled";
 356         };
 357
 358         scif5: serial@ffe45000 {
 359                 compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
 360                              "renesas,scif";
 361                 reg = <0xffe45000 0x100>;
 362                 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 363                 clocks = <&mstp0_clks R8A7778_CLK_SCIF5>,
 364                          <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
 365                 clock-names = "fck", "brg_int", "scif_clk";
 366                 power-domains = <&cpg_clocks>;
 367                 status = "disabled";
 368         };
 369
 370         mmcif: mmc@ffe4e000 {
 371                 compatible = "renesas,mmcif-r8a7778", "renesas,sh-mmcif";
 372                 reg = <0xffe4e000 0x100>;
 373                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 374                 clocks = <&mstp3_clks R8A7778_CLK_MMC>;
 375                 power-domains = <&cpg_clocks>;
 376                 status = "disabled";
 377         };
 378
 379         sdhi0: sd@ffe4c000 {
 380                 compatible = "renesas,sdhi-r8a7778",
 381                              "renesas,rcar-gen1-sdhi";
 382                 reg = <0xffe4c000 0x100>;
 383                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 384                 clocks = <&mstp3_clks R8A7778_CLK_SDHI0>;
 385                 power-domains = <&cpg_clocks>;
 386                 status = "disabled";
 387         };
 388
 389         sdhi1: sd@ffe4d000 {
 390                 compatible = "renesas,sdhi-r8a7778",
 391                              "renesas,rcar-gen1-sdhi";
 392                 reg = <0xffe4d000 0x100>;
 393                 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 394                 clocks = <&mstp3_clks R8A7778_CLK_SDHI1>;
 395                 power-domains = <&cpg_clocks>;
 396                 status = "disabled";
 397         };
 398
 399         sdhi2: sd@ffe4f000 {
 400                 compatible = "renesas,sdhi-r8a7778",
 401                              "renesas,rcar-gen1-sdhi";
 402                 reg = <0xffe4f000 0x100>;
 403                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 404                 clocks = <&mstp3_clks R8A7778_CLK_SDHI2>;
 405                 power-domains = <&cpg_clocks>;
 406                 status = "disabled";
 407         };
 408
 409         hspi0: spi@fffc7000 {
 410                 compatible = "renesas,hspi-r8a7778", "renesas,hspi";
 411                 reg = <0xfffc7000 0x18>;
 412                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 413                 clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
 414                 power-domains = <&cpg_clocks>;
 415                 #address-cells = <1>;
 416                 #size-cells = <0>;
 417                 status = "disabled";
 418         };
 419
 420         hspi1: spi@fffc8000 {
 421                 compatible = "renesas,hspi-r8a7778", "renesas,hspi";
 422                 reg = <0xfffc8000 0x18>;
 423                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 424                 clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
 425                 power-domains = <&cpg_clocks>;
 426                 #address-cells = <1>;
 427                 #size-cells = <0>;
 428                 status = "disabled";
 429         };
 430
 431         hspi2: spi@fffc6000 {
 432                 compatible = "renesas,hspi-r8a7778", "renesas,hspi";
 433                 reg = <0xfffc6000 0x18>;
 434                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 435                 clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
 436                 power-domains = <&cpg_clocks>;
 437                 #address-cells = <1>;
 438                 #size-cells = <0>;
 439                 status = "disabled";
 440         };
 441
 442         clocks {
 443                 #address-cells = <1>;
 444                 #size-cells = <1>;
 445                 ranges;
 446
 447                 /* External input clock */
 448                 extal_clk: extal {
 449                         compatible = "fixed-clock";
 450                         #clock-cells = <0>;
 451                         clock-frequency = <0>;
 452                 };
 453
 454                 /* External SCIF clock */
 455                 scif_clk: scif {
 456                         compatible = "fixed-clock";
 457                         #clock-cells = <0>;
 458                         /* This value must be overridden by the board. */
 459                         clock-frequency = <0>;
 460                 };
 461
 462                 /* Special CPG clocks */
 463                 cpg_clocks: cpg_clocks@ffc80000 {
 464                         compatible = "renesas,r8a7778-cpg-clocks";
 465                         reg = <0xffc80000 0x80>;
 466                         #clock-cells = <1>;
 467                         clocks = <&extal_clk>;
 468                         clock-output-names = "plla", "pllb", "b",
 469                                              "out", "p", "s", "s1";
 470                         #power-domain-cells = <0>;
 471                 };
 472
 473                 /* Audio clocks; frequencies are set by boards if applicable. */
 474                 audio_clk_a: audio_clk_a {
 475                         compatible = "fixed-clock";
 476                         #clock-cells = <0>;
 477                 };
 478                 audio_clk_b: audio_clk_b {
 479                         compatible = "fixed-clock";
 480                         #clock-cells = <0>;
 481                 };
 482                 audio_clk_c: audio_clk_c {
 483                         compatible = "fixed-clock";
 484                         #clock-cells = <0>;
 485                 };
 486
 487                 /* Fixed ratio clocks */
 488                 g_clk: g {
 489                         compatible = "fixed-factor-clock";
 490                         clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
 491                         #clock-cells = <0>;
 492                         clock-div = <12>;
 493                         clock-mult = <1>;
 494                 };
 495                 i_clk: i {
 496                         compatible = "fixed-factor-clock";
 497                         clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
 498                         #clock-cells = <0>;
 499                         clock-div = <1>;
 500                         clock-mult = <1>;
 501                 };
 502                 s3_clk: s3 {
 503                         compatible = "fixed-factor-clock";
 504                         clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
 505                         #clock-cells = <0>;
 506                         clock-div = <4>;
 507                         clock-mult = <1>;
 508                 };
 509                 s4_clk: s4 {
 510                         compatible = "fixed-factor-clock";
 511                         clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
 512                         #clock-cells = <0>;
 513                         clock-div = <8>;
 514                         clock-mult = <1>;
 515                 };
 516                 z_clk: z {
 517                         compatible = "fixed-factor-clock";
 518                         clocks = <&cpg_clocks R8A7778_CLK_PLLB>;
 519                         #clock-cells = <0>;
 520                         clock-div = <1>;
 521                         clock-mult = <1>;
 522                 };
 523
 524                 /* Gate clocks */
 525                 mstp0_clks: mstp0_clks@ffc80030 {
 526                         compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
 527                         reg = <0xffc80030 4>;
 528                         clocks = <&cpg_clocks R8A7778_CLK_P>,
 529                                  <&cpg_clocks R8A7778_CLK_P>,
 530                                  <&cpg_clocks R8A7778_CLK_P>,
 531                                  <&cpg_clocks R8A7778_CLK_P>,
 532                                  <&cpg_clocks R8A7778_CLK_P>,
 533                                  <&cpg_clocks R8A7778_CLK_P>,
 534                                  <&cpg_clocks R8A7778_CLK_P>,
 535                                  <&cpg_clocks R8A7778_CLK_P>,
 536                                  <&cpg_clocks R8A7778_CLK_P>,
 537                                  <&cpg_clocks R8A7778_CLK_P>,
 538                                  <&cpg_clocks R8A7778_CLK_P>,
 539                                  <&cpg_clocks R8A7778_CLK_P>,
 540                                  <&cpg_clocks R8A7778_CLK_P>,
 541                                  <&cpg_clocks R8A7778_CLK_P>,
 542                                  <&cpg_clocks R8A7778_CLK_P>,
 543                                  <&cpg_clocks R8A7778_CLK_P>,
 544                                  <&cpg_clocks R8A7778_CLK_P>,
 545                                  <&cpg_clocks R8A7778_CLK_P>,
 546                                  <&cpg_clocks R8A7778_CLK_S>;
 547                         #clock-cells = <1>;
 548                         clock-indices = <
 549                                 R8A7778_CLK_I2C0 R8A7778_CLK_I2C1
 550                                 R8A7778_CLK_I2C2 R8A7778_CLK_I2C3
 551                                 R8A7778_CLK_SCIF0 R8A7778_CLK_SCIF1
 552                                 R8A7778_CLK_SCIF2 R8A7778_CLK_SCIF3
 553                                 R8A7778_CLK_SCIF4 R8A7778_CLK_SCIF5
 554                                 R8A7778_CLK_TMU0 R8A7778_CLK_TMU1
 555                                 R8A7778_CLK_TMU2 R8A7778_CLK_SSI0
 556                                 R8A7778_CLK_SSI1 R8A7778_CLK_SSI2
 557                                 R8A7778_CLK_SSI3 R8A7778_CLK_SRU
 558                                 R8A7778_CLK_HSPI
 559                         >;
 560                         clock-output-names =
 561                                 "i2c0", "i2c1", "i2c2", "i2c3", "scif0",
 562                                 "scif1", "scif2", "scif3", "scif4", "scif5",
 563                                 "tmu0", "tmu1", "tmu2", "ssi0", "ssi1",
 564                                 "ssi2", "ssi3", "sru", "hspi";
 565                 };
 566                 mstp1_clks: mstp1_clks@ffc80034 {
 567                         compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
 568                         reg = <0xffc80034 4>, <0xffc80044 4>;
 569                         clocks = <&cpg_clocks R8A7778_CLK_P>,
 570                                  <&cpg_clocks R8A7778_CLK_S>,
 571                                  <&cpg_clocks R8A7778_CLK_S>,
 572                                  <&cpg_clocks R8A7778_CLK_P>;
 573                         #clock-cells = <1>;
 574                         clock-indices = <
 575                                 R8A7778_CLK_ETHER R8A7778_CLK_VIN0
 576                                 R8A7778_CLK_VIN1 R8A7778_CLK_USB
 577                         >;
 578                         clock-output-names =
 579                                 "ether", "vin0", "vin1", "usb";
 580                 };
 581                 mstp3_clks: mstp3_clks@ffc8003c {
 582                         compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
 583                         reg = <0xffc8003c 4>;
 584                         clocks = <&s4_clk>,
 585                                  <&cpg_clocks R8A7778_CLK_P>,
 586                                  <&cpg_clocks R8A7778_CLK_P>,
 587                                  <&cpg_clocks R8A7778_CLK_P>,
 588                                  <&cpg_clocks R8A7778_CLK_P>,
 589                                  <&cpg_clocks R8A7778_CLK_P>,
 590                                  <&cpg_clocks R8A7778_CLK_P>,
 591                                  <&cpg_clocks R8A7778_CLK_P>,
 592                                  <&cpg_clocks R8A7778_CLK_P>;
 593                         #clock-cells = <1>;
 594                         clock-indices = <
 595                                 R8A7778_CLK_MMC R8A7778_CLK_SDHI0
 596                                 R8A7778_CLK_SDHI1 R8A7778_CLK_SDHI2
 597                                 R8A7778_CLK_SSI4 R8A7778_CLK_SSI5
 598                                 R8A7778_CLK_SSI6 R8A7778_CLK_SSI7
 599                                 R8A7778_CLK_SSI8
 600                         >;
 601                         clock-output-names =
 602                                 "mmc", "sdhi0", "sdhi1", "sdhi2", "ssi4",
 603                                 "ssi5", "ssi6", "ssi7", "ssi8";
 604                 };
 605                 mstp5_clks: mstp5_clks@ffc80054 {
 606                         compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
 607                         reg = <0xffc80054 4>;
 608                         clocks = <&cpg_clocks R8A7778_CLK_P>,
 609                                  <&cpg_clocks R8A7778_CLK_P>,
 610                                  <&cpg_clocks R8A7778_CLK_P>,
 611                                  <&cpg_clocks R8A7778_CLK_P>,
 612                                  <&cpg_clocks R8A7778_CLK_P>,
 613                                  <&cpg_clocks R8A7778_CLK_P>,
 614                                  <&cpg_clocks R8A7778_CLK_P>,
 615                                  <&cpg_clocks R8A7778_CLK_P>,
 616                                  <&cpg_clocks R8A7778_CLK_P>;
 617                         #clock-cells = <1>;
 618                         clock-indices = <
 619                                 R8A7778_CLK_SRU_SRC0 R8A7778_CLK_SRU_SRC1
 620                                 R8A7778_CLK_SRU_SRC2 R8A7778_CLK_SRU_SRC3
 621                                 R8A7778_CLK_SRU_SRC4 R8A7778_CLK_SRU_SRC5
 622                                 R8A7778_CLK_SRU_SRC6 R8A7778_CLK_SRU_SRC7
 623                                 R8A7778_CLK_SRU_SRC8
 624                         >;
 625                         clock-output-names =
 626                                 "sru-src0", "sru-src1", "sru-src2",
 627                                 "sru-src3", "sru-src4", "sru-src5",
 628                                 "sru-src6", "sru-src7", "sru-src8";
 629                 };
 630         };
 631
 632         rst: reset-controller@ffcc0000 {
 633                 compatible = "renesas,r8a7778-reset-wdt";
 634                 reg = <0xffcc0000 0x40>;
 635         };
 636 };