2 * Device Tree Source for the r8a73a4 SoC
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Magnus Damm
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
12 #include <dt-bindings/clock/r8a73a4-clock.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
17 compatible = "renesas,r8a73a4";
18 interrupt-parent = <&gic>;
28 compatible = "arm,cortex-a15";
30 clock-frequency = <1500000000>;
31 power-domains = <&pd_a2sl>;
32 next-level-cache = <&L2_CA15>;
35 L2_CA15: cache-controller@0 {
38 clocks = <&cpg_clocks R8A73A4_CLK_Z>;
39 power-domains = <&pd_a3sm>;
44 L2_CA7: cache-controller@100 {
47 clocks = <&cpg_clocks R8A73A4_CLK_Z2>;
48 power-domains = <&pd_a3km>;
55 compatible = "arm,coresight-etm3x";
56 power-domains = <&pd_d4>;
60 compatible = "arm,armv7-timer";
61 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
62 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
63 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
64 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
67 dbsc1: memory-controller@e6790000 {
68 compatible = "renesas,dbsc-r8a73a4";
69 reg = <0 0xe6790000 0 0x10000>;
70 power-domains = <&pd_a3bc>;
73 dbsc2: memory-controller@e67a0000 {
74 compatible = "renesas,dbsc-r8a73a4";
75 reg = <0 0xe67a0000 0 0x10000>;
76 power-domains = <&pd_a3bc>;
79 dmac: dma-multiplexer {
80 compatible = "renesas,shdma-mux";
88 dma0: dma-controller@e6700020 {
89 compatible = "renesas,shdma-r8a73a4";
90 reg = <0 0xe6700020 0 0x89e0>;
91 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
92 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
93 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
94 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
95 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
96 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
97 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
98 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
99 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
100 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
101 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
102 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
103 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
104 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
105 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
106 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH
107 GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
108 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
109 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
110 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
111 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
112 interrupt-names = "error",
113 "ch0", "ch1", "ch2", "ch3",
114 "ch4", "ch5", "ch6", "ch7",
115 "ch8", "ch9", "ch10", "ch11",
116 "ch12", "ch13", "ch14", "ch15",
117 "ch16", "ch17", "ch18", "ch19";
118 clocks = <&mstp2_clks R8A73A4_CLK_DMAC>;
119 power-domains = <&pd_a3sp>;
124 #address-cells = <1>;
126 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
127 reg = <0 0xe60b0000 0 0x428>;
128 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
129 clocks = <&mstp4_clks R8A73A4_CLK_IIC5>;
130 power-domains = <&pd_a3sp>;
135 cmt1: timer@e6130000 {
136 compatible = "renesas,cmt-48-r8a73a4", "renesas,cmt-48-gen2";
137 reg = <0 0xe6130000 0 0x1004>;
138 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
139 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
140 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
141 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
142 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
143 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
144 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
145 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
146 clocks = <&mstp3_clks R8A73A4_CLK_CMT1>;
148 power-domains = <&pd_c5>;
150 renesas,channels-mask = <0xff>;
155 irqc0: interrupt-controller@e61c0000 {
156 compatible = "renesas,irqc-r8a73a4", "renesas,irqc";
157 #interrupt-cells = <2>;
158 interrupt-controller;
159 reg = <0 0xe61c0000 0 0x200>;
160 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
161 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
162 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
163 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
164 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
165 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
166 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
167 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
168 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
169 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
170 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
171 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
172 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
173 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
174 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
175 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
176 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
177 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
178 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
179 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
180 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
181 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
182 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
183 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
184 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
185 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
186 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
187 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
188 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
189 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
190 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
191 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
192 clocks = <&mstp4_clks R8A73A4_CLK_IRQC>;
193 power-domains = <&pd_c4>;
196 irqc1: interrupt-controller@e61c0200 {
197 compatible = "renesas,irqc-r8a73a4", "renesas,irqc";
198 #interrupt-cells = <2>;
199 interrupt-controller;
200 reg = <0 0xe61c0200 0 0x200>;
201 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
202 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
203 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
204 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
205 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
206 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
207 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
208 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
209 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
210 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
211 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
212 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
213 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
214 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
215 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
216 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
217 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
218 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
219 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
220 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
221 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
222 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
223 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
224 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
225 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
226 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
227 clocks = <&mstp4_clks R8A73A4_CLK_IRQC>;
228 power-domains = <&pd_c4>;
232 compatible = "renesas,pfc-r8a73a4";
233 reg = <0 0xe6050000 0 0x9000>;
237 <&pfc 0 0 31>, <&pfc 32 32 9>,
238 <&pfc 64 64 22>, <&pfc 96 96 31>,
239 <&pfc 128 128 7>, <&pfc 160 160 19>,
240 <&pfc 192 192 31>, <&pfc 224 224 27>,
241 <&pfc 256 256 28>, <&pfc 288 288 21>,
243 interrupts-extended =
244 <&irqc0 0 0>, <&irqc0 1 0>, <&irqc0 2 0>, <&irqc0 3 0>,
245 <&irqc0 4 0>, <&irqc0 5 0>, <&irqc0 6 0>, <&irqc0 7 0>,
246 <&irqc0 8 0>, <&irqc0 9 0>, <&irqc0 10 0>, <&irqc0 11 0>,
247 <&irqc0 12 0>, <&irqc0 13 0>, <&irqc0 14 0>, <&irqc0 15 0>,
248 <&irqc0 16 0>, <&irqc0 17 0>, <&irqc0 18 0>, <&irqc0 19 0>,
249 <&irqc0 20 0>, <&irqc0 21 0>, <&irqc0 22 0>, <&irqc0 23 0>,
250 <&irqc0 24 0>, <&irqc0 25 0>, <&irqc0 26 0>, <&irqc0 27 0>,
251 <&irqc0 28 0>, <&irqc0 29 0>, <&irqc0 30 0>, <&irqc0 31 0>,
252 <&irqc1 0 0>, <&irqc1 1 0>, <&irqc1 2 0>, <&irqc1 3 0>,
253 <&irqc1 4 0>, <&irqc1 5 0>, <&irqc1 6 0>, <&irqc1 7 0>,
254 <&irqc1 8 0>, <&irqc1 9 0>, <&irqc1 10 0>, <&irqc1 11 0>,
255 <&irqc1 12 0>, <&irqc1 13 0>, <&irqc1 14 0>, <&irqc1 15 0>,
256 <&irqc1 16 0>, <&irqc1 17 0>, <&irqc1 18 0>, <&irqc1 19 0>,
257 <&irqc1 20 0>, <&irqc1 21 0>, <&irqc1 22 0>, <&irqc1 23 0>,
258 <&irqc1 24 0>, <&irqc1 25 0>;
259 power-domains = <&pd_c5>;
263 compatible = "renesas,thermal-r8a73a4", "renesas,rcar-thermal";
264 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>,
265 <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>;
266 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
267 clocks = <&mstp5_clks R8A73A4_CLK_THERMAL>;
268 power-domains = <&pd_c5>;
272 #address-cells = <1>;
274 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
275 reg = <0 0xe6500000 0 0x428>;
276 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
277 clocks = <&mstp3_clks R8A73A4_CLK_IIC0>;
278 power-domains = <&pd_a3sp>;
283 #address-cells = <1>;
285 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
286 reg = <0 0xe6510000 0 0x428>;
287 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
288 clocks = <&mstp3_clks R8A73A4_CLK_IIC1>;
289 power-domains = <&pd_a3sp>;
294 #address-cells = <1>;
296 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
297 reg = <0 0xe6520000 0 0x428>;
298 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
299 clocks = <&mstp3_clks R8A73A4_CLK_IIC2>;
300 power-domains = <&pd_a3sp>;
305 #address-cells = <1>;
307 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
308 reg = <0 0xe6530000 0 0x428>;
309 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
310 clocks = <&mstp4_clks R8A73A4_CLK_IIC3>;
311 power-domains = <&pd_a3sp>;
316 #address-cells = <1>;
318 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
319 reg = <0 0xe6540000 0 0x428>;
320 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
321 clocks = <&mstp4_clks R8A73A4_CLK_IIC4>;
322 power-domains = <&pd_a3sp>;
327 #address-cells = <1>;
329 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
330 reg = <0 0xe6550000 0 0x428>;
331 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
332 clocks = <&mstp3_clks R8A73A4_CLK_IIC6>;
333 power-domains = <&pd_a3sp>;
338 #address-cells = <1>;
340 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
341 reg = <0 0xe6560000 0 0x428>;
342 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
343 clocks = <&mstp3_clks R8A73A4_CLK_IIC7>;
344 power-domains = <&pd_a3sp>;
349 #address-cells = <1>;
351 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
352 reg = <0 0xe6570000 0 0x428>;
353 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
354 clocks = <&mstp5_clks R8A73A4_CLK_IIC8>;
355 power-domains = <&pd_a3sp>;
359 scifb0: serial@e6c20000 {
360 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
361 reg = <0 0xe6c20000 0 0x100>;
362 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
363 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB0>;
365 power-domains = <&pd_a3sp>;
369 scifb1: serial@e6c30000 {
370 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
371 reg = <0 0xe6c30000 0 0x100>;
372 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
373 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB1>;
375 power-domains = <&pd_a3sp>;
379 scifa0: serial@e6c40000 {
380 compatible = "renesas,scifa-r8a73a4", "renesas,scifa";
381 reg = <0 0xe6c40000 0 0x100>;
382 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
383 clocks = <&mstp2_clks R8A73A4_CLK_SCIFA0>;
385 power-domains = <&pd_a3sp>;
389 scifa1: serial@e6c50000 {
390 compatible = "renesas,scifa-r8a73a4", "renesas,scifa";
391 reg = <0 0xe6c50000 0 0x100>;
392 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
393 clocks = <&mstp2_clks R8A73A4_CLK_SCIFA1>;
395 power-domains = <&pd_a3sp>;
399 scifb2: serial@e6ce0000 {
400 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
401 reg = <0 0xe6ce0000 0 0x100>;
402 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
403 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB2>;
405 power-domains = <&pd_a3sp>;
409 scifb3: serial@e6cf0000 {
410 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
411 reg = <0 0xe6cf0000 0 0x100>;
412 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
413 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB3>;
415 power-domains = <&pd_c4>;
420 compatible = "renesas,sdhi-r8a73a4";
421 reg = <0 0xee100000 0 0x100>;
422 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
423 clocks = <&mstp3_clks R8A73A4_CLK_SDHI0>;
424 power-domains = <&pd_a3sp>;
430 compatible = "renesas,sdhi-r8a73a4";
431 reg = <0 0xee120000 0 0x100>;
432 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
433 clocks = <&mstp3_clks R8A73A4_CLK_SDHI1>;
434 power-domains = <&pd_a3sp>;
440 compatible = "renesas,sdhi-r8a73a4";
441 reg = <0 0xee140000 0 0x100>;
442 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
443 clocks = <&mstp3_clks R8A73A4_CLK_SDHI2>;
444 power-domains = <&pd_a3sp>;
449 mmcif0: mmc@ee200000 {
450 compatible = "renesas,sh-mmcif";
451 reg = <0 0xee200000 0 0x80>;
452 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
453 clocks = <&mstp3_clks R8A73A4_CLK_MMCIF0>;
454 power-domains = <&pd_a3sp>;
459 mmcif1: mmc@ee220000 {
460 compatible = "renesas,sh-mmcif";
461 reg = <0 0xee220000 0 0x80>;
462 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
463 clocks = <&mstp3_clks R8A73A4_CLK_MMCIF1>;
464 power-domains = <&pd_a3sp>;
469 gic: interrupt-controller@f1001000 {
470 compatible = "arm,gic-400";
471 #interrupt-cells = <3>;
472 #address-cells = <0>;
473 interrupt-controller;
474 reg = <0 0xf1001000 0 0x1000>,
475 <0 0xf1002000 0 0x1000>,
476 <0 0xf1004000 0 0x2000>,
477 <0 0xf1006000 0 0x2000>;
478 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
482 compatible = "renesas,bsc-r8a73a4", "renesas,bsc",
484 #address-cells = <1>;
486 ranges = <0 0 0 0x20000000>;
487 reg = <0 0xfec10000 0 0x400>;
489 power-domains = <&pd_c4>;
493 #address-cells = <2>;
497 /* External root clocks */
499 compatible = "fixed-clock";
501 clock-frequency = <32768>;
504 compatible = "fixed-clock";
506 clock-frequency = <25000000>;
509 compatible = "fixed-clock";
511 clock-frequency = <48000000>;
514 compatible = "fixed-clock";
516 /* This value must be overridden by the board. */
517 clock-frequency = <0>;
520 compatible = "fixed-clock";
522 /* This value must be overridden by the board. */
523 clock-frequency = <0>;
526 /* Special CPG clocks */
527 cpg_clocks: cpg_clocks@e6150000 {
528 compatible = "renesas,r8a73a4-cpg-clocks";
529 reg = <0 0xe6150000 0 0x10000>;
530 clocks = <&extal1_clk>, <&extal2_clk>;
532 clock-output-names = "main", "pll0", "pll1", "pll2",
533 "pll2s", "pll2h", "z", "z2",
534 "i", "m3", "b", "m1", "m2",
538 /* Variable factor clocks (DIV6) */
539 zb_clk: zb_clk@e6150010 {
540 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
541 reg = <0 0xe6150010 0 4>;
542 clocks = <&pll1_div2_clk>, <0>,
543 <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>;
545 clock-output-names = "zb";
547 sdhi0_clk: sdhi0ck@e6150074 {
548 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
549 reg = <0 0xe6150074 0 4>;
550 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
554 sdhi1_clk: sdhi1ck@e6150078 {
555 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
556 reg = <0 0xe6150078 0 4>;
557 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
561 sdhi2_clk: sdhi2ck@e615007c {
562 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
563 reg = <0 0xe615007c 0 4>;
564 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
568 mmc0_clk: mmc0@e6150240 {
569 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
570 reg = <0 0xe6150240 0 4>;
571 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
575 mmc1_clk: mmc1@e6150244 {
576 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
577 reg = <0 0xe6150244 0 4>;
578 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
582 vclk1_clk: vclk1@e6150008 {
583 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
584 reg = <0 0xe6150008 0 4>;
585 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
586 <0>, <&extal2_clk>, <&main_div2_clk>,
587 <&extalr_clk>, <0>, <0>;
590 vclk2_clk: vclk2@e615000c {
591 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
592 reg = <0 0xe615000c 0 4>;
593 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
594 <0>, <&extal2_clk>, <&main_div2_clk>,
595 <&extalr_clk>, <0>, <0>;
598 vclk3_clk: vclk3@e615001c {
599 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
600 reg = <0 0xe615001c 0 4>;
601 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
602 <0>, <&extal2_clk>, <&main_div2_clk>,
603 <&extalr_clk>, <0>, <0>;
606 vclk4_clk: vclk4@e6150014 {
607 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
608 reg = <0 0xe6150014 0 4>;
609 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
610 <0>, <&extal2_clk>, <&main_div2_clk>,
611 <&extalr_clk>, <0>, <0>;
614 vclk5_clk: vclk5@e6150034 {
615 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
616 reg = <0 0xe6150034 0 4>;
617 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
618 <0>, <&extal2_clk>, <&main_div2_clk>,
619 <&extalr_clk>, <0>, <0>;
622 fsia_clk: fsia@e6150018 {
623 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
624 reg = <0 0xe6150018 0 4>;
625 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
629 fsib_clk: fsib@e6150090 {
630 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
631 reg = <0 0xe6150090 0 4>;
632 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
636 mp_clk: mp@e6150080 {
637 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
638 reg = <0 0xe6150080 0 4>;
639 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
640 <&extal2_clk>, <&extal2_clk>;
643 m4_clk: m4@e6150098 {
644 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
645 reg = <0 0xe6150098 0 4>;
646 clocks = <&cpg_clocks R8A73A4_CLK_PLL2S>;
649 hsi_clk: hsi@e615026c {
650 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
651 reg = <0 0xe615026c 0 4>;
652 clocks = <&cpg_clocks R8A73A4_CLK_PLL2H>, <&pll1_div2_clk>,
653 <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>;
656 spuv_clk: spuv@e6150094 {
657 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
658 reg = <0 0xe6150094 0 4>;
659 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
660 <&extal2_clk>, <&extal2_clk>;
664 /* Fixed factor clocks */
665 main_div2_clk: main_div2 {
666 compatible = "fixed-factor-clock";
667 clocks = <&cpg_clocks R8A73A4_CLK_MAIN>;
672 pll0_div2_clk: pll0_div2 {
673 compatible = "fixed-factor-clock";
674 clocks = <&cpg_clocks R8A73A4_CLK_PLL0>;
679 pll1_div2_clk: pll1_div2 {
680 compatible = "fixed-factor-clock";
681 clocks = <&cpg_clocks R8A73A4_CLK_PLL1>;
686 extal1_div2_clk: extal1_div2 {
687 compatible = "fixed-factor-clock";
688 clocks = <&extal1_clk>;
695 mstp2_clks: mstp2_clks@e6150138 {
696 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
697 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
698 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
699 <&mp_clk>, <&mp_clk>, <&cpg_clocks R8A73A4_CLK_HP>;
702 R8A73A4_CLK_SCIFA0 R8A73A4_CLK_SCIFA1
703 R8A73A4_CLK_SCIFB0 R8A73A4_CLK_SCIFB1
704 R8A73A4_CLK_SCIFB2 R8A73A4_CLK_SCIFB3
708 "scifa0", "scifa1", "scifb0", "scifb1",
709 "scifb2", "scifb3", "dmac";
711 mstp3_clks: mstp3_clks@e615013c {
712 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
713 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
714 clocks = <&cpg_clocks R8A73A4_CLK_HP>, <&mmc1_clk>,
715 <&sdhi2_clk>, <&sdhi1_clk>, <&sdhi0_clk>,
716 <&mmc0_clk>, <&cpg_clocks R8A73A4_CLK_HP>,
717 <&cpg_clocks R8A73A4_CLK_HP>, <&cpg_clocks
718 R8A73A4_CLK_HP>, <&cpg_clocks
719 R8A73A4_CLK_HP>, <&extalr_clk>;
722 R8A73A4_CLK_IIC2 R8A73A4_CLK_MMCIF1
723 R8A73A4_CLK_SDHI2 R8A73A4_CLK_SDHI1
724 R8A73A4_CLK_SDHI0 R8A73A4_CLK_MMCIF0
725 R8A73A4_CLK_IIC6 R8A73A4_CLK_IIC7
726 R8A73A4_CLK_IIC0 R8A73A4_CLK_IIC1
730 "iic2", "mmcif1", "sdhi2", "sdhi1", "sdhi0",
731 "mmcif0", "iic6", "iic7", "iic0", "iic1",
734 mstp4_clks: mstp4_clks@e6150140 {
735 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
736 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
737 clocks = <&main_div2_clk>, <&main_div2_clk>,
738 <&cpg_clocks R8A73A4_CLK_HP>,
739 <&cpg_clocks R8A73A4_CLK_HP>;
742 R8A73A4_CLK_IRQC R8A73A4_CLK_IIC5
743 R8A73A4_CLK_IIC4 R8A73A4_CLK_IIC3
746 "irqc", "iic5", "iic4", "iic3";
748 mstp5_clks: mstp5_clks@e6150144 {
749 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
750 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
751 clocks = <&extal2_clk>, <&cpg_clocks R8A73A4_CLK_HP>;
754 R8A73A4_CLK_THERMAL R8A73A4_CLK_IIC8
761 sysc: system-controller@e6180000 {
762 compatible = "renesas,sysc-r8a73a4", "renesas,sysc-rmobile";
763 reg = <0 0xe6180000 0 0x8000>, <0 0xe6188000 0 0x8000>;
767 #address-cells = <1>;
769 #power-domain-cells = <0>;
773 #address-cells = <1>;
775 #power-domain-cells = <0>;
779 #power-domain-cells = <0>;
784 #power-domain-cells = <0>;
789 #address-cells = <1>;
791 #power-domain-cells = <0>;
795 #power-domain-cells = <0>;
801 #address-cells = <1>;
803 #power-domain-cells = <0>;
807 #power-domain-cells = <0>;
813 #address-cells = <1>;
815 #power-domain-cells = <0>;
819 #power-domain-cells = <0>;
826 #power-domain-cells = <0>;
831 #power-domain-cells = <0>;
836 #power-domain-cells = <0>;
841 #address-cells = <1>;
843 #power-domain-cells = <0>;
847 #power-domain-cells = <0>;
853 #power-domain-cells = <0>;
858 #power-domain-cells = <0>;
863 #address-cells = <1>;
865 #power-domain-cells = <0>;
869 #power-domain-cells = <0>;
874 #power-domain-cells = <0>;
880 #power-domain-cells = <0>;
885 #address-cells = <1>;
887 #power-domain-cells = <0>;
891 #power-domain-cells = <0>;
896 #power-domain-cells = <0>;