2 * Device Tree Source for the r8a73a4 SoC
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Magnus Damm
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
12 #include <dt-bindings/clock/r8a73a4-clock.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
17 compatible = "renesas,r8a73a4";
18 interrupt-parent = <&gic>;
28 compatible = "arm,cortex-a15";
30 clock-frequency = <1500000000>;
31 power-domains = <&pd_a2sl>;
32 next-level-cache = <&L2_CA15>;
35 L2_CA15: cache-controller-0 {
37 clocks = <&cpg_clocks R8A73A4_CLK_Z>;
38 power-domains = <&pd_a3sm>;
43 L2_CA7: cache-controller-1 {
45 clocks = <&cpg_clocks R8A73A4_CLK_Z2>;
46 power-domains = <&pd_a3km>;
53 compatible = "arm,coresight-etm3x";
54 power-domains = <&pd_d4>;
58 compatible = "arm,armv7-timer";
59 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
60 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
61 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
62 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
65 dbsc1: memory-controller@e6790000 {
66 compatible = "renesas,dbsc-r8a73a4";
67 reg = <0 0xe6790000 0 0x10000>;
68 power-domains = <&pd_a3bc>;
71 dbsc2: memory-controller@e67a0000 {
72 compatible = "renesas,dbsc-r8a73a4";
73 reg = <0 0xe67a0000 0 0x10000>;
74 power-domains = <&pd_a3bc>;
77 dmac: dma-multiplexer {
78 compatible = "renesas,shdma-mux";
86 dma0: dma-controller@e6700020 {
87 compatible = "renesas,shdma-r8a73a4";
88 reg = <0 0xe6700020 0 0x89e0>;
89 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
90 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
91 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
92 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
93 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
94 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
95 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
96 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
97 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
98 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
99 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
100 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
101 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
102 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
103 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
104 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH
105 GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
106 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
107 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
108 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
109 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
110 interrupt-names = "error",
111 "ch0", "ch1", "ch2", "ch3",
112 "ch4", "ch5", "ch6", "ch7",
113 "ch8", "ch9", "ch10", "ch11",
114 "ch12", "ch13", "ch14", "ch15",
115 "ch16", "ch17", "ch18", "ch19";
116 clocks = <&mstp2_clks R8A73A4_CLK_DMAC>;
117 power-domains = <&pd_a3sp>;
122 #address-cells = <1>;
124 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
125 reg = <0 0xe60b0000 0 0x428>;
126 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
127 clocks = <&mstp4_clks R8A73A4_CLK_IIC5>;
128 power-domains = <&pd_a3sp>;
133 cmt1: timer@e6130000 {
134 compatible = "renesas,cmt-48-r8a73a4", "renesas,cmt-48-gen2";
135 reg = <0 0xe6130000 0 0x1004>;
136 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
137 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
138 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
139 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
140 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
141 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
142 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
143 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
144 clocks = <&mstp3_clks R8A73A4_CLK_CMT1>;
146 power-domains = <&pd_c5>;
148 renesas,channels-mask = <0xff>;
153 irqc0: interrupt-controller@e61c0000 {
154 compatible = "renesas,irqc-r8a73a4", "renesas,irqc";
155 #interrupt-cells = <2>;
156 interrupt-controller;
157 reg = <0 0xe61c0000 0 0x200>;
158 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
159 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
160 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
161 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
162 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
163 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
164 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
165 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
166 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
167 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
168 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
169 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
170 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
171 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
172 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
173 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
174 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
175 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
176 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
177 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
178 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
179 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
180 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
181 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
182 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
183 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
184 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
185 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
186 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
187 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
188 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
189 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
190 clocks = <&mstp4_clks R8A73A4_CLK_IRQC>;
191 power-domains = <&pd_c4>;
194 irqc1: interrupt-controller@e61c0200 {
195 compatible = "renesas,irqc-r8a73a4", "renesas,irqc";
196 #interrupt-cells = <2>;
197 interrupt-controller;
198 reg = <0 0xe61c0200 0 0x200>;
199 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
200 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
201 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
202 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
203 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
204 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
205 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
206 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
207 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
208 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
209 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
210 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
211 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
212 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
213 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
214 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
215 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
216 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
217 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
218 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
219 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
220 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
221 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
222 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
223 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
224 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
225 clocks = <&mstp4_clks R8A73A4_CLK_IRQC>;
226 power-domains = <&pd_c4>;
229 pfc: pin-controller@e6050000 {
230 compatible = "renesas,pfc-r8a73a4";
231 reg = <0 0xe6050000 0 0x9000>;
235 <&pfc 0 0 31>, <&pfc 32 32 9>,
236 <&pfc 64 64 22>, <&pfc 96 96 31>,
237 <&pfc 128 128 7>, <&pfc 160 160 19>,
238 <&pfc 192 192 31>, <&pfc 224 224 27>,
239 <&pfc 256 256 28>, <&pfc 288 288 21>,
241 interrupts-extended =
242 <&irqc0 0 0>, <&irqc0 1 0>, <&irqc0 2 0>, <&irqc0 3 0>,
243 <&irqc0 4 0>, <&irqc0 5 0>, <&irqc0 6 0>, <&irqc0 7 0>,
244 <&irqc0 8 0>, <&irqc0 9 0>, <&irqc0 10 0>, <&irqc0 11 0>,
245 <&irqc0 12 0>, <&irqc0 13 0>, <&irqc0 14 0>, <&irqc0 15 0>,
246 <&irqc0 16 0>, <&irqc0 17 0>, <&irqc0 18 0>, <&irqc0 19 0>,
247 <&irqc0 20 0>, <&irqc0 21 0>, <&irqc0 22 0>, <&irqc0 23 0>,
248 <&irqc0 24 0>, <&irqc0 25 0>, <&irqc0 26 0>, <&irqc0 27 0>,
249 <&irqc0 28 0>, <&irqc0 29 0>, <&irqc0 30 0>, <&irqc0 31 0>,
250 <&irqc1 0 0>, <&irqc1 1 0>, <&irqc1 2 0>, <&irqc1 3 0>,
251 <&irqc1 4 0>, <&irqc1 5 0>, <&irqc1 6 0>, <&irqc1 7 0>,
252 <&irqc1 8 0>, <&irqc1 9 0>, <&irqc1 10 0>, <&irqc1 11 0>,
253 <&irqc1 12 0>, <&irqc1 13 0>, <&irqc1 14 0>, <&irqc1 15 0>,
254 <&irqc1 16 0>, <&irqc1 17 0>, <&irqc1 18 0>, <&irqc1 19 0>,
255 <&irqc1 20 0>, <&irqc1 21 0>, <&irqc1 22 0>, <&irqc1 23 0>,
256 <&irqc1 24 0>, <&irqc1 25 0>;
257 power-domains = <&pd_c5>;
261 compatible = "renesas,thermal-r8a73a4", "renesas,rcar-thermal";
262 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>,
263 <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>;
264 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
265 clocks = <&mstp5_clks R8A73A4_CLK_THERMAL>;
266 power-domains = <&pd_c5>;
270 #address-cells = <1>;
272 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
273 reg = <0 0xe6500000 0 0x428>;
274 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
275 clocks = <&mstp3_clks R8A73A4_CLK_IIC0>;
276 power-domains = <&pd_a3sp>;
281 #address-cells = <1>;
283 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
284 reg = <0 0xe6510000 0 0x428>;
285 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
286 clocks = <&mstp3_clks R8A73A4_CLK_IIC1>;
287 power-domains = <&pd_a3sp>;
292 #address-cells = <1>;
294 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
295 reg = <0 0xe6520000 0 0x428>;
296 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
297 clocks = <&mstp3_clks R8A73A4_CLK_IIC2>;
298 power-domains = <&pd_a3sp>;
303 #address-cells = <1>;
305 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
306 reg = <0 0xe6530000 0 0x428>;
307 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
308 clocks = <&mstp4_clks R8A73A4_CLK_IIC3>;
309 power-domains = <&pd_a3sp>;
314 #address-cells = <1>;
316 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
317 reg = <0 0xe6540000 0 0x428>;
318 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
319 clocks = <&mstp4_clks R8A73A4_CLK_IIC4>;
320 power-domains = <&pd_a3sp>;
325 #address-cells = <1>;
327 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
328 reg = <0 0xe6550000 0 0x428>;
329 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
330 clocks = <&mstp3_clks R8A73A4_CLK_IIC6>;
331 power-domains = <&pd_a3sp>;
336 #address-cells = <1>;
338 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
339 reg = <0 0xe6560000 0 0x428>;
340 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
341 clocks = <&mstp3_clks R8A73A4_CLK_IIC7>;
342 power-domains = <&pd_a3sp>;
347 #address-cells = <1>;
349 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
350 reg = <0 0xe6570000 0 0x428>;
351 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
352 clocks = <&mstp5_clks R8A73A4_CLK_IIC8>;
353 power-domains = <&pd_a3sp>;
357 scifb0: serial@e6c20000 {
358 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
359 reg = <0 0xe6c20000 0 0x100>;
360 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
361 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB0>;
363 power-domains = <&pd_a3sp>;
367 scifb1: serial@e6c30000 {
368 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
369 reg = <0 0xe6c30000 0 0x100>;
370 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
371 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB1>;
373 power-domains = <&pd_a3sp>;
377 scifa0: serial@e6c40000 {
378 compatible = "renesas,scifa-r8a73a4", "renesas,scifa";
379 reg = <0 0xe6c40000 0 0x100>;
380 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
381 clocks = <&mstp2_clks R8A73A4_CLK_SCIFA0>;
383 power-domains = <&pd_a3sp>;
387 scifa1: serial@e6c50000 {
388 compatible = "renesas,scifa-r8a73a4", "renesas,scifa";
389 reg = <0 0xe6c50000 0 0x100>;
390 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
391 clocks = <&mstp2_clks R8A73A4_CLK_SCIFA1>;
393 power-domains = <&pd_a3sp>;
397 scifb2: serial@e6ce0000 {
398 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
399 reg = <0 0xe6ce0000 0 0x100>;
400 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
401 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB2>;
403 power-domains = <&pd_a3sp>;
407 scifb3: serial@e6cf0000 {
408 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
409 reg = <0 0xe6cf0000 0 0x100>;
410 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
411 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB3>;
413 power-domains = <&pd_c4>;
418 compatible = "renesas,sdhi-r8a73a4";
419 reg = <0 0xee100000 0 0x100>;
420 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
421 clocks = <&mstp3_clks R8A73A4_CLK_SDHI0>;
422 power-domains = <&pd_a3sp>;
428 compatible = "renesas,sdhi-r8a73a4";
429 reg = <0 0xee120000 0 0x100>;
430 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
431 clocks = <&mstp3_clks R8A73A4_CLK_SDHI1>;
432 power-domains = <&pd_a3sp>;
438 compatible = "renesas,sdhi-r8a73a4";
439 reg = <0 0xee140000 0 0x100>;
440 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
441 clocks = <&mstp3_clks R8A73A4_CLK_SDHI2>;
442 power-domains = <&pd_a3sp>;
447 mmcif0: mmc@ee200000 {
448 compatible = "renesas,mmcif-r8a73a4", "renesas,sh-mmcif";
449 reg = <0 0xee200000 0 0x80>;
450 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
451 clocks = <&mstp3_clks R8A73A4_CLK_MMCIF0>;
452 power-domains = <&pd_a3sp>;
457 mmcif1: mmc@ee220000 {
458 compatible = "renesas,mmcif-r8a73a4", "renesas,sh-mmcif";
459 reg = <0 0xee220000 0 0x80>;
460 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
461 clocks = <&mstp3_clks R8A73A4_CLK_MMCIF1>;
462 power-domains = <&pd_a3sp>;
467 gic: interrupt-controller@f1001000 {
468 compatible = "arm,gic-400";
469 #interrupt-cells = <3>;
470 #address-cells = <0>;
471 interrupt-controller;
472 reg = <0 0xf1001000 0 0x1000>,
473 <0 0xf1002000 0 0x2000>,
474 <0 0xf1004000 0 0x2000>,
475 <0 0xf1006000 0 0x2000>;
476 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
477 clocks = <&mstp4_clks R8A73A4_CLK_INTC_SYS>;
479 power-domains = <&pd_c4>;
483 compatible = "renesas,bsc-r8a73a4", "renesas,bsc",
485 #address-cells = <1>;
487 ranges = <0 0 0 0x20000000>;
488 reg = <0 0xfec10000 0 0x400>;
490 power-domains = <&pd_c4>;
494 #address-cells = <2>;
498 /* External root clocks */
500 compatible = "fixed-clock";
502 clock-frequency = <32768>;
505 compatible = "fixed-clock";
507 clock-frequency = <25000000>;
510 compatible = "fixed-clock";
512 clock-frequency = <48000000>;
515 compatible = "fixed-clock";
517 /* This value must be overridden by the board. */
518 clock-frequency = <0>;
521 compatible = "fixed-clock";
523 /* This value must be overridden by the board. */
524 clock-frequency = <0>;
527 /* Special CPG clocks */
528 cpg_clocks: cpg_clocks@e6150000 {
529 compatible = "renesas,r8a73a4-cpg-clocks";
530 reg = <0 0xe6150000 0 0x10000>;
531 clocks = <&extal1_clk>, <&extal2_clk>;
533 clock-output-names = "main", "pll0", "pll1", "pll2",
534 "pll2s", "pll2h", "z", "z2",
535 "i", "m3", "b", "m1", "m2",
539 /* Variable factor clocks (DIV6) */
540 zb_clk: zb_clk@e6150010 {
541 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
542 reg = <0 0xe6150010 0 4>;
543 clocks = <&pll1_div2_clk>, <0>,
544 <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>;
546 clock-output-names = "zb";
548 sdhi0_clk: sdhi0ck@e6150074 {
549 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
550 reg = <0 0xe6150074 0 4>;
551 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
555 sdhi1_clk: sdhi1ck@e6150078 {
556 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
557 reg = <0 0xe6150078 0 4>;
558 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
562 sdhi2_clk: sdhi2ck@e615007c {
563 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
564 reg = <0 0xe615007c 0 4>;
565 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
569 mmc0_clk: mmc0@e6150240 {
570 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
571 reg = <0 0xe6150240 0 4>;
572 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
576 mmc1_clk: mmc1@e6150244 {
577 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
578 reg = <0 0xe6150244 0 4>;
579 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
583 vclk1_clk: vclk1@e6150008 {
584 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
585 reg = <0 0xe6150008 0 4>;
586 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
587 <0>, <&extal2_clk>, <&main_div2_clk>,
588 <&extalr_clk>, <0>, <0>;
591 vclk2_clk: vclk2@e615000c {
592 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
593 reg = <0 0xe615000c 0 4>;
594 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
595 <0>, <&extal2_clk>, <&main_div2_clk>,
596 <&extalr_clk>, <0>, <0>;
599 vclk3_clk: vclk3@e615001c {
600 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
601 reg = <0 0xe615001c 0 4>;
602 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
603 <0>, <&extal2_clk>, <&main_div2_clk>,
604 <&extalr_clk>, <0>, <0>;
607 vclk4_clk: vclk4@e6150014 {
608 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
609 reg = <0 0xe6150014 0 4>;
610 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
611 <0>, <&extal2_clk>, <&main_div2_clk>,
612 <&extalr_clk>, <0>, <0>;
615 vclk5_clk: vclk5@e6150034 {
616 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
617 reg = <0 0xe6150034 0 4>;
618 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
619 <0>, <&extal2_clk>, <&main_div2_clk>,
620 <&extalr_clk>, <0>, <0>;
623 fsia_clk: fsia@e6150018 {
624 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
625 reg = <0 0xe6150018 0 4>;
626 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
630 fsib_clk: fsib@e6150090 {
631 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
632 reg = <0 0xe6150090 0 4>;
633 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
637 mp_clk: mp@e6150080 {
638 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
639 reg = <0 0xe6150080 0 4>;
640 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
641 <&extal2_clk>, <&extal2_clk>;
644 m4_clk: m4@e6150098 {
645 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
646 reg = <0 0xe6150098 0 4>;
647 clocks = <&cpg_clocks R8A73A4_CLK_PLL2S>;
650 hsi_clk: hsi@e615026c {
651 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
652 reg = <0 0xe615026c 0 4>;
653 clocks = <&cpg_clocks R8A73A4_CLK_PLL2H>, <&pll1_div2_clk>,
654 <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>;
657 spuv_clk: spuv@e6150094 {
658 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
659 reg = <0 0xe6150094 0 4>;
660 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
661 <&extal2_clk>, <&extal2_clk>;
665 /* Fixed factor clocks */
666 main_div2_clk: main_div2 {
667 compatible = "fixed-factor-clock";
668 clocks = <&cpg_clocks R8A73A4_CLK_MAIN>;
673 pll0_div2_clk: pll0_div2 {
674 compatible = "fixed-factor-clock";
675 clocks = <&cpg_clocks R8A73A4_CLK_PLL0>;
680 pll1_div2_clk: pll1_div2 {
681 compatible = "fixed-factor-clock";
682 clocks = <&cpg_clocks R8A73A4_CLK_PLL1>;
687 extal1_div2_clk: extal1_div2 {
688 compatible = "fixed-factor-clock";
689 clocks = <&extal1_clk>;
696 mstp2_clks: mstp2_clks@e6150138 {
697 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
698 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
699 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
700 <&mp_clk>, <&mp_clk>, <&cpg_clocks R8A73A4_CLK_HP>;
703 R8A73A4_CLK_SCIFA0 R8A73A4_CLK_SCIFA1
704 R8A73A4_CLK_SCIFB0 R8A73A4_CLK_SCIFB1
705 R8A73A4_CLK_SCIFB2 R8A73A4_CLK_SCIFB3
709 "scifa0", "scifa1", "scifb0", "scifb1",
710 "scifb2", "scifb3", "dmac";
712 mstp3_clks: mstp3_clks@e615013c {
713 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
714 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
715 clocks = <&cpg_clocks R8A73A4_CLK_HP>, <&mmc1_clk>,
716 <&sdhi2_clk>, <&sdhi1_clk>, <&sdhi0_clk>,
717 <&mmc0_clk>, <&cpg_clocks R8A73A4_CLK_HP>,
718 <&cpg_clocks R8A73A4_CLK_HP>, <&cpg_clocks
719 R8A73A4_CLK_HP>, <&cpg_clocks
720 R8A73A4_CLK_HP>, <&extalr_clk>;
723 R8A73A4_CLK_IIC2 R8A73A4_CLK_MMCIF1
724 R8A73A4_CLK_SDHI2 R8A73A4_CLK_SDHI1
725 R8A73A4_CLK_SDHI0 R8A73A4_CLK_MMCIF0
726 R8A73A4_CLK_IIC6 R8A73A4_CLK_IIC7
727 R8A73A4_CLK_IIC0 R8A73A4_CLK_IIC1
731 "iic2", "mmcif1", "sdhi2", "sdhi1", "sdhi0",
732 "mmcif0", "iic6", "iic7", "iic0", "iic1",
735 mstp4_clks: mstp4_clks@e6150140 {
736 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
737 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
738 clocks = <&main_div2_clk>, <&cpg_clocks R8A73A4_CLK_ZS>,
740 <&cpg_clocks R8A73A4_CLK_HP>,
741 <&cpg_clocks R8A73A4_CLK_HP>;
744 R8A73A4_CLK_IRQC R8A73A4_CLK_INTC_SYS
745 R8A73A4_CLK_IIC5 R8A73A4_CLK_IIC4
749 "irqc", "intc-sys", "iic5", "iic4", "iic3";
751 mstp5_clks: mstp5_clks@e6150144 {
752 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
753 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
754 clocks = <&extal2_clk>, <&cpg_clocks R8A73A4_CLK_HP>;
757 R8A73A4_CLK_THERMAL R8A73A4_CLK_IIC8
764 prr: chipid@ff000044 {
765 compatible = "renesas,prr";
766 reg = <0 0xff000044 0 4>;
769 sysc: system-controller@e6180000 {
770 compatible = "renesas,sysc-r8a73a4", "renesas,sysc-rmobile";
771 reg = <0 0xe6180000 0 0x8000>, <0 0xe6188000 0 0x8000>;
775 #address-cells = <1>;
777 #power-domain-cells = <0>;
781 #address-cells = <1>;
783 #power-domain-cells = <0>;
787 #power-domain-cells = <0>;
792 #power-domain-cells = <0>;
797 #address-cells = <1>;
799 #power-domain-cells = <0>;
803 #power-domain-cells = <0>;
809 #address-cells = <1>;
811 #power-domain-cells = <0>;
815 #power-domain-cells = <0>;
821 #address-cells = <1>;
823 #power-domain-cells = <0>;
827 #power-domain-cells = <0>;
834 #power-domain-cells = <0>;
839 #power-domain-cells = <0>;
844 #power-domain-cells = <0>;
849 #address-cells = <1>;
851 #power-domain-cells = <0>;
855 #power-domain-cells = <0>;
861 #power-domain-cells = <0>;
866 #power-domain-cells = <0>;
871 #address-cells = <1>;
873 #power-domain-cells = <0>;
877 #power-domain-cells = <0>;
882 #power-domain-cells = <0>;
888 #power-domain-cells = <0>;
893 #address-cells = <1>;
895 #power-domain-cells = <0>;
899 #power-domain-cells = <0>;
904 #power-domain-cells = <0>;