2 * Device Tree Source for the r7s72100 SoC
4 * Copyright (C) 2013-14 Renesas Solutions Corp.
5 * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
12 #include <dt-bindings/clock/r7s72100-clock.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
17 compatible = "renesas,r7s72100";
18 interrupt-parent = <&gic>;
42 compatible = "fixed-clock";
43 /* If clk present, value must be set by board */
44 clock-frequency = <0>;
49 compatible = "fixed-clock";
50 /* If clk present, value must be set by board */
51 clock-frequency = <0>;
54 /* Fixed factor clocks */
57 compatible = "fixed-factor-clock";
58 clocks = <&cpg_clocks R7S72100_CLK_PLL>;
64 compatible = "fixed-factor-clock";
65 clocks = <&cpg_clocks R7S72100_CLK_PLL>;
71 compatible = "fixed-factor-clock";
72 clocks = <&cpg_clocks R7S72100_CLK_PLL>;
77 /* Special CPG clocks */
78 cpg_clocks: cpg_clocks@fcfe0000 {
80 compatible = "renesas,r7s72100-cpg-clocks",
81 "renesas,rz-cpg-clocks";
82 reg = <0xfcfe0000 0x18>;
83 clocks = <&extal_clk>, <&usb_x1_clk>;
84 clock-output-names = "pll", "i", "g";
85 #power-domain-cells = <0>;
89 mstp3_clks: mstp3_clks@fcfe0420 {
91 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
94 clock-indices = <R7S72100_CLK_MTU2>;
95 clock-output-names = "mtu2";
98 mstp4_clks: mstp4_clks@fcfe0424 {
100 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
101 reg = <0xfcfe0424 4>;
102 clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>,
103 <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>;
105 R7S72100_CLK_SCIF0 R7S72100_CLK_SCIF1 R7S72100_CLK_SCIF2 R7S72100_CLK_SCIF3
106 R7S72100_CLK_SCIF4 R7S72100_CLK_SCIF5 R7S72100_CLK_SCIF6 R7S72100_CLK_SCIF7
108 clock-output-names = "scif0", "scif1", "scif2", "scif3", "scif4", "scif5", "scif6", "scif7";
111 mstp7_clks: mstp7_clks@fcfe0430 {
113 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
114 reg = <0xfcfe0430 4>;
116 clock-indices = <R7S72100_CLK_ETHER>;
117 clock-output-names = "ether";
120 mstp9_clks: mstp9_clks@fcfe0438 {
122 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
123 reg = <0xfcfe0438 4>;
124 clocks = <&p0_clk>, <&p0_clk>, <&p0_clk>, <&p0_clk>;
126 R7S72100_CLK_I2C0 R7S72100_CLK_I2C1 R7S72100_CLK_I2C2 R7S72100_CLK_I2C3
128 clock-output-names = "i2c0", "i2c1", "i2c2", "i2c3";
131 mstp10_clks: mstp10_clks@fcfe043c {
133 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
134 reg = <0xfcfe043c 4>;
135 clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>,
138 R7S72100_CLK_SPI0 R7S72100_CLK_SPI1 R7S72100_CLK_SPI2 R7S72100_CLK_SPI3
141 clock-output-names = "spi0", "spi1", "spi2", "spi3", "spi4";
146 #address-cells = <1>;
151 compatible = "arm,cortex-a9";
153 clock-frequency = <400000000>;
157 scif0: serial@e8007000 {
158 compatible = "renesas,scif-r7s72100", "renesas,scif";
159 reg = <0xe8007000 64>;
160 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
161 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
162 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
163 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
164 clocks = <&mstp4_clks R7S72100_CLK_SCIF0>;
166 power-domains = <&cpg_clocks>;
170 scif1: serial@e8007800 {
171 compatible = "renesas,scif-r7s72100", "renesas,scif";
172 reg = <0xe8007800 64>;
173 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
174 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
175 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
176 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
177 clocks = <&mstp4_clks R7S72100_CLK_SCIF1>;
179 power-domains = <&cpg_clocks>;
183 scif2: serial@e8008000 {
184 compatible = "renesas,scif-r7s72100", "renesas,scif";
185 reg = <0xe8008000 64>;
186 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
187 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
188 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
189 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
190 clocks = <&mstp4_clks R7S72100_CLK_SCIF2>;
192 power-domains = <&cpg_clocks>;
196 scif3: serial@e8008800 {
197 compatible = "renesas,scif-r7s72100", "renesas,scif";
198 reg = <0xe8008800 64>;
199 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
200 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
201 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
202 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
203 clocks = <&mstp4_clks R7S72100_CLK_SCIF3>;
205 power-domains = <&cpg_clocks>;
209 scif4: serial@e8009000 {
210 compatible = "renesas,scif-r7s72100", "renesas,scif";
211 reg = <0xe8009000 64>;
212 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
213 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
214 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
215 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
216 clocks = <&mstp4_clks R7S72100_CLK_SCIF4>;
218 power-domains = <&cpg_clocks>;
222 scif5: serial@e8009800 {
223 compatible = "renesas,scif-r7s72100", "renesas,scif";
224 reg = <0xe8009800 64>;
225 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
226 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
227 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
228 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
229 clocks = <&mstp4_clks R7S72100_CLK_SCIF5>;
231 power-domains = <&cpg_clocks>;
235 scif6: serial@e800a000 {
236 compatible = "renesas,scif-r7s72100", "renesas,scif";
237 reg = <0xe800a000 64>;
238 interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
239 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
240 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
241 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
242 clocks = <&mstp4_clks R7S72100_CLK_SCIF6>;
244 power-domains = <&cpg_clocks>;
248 scif7: serial@e800a800 {
249 compatible = "renesas,scif-r7s72100", "renesas,scif";
250 reg = <0xe800a800 64>;
251 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
252 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
253 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
254 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
255 clocks = <&mstp4_clks R7S72100_CLK_SCIF7>;
257 power-domains = <&cpg_clocks>;
262 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
263 reg = <0xe800c800 0x24>;
264 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
265 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
266 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
267 interrupt-names = "error", "rx", "tx";
268 clocks = <&mstp10_clks R7S72100_CLK_SPI0>;
269 power-domains = <&cpg_clocks>;
271 #address-cells = <1>;
277 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
278 reg = <0xe800d000 0x24>;
279 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
280 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
281 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
282 interrupt-names = "error", "rx", "tx";
283 clocks = <&mstp10_clks R7S72100_CLK_SPI1>;
284 power-domains = <&cpg_clocks>;
286 #address-cells = <1>;
292 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
293 reg = <0xe800d800 0x24>;
294 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
295 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
296 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
297 interrupt-names = "error", "rx", "tx";
298 clocks = <&mstp10_clks R7S72100_CLK_SPI2>;
299 power-domains = <&cpg_clocks>;
301 #address-cells = <1>;
307 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
308 reg = <0xe800e000 0x24>;
309 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
310 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
311 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
312 interrupt-names = "error", "rx", "tx";
313 clocks = <&mstp10_clks R7S72100_CLK_SPI3>;
314 power-domains = <&cpg_clocks>;
316 #address-cells = <1>;
322 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
323 reg = <0xe800e800 0x24>;
324 interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
325 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
326 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
327 interrupt-names = "error", "rx", "tx";
328 clocks = <&mstp10_clks R7S72100_CLK_SPI4>;
329 power-domains = <&cpg_clocks>;
331 #address-cells = <1>;
336 gic: interrupt-controller@e8201000 {
337 compatible = "arm,pl390";
338 #interrupt-cells = <3>;
339 #address-cells = <0>;
340 interrupt-controller;
341 reg = <0xe8201000 0x1000>,
346 #address-cells = <1>;
348 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
349 reg = <0xfcfee000 0x44>;
350 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
351 <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>,
352 <GIC_SPI 159 IRQ_TYPE_EDGE_RISING>,
353 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
354 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
355 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
356 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
357 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
358 clocks = <&mstp9_clks R7S72100_CLK_I2C0>;
359 clock-frequency = <100000>;
360 power-domains = <&cpg_clocks>;
365 #address-cells = <1>;
367 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
368 reg = <0xfcfee400 0x44>;
369 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
370 <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>,
371 <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>,
372 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
373 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
374 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
375 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
376 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
377 clocks = <&mstp9_clks R7S72100_CLK_I2C1>;
378 clock-frequency = <100000>;
379 power-domains = <&cpg_clocks>;
384 #address-cells = <1>;
386 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
387 reg = <0xfcfee800 0x44>;
388 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
389 <GIC_SPI 174 IRQ_TYPE_EDGE_RISING>,
390 <GIC_SPI 175 IRQ_TYPE_EDGE_RISING>,
391 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
392 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
393 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
394 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
395 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
396 clocks = <&mstp9_clks R7S72100_CLK_I2C2>;
397 clock-frequency = <100000>;
398 power-domains = <&cpg_clocks>;
403 #address-cells = <1>;
405 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
406 reg = <0xfcfeec00 0x44>;
407 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
408 <GIC_SPI 182 IRQ_TYPE_EDGE_RISING>,
409 <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>,
410 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
411 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
412 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
413 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
414 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
415 clocks = <&mstp9_clks R7S72100_CLK_I2C3>;
416 clock-frequency = <100000>;
417 power-domains = <&cpg_clocks>;
421 mtu2: timer@fcff0000 {
422 compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
423 reg = <0xfcff0000 0x400>;
424 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
425 interrupt-names = "tgi0a";
426 clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
428 power-domains = <&cpg_clocks>;
432 ether: ethernet@e8203000 {
433 compatible = "renesas,ether-r7s72100";
434 reg = <0xe8203000 0x800>,
436 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
437 clocks = <&mstp7_clks R7S72100_CLK_ETHER>;
438 power-domains = <&cpg_clocks>;
440 #address-cells = <1>;