arch/arm/boot/dts/r7s72100-rskrza1.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for the RZ/A1H RSK board
   4  *
   5  * Copyright (C) 2016 Renesas Electronics
   6  */
   7
   8 /dts-v1/;
   9 #include "r7s72100.dtsi"
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include <dt-bindings/pinctrl/r7s72100-pinctrl.h>
  12
  13 / {
  14         model = "RSKRZA1";
  15         compatible = "renesas,rskrza1", "renesas,r7s72100";
  16
  17         aliases {
  18                 serial0 = &scif2;
  19         };
  20
  21         chosen {
  22                 bootargs = "ignore_loglevel";
  23                 stdout-path = "serial0:115200n8";
  24         };
  25
  26         memory@8000000 {
  27                 device_type = "memory";
  28                 reg = <0x08000000 0x02000000>;
  29         };
  30
  31         lbsc {
  32                 #address-cells = <1>;
  33                 #size-cells = <1>;
  34         };
  35
  36         leds {
  37                 status = "okay";
  38                 compatible = "gpio-leds";
  39
  40                 led0 {
  41                         gpios = <&port7 1 GPIO_ACTIVE_LOW>;
  42                 };
  43         };
  44 };
  45
  46 &extal_clk {
  47         clock-frequency = <13330000>;
  48 };
  49
  50 &usb_x1_clk {
  51         clock-frequency = <48000000>;
  52 };
  53
  54 &rtc_x1_clk {
  55         clock-frequency = <32768>;
  56 };
  57
  58 &pinctrl {
  59
  60         /* Serial Console */
  61         scif2_pins: serial2 {
  62                 pinmux = <RZA1_PINMUX(3, 0, 6)>,        /* TxD2 */
  63                          <RZA1_PINMUX(3, 2, 4)>;        /* RxD2 */
  64         };
  65
  66         /* Ethernet */
  67         ether_pins: ether {
  68                 /* Ethernet on Ports 1,2,3,5 */
  69                 pinmux = <RZA1_PINMUX(1, 14, 4)>,       /* ET_COL   */
  70                          <RZA1_PINMUX(5, 9, 2)>,        /* ET_MDC   */
  71                          <RZA1_PINMUX(3, 3, 2)>,        /* ET_MDIO  */
  72                          <RZA1_PINMUX(3, 4, 2)>,        /* ET_RXCLK */
  73                          <RZA1_PINMUX(3, 5, 2)>,        /* ET_RXER  */
  74                          <RZA1_PINMUX(3, 6, 2)>,        /* ET_RXDV  */
  75                          <RZA1_PINMUX(2, 0, 2)>,        /* ET_TXCLK */
  76                          <RZA1_PINMUX(2, 1, 2)>,        /* ET_TXER  */
  77                          <RZA1_PINMUX(2, 2, 2)>,        /* ET_TXEN  */
  78                          <RZA1_PINMUX(2, 3, 2)>,        /* ET_CRS   */
  79                          <RZA1_PINMUX(2, 4, 2)>,        /* ET_TXD0  */
  80                          <RZA1_PINMUX(2, 5, 2)>,        /* ET_TXD1  */
  81                          <RZA1_PINMUX(2, 6, 2)>,        /* ET_TXD2  */
  82                          <RZA1_PINMUX(2, 7, 2)>,        /* ET_TXD3  */
  83                          <RZA1_PINMUX(2, 8, 2)>,        /* ET_RXD0  */
  84                          <RZA1_PINMUX(2, 9, 2)>,        /* ET_RXD1  */
  85                          <RZA1_PINMUX(2, 10, 2)>,       /* ET_RXD2  */
  86                          <RZA1_PINMUX(2, 11, 2)>;       /* ET_RXD3  */
  87         };
  88
  89         /* SDHI ch1 on CN1 */
  90         sdhi1_pins: sdhi1 {
  91                 pinmux = <RZA1_PINMUX(3, 8, 7)>,        /* SD_CD_1 */
  92                          <RZA1_PINMUX(3, 9, 7)>,        /* SD_WP_1 */
  93                          <RZA1_PINMUX(3, 10, 7)>,       /* SD_D1_1 */
  94                          <RZA1_PINMUX(3, 11, 7)>,       /* SD_D0_1 */
  95                          <RZA1_PINMUX(3, 12, 7)>,       /* SD_CLK_1 */
  96                          <RZA1_PINMUX(3, 13, 7)>,       /* SD_CMD_1 */
  97                          <RZA1_PINMUX(3, 14, 7)>,       /* SD_D3_1 */
  98                          <RZA1_PINMUX(3, 15, 7)>;       /* SD_D2_1 */
  99         };
 100 };
 101
 102 &mtu2 {
 103         status = "okay";
 104 };
 105
 106 &ether {
 107         pinctrl-names = "default";
 108         pinctrl-0 = <&ether_pins>;
 109         status = "okay";
 110         renesas,no-ether-link;
 111         phy-handle = <&phy0>;
 112         phy0: ethernet-phy@0 {
 113                 reg = <0>;
 114         };
 115 };
 116
 117 &sdhi1 {
 118         pinctrl-names = "default";
 119         pinctrl-0 = <&sdhi1_pins>;
 120         bus-width = <4>;
 121         status = "okay";
 122 };
 123
 124 &ostm0 {
 125         status = "okay";
 126 };
 127
 128 &ostm1 {
 129         status = "okay";
 130 };
 131
 132 &rtc {
 133         status = "okay";
 134 };
 135
 136 &scif2 {
 137         pinctrl-names = "default";
 138         pinctrl-0 = <&scif2_pins>;
 139         status = "okay";
 140 };