1 // SPDX-License-Identifier: BSD-3-Clause
3 * SDX55 SoC device tree source
5 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
6 * Copyright (c) 2020, Linaro Ltd.
9 #include <dt-bindings/clock/qcom,gcc-sdx55.h>
10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interconnect/qcom,sdx55.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/power/qcom-rpmpd.h>
15 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
20 qcom,msm-id = <357 0x10000>, <368 0x10000>, <418 0x10000>;
21 interrupt-parent = <&intc>;
24 device_type = "memory";
30 compatible = "fixed-clock";
32 clock-frequency = <38400000>;
33 clock-output-names = "xo_board";
36 sleep_clk: sleep-clk {
37 compatible = "fixed-clock";
39 clock-frequency = <32000>;
42 nand_clk_dummy: nand-clk-dummy {
43 compatible = "fixed-clock";
45 clock-frequency = <32000>;
55 compatible = "arm,cortex-a7";
57 enable-method = "psci";
59 power-domains = <&rpmhpd SDX55_CX>;
60 power-domain-names = "rpmhpd";
61 operating-points-v2 = <&cpu_opp_table>;
65 cpu_opp_table: cpu-opp-table {
66 compatible = "operating-points-v2";
70 opp-hz = /bits/ 64 <345600000>;
71 required-opps = <&rpmhpd_opp_low_svs>;
75 opp-hz = /bits/ 64 <576000000>;
76 required-opps = <&rpmhpd_opp_svs>;
80 opp-hz = /bits/ 64 <1094400000>;
81 required-opps = <&rpmhpd_opp_nom>;
85 opp-hz = /bits/ 64 <1555200000>;
86 required-opps = <&rpmhpd_opp_turbo>;
92 compatible = "qcom,scm-sdx55", "qcom,scm";
97 compatible = "arm,psci-1.0";
102 #address-cells = <1>;
106 hyp_mem: memory@8fc00000 {
108 reg = <0x8fc00000 0x80000>;
111 ac_db_mem: memory@8fc80000 {
113 reg = <0x8fc80000 0x40000>;
116 secdata_mem: memory@8fcfd000 {
118 reg = <0x8fcfd000 0x1000>;
121 sbl_mem: memory@8fd00000 {
123 reg = <0x8fd00000 0x100000>;
126 aop_image: memory@8fe00000 {
128 reg = <0x8fe00000 0x20000>;
131 aop_cmd_db: memory@8fe20000 {
132 compatible = "qcom,cmd-db";
133 reg = <0x8fe20000 0x20000>;
137 smem_mem: memory@8fe40000 {
139 reg = <0x8fe40000 0xc0000>;
142 tz_mem: memory@8ff00000 {
144 reg = <0x8ff00000 0x100000>;
147 tz_apps_mem: memory@90000000 {
149 reg = <0x90000000 0x500000>;
154 compatible = "qcom,smem";
155 memory-region = <&smem_mem>;
156 hwlocks = <&tcsr_mutex 3>;
160 compatible = "qcom,smp2p";
161 qcom,smem = <435>, <428>;
162 interrupts = <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>;
164 qcom,local-pid = <0>;
165 qcom,remote-pid = <1>;
167 modem_smp2p_out: master-kernel {
168 qcom,entry-name = "master-kernel";
169 #qcom,smem-state-cells = <1>;
172 modem_smp2p_in: slave-kernel {
173 qcom,entry-name = "slave-kernel";
174 interrupt-controller;
175 #interrupt-cells = <2>;
178 ipa_smp2p_out: ipa-ap-to-modem {
179 qcom,entry-name = "ipa";
180 #qcom,smem-state-cells = <1>;
183 ipa_smp2p_in: ipa-modem-to-ap {
184 qcom,entry-name = "ipa";
185 interrupt-controller;
186 #interrupt-cells = <2>;
191 #address-cells = <1>;
194 compatible = "simple-bus";
196 gcc: clock-controller@100000 {
197 compatible = "qcom,gcc-sdx55";
198 reg = <0x100000 0x1f0000>;
201 #power-domain-cells = <1>;
202 clock-names = "bi_tcxo", "sleep_clk";
203 clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
206 blsp1_uart3: serial@831000 {
207 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
208 reg = <0x00831000 0x200>;
209 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
212 clock-names = "core", "iface";
216 usb_hsphy: phy@ff4000 {
217 compatible = "qcom,usb-snps-hs-7nm-phy";
218 reg = <0x00ff4000 0x114>;
222 clocks = <&rpmhcc RPMH_CXO_CLK>;
225 resets = <&gcc GCC_QUSB2PHY_BCR>;
228 usb_qmpphy: phy@ff6000 {
229 compatible = "qcom,sdx55-qmp-usb3-uni-phy";
230 reg = <0x00ff6000 0x1c0>;
232 #address-cells = <1>;
236 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
237 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
238 <&gcc GCC_USB3_PRIM_CLKREF_CLK>;
239 clock-names = "aux", "cfg_ahb", "ref";
241 resets = <&gcc GCC_USB3PHY_PHY_BCR>,
242 <&gcc GCC_USB3_PHY_BCR>;
243 reset-names = "phy", "common";
245 usb_ssphy: phy@ff6200 {
246 reg = <0x00ff6200 0x170>,
251 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
252 clock-names = "pipe0";
253 clock-output-names = "usb3_uni_phy_pipe_clk_src";
257 mc_virt: interconnect@1100000 {
258 compatible = "qcom,sdx55-mc-virt";
259 reg = <0x01100000 0x400000>;
260 #interconnect-cells = <1>;
261 qcom,bcm-voters = <&apps_bcm_voter>;
264 mem_noc: interconnect@9680000 {
265 compatible = "qcom,sdx55-mem-noc";
266 reg = <0x09680000 0x40000>;
267 #interconnect-cells = <1>;
268 qcom,bcm-voters = <&apps_bcm_voter>;
271 system_noc: interconnect@162c000 {
272 compatible = "qcom,sdx55-system-noc";
273 reg = <0x0162c000 0x31200>;
274 #interconnect-cells = <1>;
275 qcom,bcm-voters = <&apps_bcm_voter>;
278 qpic_bam: dma-controller@1b04000 {
279 compatible = "qcom,bam-v1.7.0";
280 reg = <0x01b04000 0x1c000>;
281 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
282 clocks = <&rpmhcc RPMH_QPIC_CLK>;
283 clock-names = "bam_clk";
286 qcom,controlled-remotely;
290 qpic_nand: nand-controller@1b30000 {
291 compatible = "qcom,sdx55-nand";
292 reg = <0x01b30000 0x10000>;
293 #address-cells = <1>;
295 clocks = <&rpmhcc RPMH_QPIC_CLK>,
297 clock-names = "core", "aon";
299 dmas = <&qpic_bam 0>,
302 dma-names = "tx", "rx", "cmd";
306 pcie_ep: pcie-ep@1c00000 {
307 compatible = "qcom,sdx55-pcie-ep";
308 reg = <0x01c00000 0x3000>,
312 <0x40200000 0x100000>,
314 reg-names = "parf", "dbi", "elbi", "atu", "addr_space",
317 qcom,perst-regs = <&tcsr 0xb258 0xb270>;
319 clocks = <&gcc GCC_PCIE_AUX_CLK>,
320 <&gcc GCC_PCIE_CFG_AHB_CLK>,
321 <&gcc GCC_PCIE_MSTR_AXI_CLK>,
322 <&gcc GCC_PCIE_SLV_AXI_CLK>,
323 <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
324 <&gcc GCC_PCIE_SLEEP_CLK>,
325 <&gcc GCC_PCIE_0_CLKREF_CLK>;
326 clock-names = "aux", "cfg", "bus_master", "bus_slave",
327 "slave_q2a", "sleep", "ref";
329 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
330 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
331 interrupt-names = "global", "doorbell";
332 reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
333 wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>;
334 resets = <&gcc GCC_PCIE_BCR>;
335 reset-names = "core";
336 power-domains = <&gcc PCIE_GDSC>;
337 phys = <&pcie0_lane>;
338 phy-names = "pciephy";
339 max-link-speed = <3>;
345 pcie0_phy: phy@1c07000 {
346 compatible = "qcom,sdx55-qmp-pcie-phy";
347 reg = <0x01c07000 0x1c4>;
348 #address-cells = <1>;
351 clocks = <&gcc GCC_PCIE_AUX_PHY_CLK_SRC>,
352 <&gcc GCC_PCIE_CFG_AHB_CLK>,
353 <&gcc GCC_PCIE_0_CLKREF_CLK>,
354 <&gcc GCC_PCIE_RCHNG_PHY_CLK>;
355 clock-names = "aux", "cfg_ahb", "ref", "refgen";
357 resets = <&gcc GCC_PCIE_PHY_BCR>;
360 assigned-clocks = <&gcc GCC_PCIE_RCHNG_PHY_CLK>;
361 assigned-clock-rates = <100000000>;
365 pcie0_lane: lanes@1c06000 {
366 reg = <0x01c06000 0x104>, /* tx0 */
367 <0x01c06200 0x328>, /* rx0 */
368 <0x01c07200 0x1e8>, /* pcs */
369 <0x01c06800 0x104>, /* tx1 */
370 <0x01c06a00 0x328>, /* rx1 */
371 <0x01c07600 0x800>; /* pcs_misc */
372 clocks = <&gcc GCC_PCIE_PIPE_CLK>;
373 clock-names = "pipe0";
376 clock-output-names = "pcie_pipe_clk";
381 compatible = "qcom,sdx55-ipa";
383 iommus = <&apps_smmu 0x5e0 0x0>,
384 <&apps_smmu 0x5e2 0x0>;
385 reg = <0x1e40000 0x7000>,
388 reg-names = "ipa-reg",
392 interrupts-extended = <&intc GIC_SPI 241 IRQ_TYPE_EDGE_RISING>,
393 <&intc GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
394 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
395 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
396 interrupt-names = "ipa",
401 clocks = <&rpmhcc RPMH_IPA_CLK>;
402 clock-names = "core";
404 interconnects = <&system_noc MASTER_IPA &mc_virt SLAVE_EBI_CH0>,
405 <&system_noc MASTER_IPA &system_noc SLAVE_OCIMEM>,
406 <&mem_noc MASTER_AMPSS_M0 &system_noc SLAVE_IPA_CFG>;
407 interconnect-names = "memory",
411 qcom,smem-states = <&ipa_smp2p_out 0>,
413 qcom,smem-state-names = "ipa-clock-enabled-valid",
419 tcsr_mutex: hwlock@1f40000 {
420 compatible = "qcom,tcsr-mutex";
421 reg = <0x01f40000 0x40000>;
425 tcsr: syscon@1fcb000 {
426 compatible = "syscon";
427 reg = <0x01fc0000 0x1000>;
430 sdhc_1: mmc@8804000 {
431 compatible = "qcom,sdx55-sdhci", "qcom,sdhci-msm-v5";
432 reg = <0x08804000 0x1000>;
433 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
434 <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
435 interrupt-names = "hc_irq", "pwr_irq";
436 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
437 <&gcc GCC_SDCC1_APPS_CLK>;
438 clock-names = "iface", "core";
442 remoteproc_mpss: remoteproc@4080000 {
443 compatible = "qcom,sdx55-mpss-pas";
444 reg = <0x04080000 0x4040>;
446 interrupts-extended = <&intc GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
447 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
448 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
449 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
450 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
451 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
452 interrupt-names = "wdog", "fatal", "ready", "handover",
453 "stop-ack", "shutdown-ack";
455 clocks = <&rpmhcc RPMH_CXO_CLK>;
458 power-domains = <&rpmhpd SDX55_CX>,
460 power-domain-names = "cx", "mss";
462 qcom,smem-states = <&modem_smp2p_out 0>;
463 qcom,smem-state-names = "stop";
468 interrupts = <GIC_SPI 114 IRQ_TYPE_EDGE_RISING>;
470 qcom,remote-pid = <1>;
476 compatible = "qcom,sdx55-dwc3", "qcom,dwc3";
477 reg = <0x0a6f8800 0x400>;
479 #address-cells = <1>;
483 clocks = <&gcc GCC_USB30_SLV_AHB_CLK>,
484 <&gcc GCC_USB30_MASTER_CLK>,
485 <&gcc GCC_USB30_MSTR_AXI_CLK>,
486 <&gcc GCC_USB30_SLEEP_CLK>,
487 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
488 clock-names = "cfg_noc",
494 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
495 <&gcc GCC_USB30_MASTER_CLK>;
496 assigned-clock-rates = <19200000>, <200000000>;
498 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
499 <&pdc 51 IRQ_TYPE_LEVEL_HIGH>,
500 <&pdc 11 IRQ_TYPE_EDGE_BOTH>,
501 <&pdc 10 IRQ_TYPE_EDGE_BOTH>;
502 interrupt-names = "hs_phy_irq", "ss_phy_irq",
503 "dm_hs_phy_irq", "dp_hs_phy_irq";
505 power-domains = <&gcc USB30_GDSC>;
507 resets = <&gcc GCC_USB30_BCR>;
509 usb_dwc3: dwc3@a600000 {
510 compatible = "snps,dwc3";
511 reg = <0x0a600000 0xcd00>;
512 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
513 iommus = <&apps_smmu 0x1a0 0x0>;
514 snps,dis_u2_susphy_quirk;
515 snps,dis_enblslpm_quirk;
516 phys = <&usb_hsphy>, <&usb_ssphy>;
517 phy-names = "usb2-phy", "usb3-phy";
521 pdc: interrupt-controller@b210000 {
522 compatible = "qcom,sdx55-pdc", "qcom,pdc";
523 reg = <0x0b210000 0x30000>;
524 qcom,pdc-ranges = <0 179 52>;
525 #interrupt-cells = <2>;
526 interrupt-parent = <&intc>;
527 interrupt-controller;
531 compatible = "qcom,pshold";
532 reg = <0x0c264000 0x1000>;
535 spmi_bus: spmi@c440000 {
536 compatible = "qcom,spmi-pmic-arb";
537 reg = <0x0c440000 0x0000d00>,
538 <0x0c600000 0x2000000>,
539 <0x0e600000 0x0100000>,
540 <0x0e700000 0x00a0000>,
541 <0x0c40a000 0x0000700>;
542 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
543 interrupt-names = "periph_irq";
544 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
547 #address-cells = <2>;
549 interrupt-controller;
550 #interrupt-cells = <4>;
554 tlmm: pinctrl@f100000 {
555 compatible = "qcom,sdx55-pinctrl";
556 reg = <0xf100000 0x300000>;
557 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
560 interrupt-controller;
561 #interrupt-cells = <2>;
565 compatible = "qcom,sdx55-imem", "syscon", "simple-mfd";
566 reg = <0x1468f000 0x1000>;
568 #address-cells = <1>;
571 ranges = <0x0 0x1468f000 0x1000>;
574 compatible = "qcom,pil-reloc-info";
579 apps_smmu: iommu@15000000 {
580 compatible = "qcom,sdx55-smmu-500", "qcom,smmu-500", "arm,mmu-500";
581 reg = <0x15000000 0x20000>;
583 #global-interrupts = <1>;
584 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
585 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
586 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
587 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
588 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
589 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
590 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
591 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
592 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
593 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
594 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
595 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
596 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
597 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
598 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
599 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
600 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
603 intc: interrupt-controller@17800000 {
604 compatible = "qcom,msm-qgic2";
605 interrupt-controller;
606 interrupt-parent = <&intc>;
607 #interrupt-cells = <3>;
608 reg = <0x17800000 0x1000>,
612 a7pll: clock@17808000 {
613 compatible = "qcom,sdx55-a7pll";
614 reg = <0x17808000 0x1000>;
615 clocks = <&rpmhcc RPMH_CXO_CLK>;
616 clock-names = "bi_tcxo";
620 apcs: mailbox@17810000 {
621 compatible = "qcom,sdx55-apcs-gcc", "syscon";
622 reg = <0x17810000 0x2000>;
624 clocks = <&rpmhcc RPMH_CXO_CLK>, <&a7pll>, <&gcc GPLL0>;
625 clock-names = "ref", "pll", "aux";
630 compatible = "qcom,apss-wdt-sdx55", "qcom,kpss-wdt";
631 reg = <0x17817000 0x1000>;
632 clocks = <&sleep_clk>;
636 #address-cells = <1>;
639 compatible = "arm,armv7-timer-mem";
640 reg = <0x17820000 0x1000>;
641 clock-frequency = <19200000>;
645 interrupts = <GIC_SPI 7 0x4>,
647 reg = <0x17821000 0x1000>,
653 interrupts = <GIC_SPI 8 0x4>;
654 reg = <0x17823000 0x1000>;
660 interrupts = <GIC_SPI 9 0x4>;
661 reg = <0x17824000 0x1000>;
667 interrupts = <GIC_SPI 10 0x4>;
668 reg = <0x17825000 0x1000>;
674 interrupts = <GIC_SPI 11 0x4>;
675 reg = <0x17826000 0x1000>;
681 interrupts = <GIC_SPI 12 0x4>;
682 reg = <0x17827000 0x1000>;
688 interrupts = <GIC_SPI 13 0x4>;
689 reg = <0x17828000 0x1000>;
695 interrupts = <GIC_SPI 14 0x4>;
696 reg = <0x17829000 0x1000>;
701 apps_rsc: rsc@17840000 {
702 compatible = "qcom,rpmh-rsc";
703 reg = <0x17830000 0x10000>, <0x17840000 0x10000>;
704 reg-names = "drv-0", "drv-1";
705 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
706 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
707 qcom,tcs-offset = <0xd00>;
709 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 2>,
710 <WAKE_TCS 2>, <CONTROL_TCS 1>;
712 rpmhcc: clock-controller {
713 compatible = "qcom,sdx55-rpmh-clk";
716 clocks = <&xo_board>;
719 rpmhpd: power-controller {
720 compatible = "qcom,sdx55-rpmhpd";
721 #power-domain-cells = <1>;
722 operating-points-v2 = <&rpmhpd_opp_table>;
724 rpmhpd_opp_table: opp-table {
725 compatible = "operating-points-v2";
727 rpmhpd_opp_ret: opp1 {
728 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
731 rpmhpd_opp_min_svs: opp2 {
732 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
735 rpmhpd_opp_low_svs: opp3 {
736 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
739 rpmhpd_opp_svs: opp4 {
740 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
743 rpmhpd_opp_svs_l1: opp5 {
744 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
747 rpmhpd_opp_nom: opp6 {
748 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
751 rpmhpd_opp_nom_l1: opp7 {
752 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
755 rpmhpd_opp_nom_l2: opp8 {
756 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
759 rpmhpd_opp_turbo: opp9 {
760 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
763 rpmhpd_opp_turbo_l1: opp10 {
764 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
769 apps_bcm_voter: bcm-voter {
770 compatible = "qcom,bcm-voter";
776 compatible = "arm,armv7-timer";
777 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
778 <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
779 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
780 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
781 clock-frequency = <19200000>;