1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/interconnect/qcom,msm8974.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/reset/qcom,gcc-msm8974.h>
10 #include <dt-bindings/gpio/gpio.h>
15 interrupt-parent = <&intc>;
19 compatible = "fixed-clock";
21 clock-frequency = <19200000>;
24 sleep_clk: sleep_clk {
25 compatible = "fixed-clock";
27 clock-frequency = <32768>;
34 interrupts = <GIC_PPI 9 0xf04>;
37 compatible = "qcom,krait";
38 enable-method = "qcom,kpss-acc-v2";
41 next-level-cache = <&L2>;
44 cpu-idle-states = <&CPU_SPC>;
48 compatible = "qcom,krait";
49 enable-method = "qcom,kpss-acc-v2";
52 next-level-cache = <&L2>;
55 cpu-idle-states = <&CPU_SPC>;
59 compatible = "qcom,krait";
60 enable-method = "qcom,kpss-acc-v2";
63 next-level-cache = <&L2>;
66 cpu-idle-states = <&CPU_SPC>;
70 compatible = "qcom,krait";
71 enable-method = "qcom,kpss-acc-v2";
74 next-level-cache = <&L2>;
77 cpu-idle-states = <&CPU_SPC>;
88 compatible = "qcom,idle-state-spc",
90 entry-latency-us = <150>;
91 exit-latency-us = <200>;
92 min-residency-us = <2000>;
99 compatible = "qcom,scm-msm8974", "qcom,scm";
100 clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
101 clock-names = "core", "bus", "iface";
106 device_type = "memory";
111 compatible = "qcom,krait-pmu";
112 interrupts = <GIC_PPI 7 0xf04>;
116 #address-cells = <1>;
120 mpss_region: mpss@8000000 {
121 reg = <0x08000000 0x5100000>;
125 mba_region: mba@d100000 {
126 reg = <0x0d100000 0x100000>;
130 wcnss_region: wcnss@d200000 {
131 reg = <0x0d200000 0xa00000>;
135 adsp_region: adsp@dc00000 {
136 reg = <0x0dc00000 0x1900000>;
140 venus_region: memory@f500000 {
141 reg = <0x0f500000 0x500000>;
145 smem_region: smem@fa00000 {
146 reg = <0xfa00000 0x200000>;
150 tz_region: memory@fc00000 {
151 reg = <0x0fc00000 0x160000>;
155 rfsa_mem: memory@fd60000 {
156 reg = <0x0fd60000 0x20000>;
161 compatible = "qcom,rmtfs-mem";
162 reg = <0x0fd80000 0x180000>;
165 qcom,client-id = <1>;
170 compatible = "qcom,smem";
172 memory-region = <&smem_region>;
173 qcom,rpm-msg-ram = <&rpm_msg_ram>;
175 hwlocks = <&tcsr_mutex 3>;
179 compatible = "qcom,smp2p";
180 qcom,smem = <443>, <429>;
182 interrupt-parent = <&intc>;
183 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
185 qcom,ipc = <&apcs 8 10>;
187 qcom,local-pid = <0>;
188 qcom,remote-pid = <2>;
190 adsp_smp2p_out: master-kernel {
191 qcom,entry-name = "master-kernel";
192 #qcom,smem-state-cells = <1>;
195 adsp_smp2p_in: slave-kernel {
196 qcom,entry-name = "slave-kernel";
198 interrupt-controller;
199 #interrupt-cells = <2>;
204 compatible = "qcom,smp2p";
205 qcom,smem = <435>, <428>;
207 interrupt-parent = <&intc>;
208 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
210 qcom,ipc = <&apcs 8 14>;
212 qcom,local-pid = <0>;
213 qcom,remote-pid = <1>;
215 modem_smp2p_out: master-kernel {
216 qcom,entry-name = "master-kernel";
217 #qcom,smem-state-cells = <1>;
220 modem_smp2p_in: slave-kernel {
221 qcom,entry-name = "slave-kernel";
223 interrupt-controller;
224 #interrupt-cells = <2>;
229 compatible = "qcom,smp2p";
230 qcom,smem = <451>, <431>;
232 interrupt-parent = <&intc>;
233 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
235 qcom,ipc = <&apcs 8 18>;
237 qcom,local-pid = <0>;
238 qcom,remote-pid = <4>;
240 wcnss_smp2p_out: master-kernel {
241 qcom,entry-name = "master-kernel";
243 #qcom,smem-state-cells = <1>;
246 wcnss_smp2p_in: slave-kernel {
247 qcom,entry-name = "slave-kernel";
249 interrupt-controller;
250 #interrupt-cells = <2>;
255 compatible = "qcom,smsm";
257 #address-cells = <1>;
260 qcom,ipc-1 = <&apcs 8 13>;
261 qcom,ipc-2 = <&apcs 8 9>;
262 qcom,ipc-3 = <&apcs 8 19>;
267 #qcom,smem-state-cells = <1>;
270 modem_smsm: modem@1 {
272 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
274 interrupt-controller;
275 #interrupt-cells = <2>;
280 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
282 interrupt-controller;
283 #interrupt-cells = <2>;
286 wcnss_smsm: wcnss@7 {
288 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
290 interrupt-controller;
291 #interrupt-cells = <2>;
296 compatible = "qcom,smd";
299 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
300 qcom,ipc = <&apcs 8 0>;
301 qcom,smd-edge = <15>;
303 rpm_requests: rpm-requests {
304 compatible = "qcom,rpm-msm8974";
305 qcom,smd-channels = "rpm_requests";
307 rpmcc: clock-controller {
308 compatible = "qcom,rpmcc-msm8974", "qcom,rpmcc";
316 #address-cells = <1>;
319 compatible = "simple-bus";
321 intc: interrupt-controller@f9000000 {
322 compatible = "qcom,msm-qgic2";
323 interrupt-controller;
324 #interrupt-cells = <3>;
325 reg = <0xf9000000 0x1000>,
329 apcs: syscon@f9011000 {
330 compatible = "syscon";
331 reg = <0xf9011000 0x1000>;
335 #address-cells = <1>;
338 compatible = "arm,armv7-timer-mem";
339 reg = <0xf9020000 0x1000>;
340 clock-frequency = <19200000>;
344 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
345 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
346 reg = <0xf9021000 0x1000>,
352 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
353 reg = <0xf9023000 0x1000>;
359 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
360 reg = <0xf9024000 0x1000>;
366 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
367 reg = <0xf9025000 0x1000>;
373 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
374 reg = <0xf9026000 0x1000>;
380 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
381 reg = <0xf9027000 0x1000>;
387 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
388 reg = <0xf9028000 0x1000>;
393 saw0: power-controller@f9089000 {
394 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
395 reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
398 saw1: power-controller@f9099000 {
399 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
400 reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
403 saw2: power-controller@f90a9000 {
404 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
405 reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
408 saw3: power-controller@f90b9000 {
409 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
410 reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
413 saw_l2: power-controller@f9012000 {
414 compatible = "qcom,saw2";
415 reg = <0xf9012000 0x1000>;
419 acc0: clock-controller@f9088000 {
420 compatible = "qcom,kpss-acc-v2";
421 reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
424 acc1: clock-controller@f9098000 {
425 compatible = "qcom,kpss-acc-v2";
426 reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
429 acc2: clock-controller@f90a8000 {
430 compatible = "qcom,kpss-acc-v2";
431 reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
434 acc3: clock-controller@f90b8000 {
435 compatible = "qcom,kpss-acc-v2";
436 reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
439 sdhc_1: mmc@f9824900 {
440 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
441 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
442 reg-names = "hc", "core";
443 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
444 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
445 interrupt-names = "hc_irq", "pwr_irq";
446 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
447 <&gcc GCC_SDCC1_APPS_CLK>,
449 clock-names = "iface", "core", "xo";
456 sdhc_3: mmc@f9864900 {
457 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
458 reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
459 reg-names = "hc", "core";
460 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
461 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
462 interrupt-names = "hc_irq", "pwr_irq";
463 clocks = <&gcc GCC_SDCC3_AHB_CLK>,
464 <&gcc GCC_SDCC3_APPS_CLK>,
466 clock-names = "iface", "core", "xo";
469 #address-cells = <1>;
475 sdhc_2: mmc@f98a4900 {
476 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
477 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
478 reg-names = "hc", "core";
479 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
480 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
481 interrupt-names = "hc_irq", "pwr_irq";
482 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
483 <&gcc GCC_SDCC2_APPS_CLK>,
485 clock-names = "iface", "core", "xo";
488 #address-cells = <1>;
494 blsp1_uart1: serial@f991d000 {
495 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
496 reg = <0xf991d000 0x1000>;
497 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
498 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
499 clock-names = "core", "iface";
503 blsp1_uart2: serial@f991e000 {
504 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
505 reg = <0xf991e000 0x1000>;
506 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
507 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
508 clock-names = "core", "iface";
509 pinctrl-names = "default";
510 pinctrl-0 = <&blsp1_uart2_default>;
514 blsp1_i2c1: i2c@f9923000 {
516 compatible = "qcom,i2c-qup-v2.1.1";
517 reg = <0xf9923000 0x1000>;
518 interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
519 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
520 clock-names = "core", "iface";
521 pinctrl-names = "default", "sleep";
522 pinctrl-0 = <&blsp1_i2c1_default>;
523 pinctrl-1 = <&blsp1_i2c1_sleep>;
524 #address-cells = <1>;
528 blsp1_i2c2: i2c@f9924000 {
530 compatible = "qcom,i2c-qup-v2.1.1";
531 reg = <0xf9924000 0x1000>;
532 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
533 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
534 clock-names = "core", "iface";
535 pinctrl-names = "default", "sleep";
536 pinctrl-0 = <&blsp1_i2c2_default>;
537 pinctrl-1 = <&blsp1_i2c2_sleep>;
538 #address-cells = <1>;
542 blsp1_i2c3: i2c@f9925000 {
544 compatible = "qcom,i2c-qup-v2.1.1";
545 reg = <0xf9925000 0x1000>;
546 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
547 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
548 clock-names = "core", "iface";
549 pinctrl-names = "default", "sleep";
550 pinctrl-0 = <&blsp1_i2c3_default>;
551 pinctrl-1 = <&blsp1_i2c3_sleep>;
552 #address-cells = <1>;
556 blsp1_i2c6: i2c@f9928000 {
558 compatible = "qcom,i2c-qup-v2.1.1";
559 reg = <0xf9928000 0x1000>;
560 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
561 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
562 clock-names = "core", "iface";
563 pinctrl-names = "default", "sleep";
564 pinctrl-0 = <&blsp1_i2c6_default>;
565 pinctrl-1 = <&blsp1_i2c6_sleep>;
566 #address-cells = <1>;
570 blsp2_dma: dma-controller@f9944000 {
571 compatible = "qcom,bam-v1.4.0";
572 reg = <0xf9944000 0x19000>;
573 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
574 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
575 clock-names = "bam_clk";
580 blsp2_uart1: serial@f995d000 {
581 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
582 reg = <0xf995d000 0x1000>;
583 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
584 clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
585 clock-names = "core", "iface";
586 pinctrl-names = "default", "sleep";
587 pinctrl-0 = <&blsp2_uart1_default>;
588 pinctrl-1 = <&blsp2_uart1_sleep>;
592 blsp2_uart2: serial@f995e000 {
593 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
594 reg = <0xf995e000 0x1000>;
595 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
596 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
597 clock-names = "core", "iface";
601 blsp2_uart4: serial@f9960000 {
602 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
603 reg = <0xf9960000 0x1000>;
604 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
605 clocks = <&gcc GCC_BLSP2_UART4_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
606 clock-names = "core", "iface";
607 pinctrl-names = "default";
608 pinctrl-0 = <&blsp2_uart4_default>;
612 blsp2_i2c2: i2c@f9964000 {
614 compatible = "qcom,i2c-qup-v2.1.1";
615 reg = <0xf9964000 0x1000>;
616 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
617 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
618 clock-names = "core", "iface";
619 pinctrl-names = "default", "sleep";
620 pinctrl-0 = <&blsp2_i2c2_default>;
621 pinctrl-1 = <&blsp2_i2c2_sleep>;
622 #address-cells = <1>;
626 blsp2_i2c5: i2c@f9967000 {
628 compatible = "qcom,i2c-qup-v2.1.1";
629 reg = <0xf9967000 0x1000>;
630 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
631 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
632 clock-names = "core", "iface";
633 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
634 dma-names = "tx", "rx";
635 pinctrl-names = "default", "sleep";
636 pinctrl-0 = <&blsp2_i2c5_default>;
637 pinctrl-1 = <&blsp2_i2c5_sleep>;
638 #address-cells = <1>;
642 blsp2_i2c6: i2c@f9968000 {
644 compatible = "qcom,i2c-qup-v2.1.1";
645 reg = <0xf9968000 0x1000>;
646 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
647 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
648 clock-names = "core", "iface";
649 pinctrl-names = "default", "sleep";
650 pinctrl-0 = <&blsp2_i2c6_default>;
651 pinctrl-1 = <&blsp2_i2c6_sleep>;
652 #address-cells = <1>;
657 compatible = "qcom,ci-hdrc";
658 reg = <0xf9a55000 0x200>,
660 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
661 clocks = <&gcc GCC_USB_HS_AHB_CLK>,
662 <&gcc GCC_USB_HS_SYSTEM_CLK>;
663 clock-names = "iface", "core";
664 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
665 assigned-clock-rates = <75000000>;
666 resets = <&gcc GCC_USB_HS_BCR>;
667 reset-names = "core";
670 ahb-burst-config = <0>;
671 phy-names = "usb-phy";
677 compatible = "qcom,usb-hs-phy-msm8974",
680 clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
681 clock-names = "ref", "sleep";
682 resets = <&gcc GCC_USB2A_PHY_BCR>, <&otg 0>;
683 reset-names = "phy", "por";
688 compatible = "qcom,usb-hs-phy-msm8974",
691 clocks = <&xo_board>, <&gcc GCC_USB2B_PHY_SLEEP_CLK>;
692 clock-names = "ref", "sleep";
693 resets = <&gcc GCC_USB2B_PHY_BCR>, <&otg 1>;
694 reset-names = "phy", "por";
701 compatible = "qcom,prng";
702 reg = <0xf9bff000 0x200>;
703 clocks = <&gcc GCC_PRNG_AHB_CLK>;
704 clock-names = "core";
707 pronto: remoteproc@fb21b000 {
708 compatible = "qcom,pronto-v2-pil", "qcom,pronto";
709 reg = <0xfb204000 0x2000>, <0xfb202000 0x1000>, <0xfb21b000 0x3000>;
710 reg-names = "ccu", "dxe", "pmu";
712 memory-region = <&wcnss_region>;
714 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
715 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
716 <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
717 <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
718 <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
719 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
721 qcom,smem-states = <&wcnss_smp2p_out 0>;
722 qcom,smem-state-names = "stop";
727 compatible = "qcom,wcn3680";
729 clocks = <&rpmcc RPM_SMD_CXO_A2>;
734 interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
736 qcom,ipc = <&apcs 8 17>;
740 compatible = "qcom,wcnss";
741 qcom,smd-channels = "WCNSS_CTRL";
744 qcom,mmio = <&pronto>;
747 compatible = "qcom,wcnss-bt";
751 compatible = "qcom,wcnss-wlan";
753 interrupts = <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>,
754 <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>;
755 interrupt-names = "tx", "rx";
757 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
758 qcom,smem-state-names = "tx-enable",
766 compatible = "qcom,msm8974-rpm-stats";
767 reg = <0xfc190000 0x10000>;
771 compatible = "arm,coresight-tmc", "arm,primecell";
772 reg = <0xfc307000 0x1000>;
774 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
775 clock-names = "apb_pclk", "atclk";
780 remote-endpoint = <&replicator_in>;
788 remote-endpoint = <&merger_out>;
795 compatible = "arm,coresight-tpiu", "arm,primecell";
796 reg = <0xfc318000 0x1000>;
798 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
799 clock-names = "apb_pclk", "atclk";
804 remote-endpoint = <&replicator_out1>;
811 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
812 reg = <0xfc31a000 0x1000>;
814 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
815 clock-names = "apb_pclk", "atclk";
818 #address-cells = <1>;
822 * Not described input ports:
824 * 1 - connected trought funnel to Multimedia CPU
825 * 2 - connected to Wireless CPU
829 * 7 - connected to STM
833 funnel1_in5: endpoint {
834 remote-endpoint = <&kpss_out>;
841 funnel1_out: endpoint {
842 remote-endpoint = <&merger_in1>;
849 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
850 reg = <0xfc31b000 0x1000>;
852 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
853 clock-names = "apb_pclk", "atclk";
856 #address-cells = <1>;
860 * Not described input ports:
861 * 0 - connected trought funnel to Audio, Modem and
862 * Resource and Power Manager CPU's
863 * 2...7 - not-connected
867 merger_in1: endpoint {
868 remote-endpoint = <&funnel1_out>;
875 merger_out: endpoint {
876 remote-endpoint = <&etf_in>;
882 replicator@fc31c000 {
883 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
884 reg = <0xfc31c000 0x1000>;
886 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
887 clock-names = "apb_pclk", "atclk";
890 #address-cells = <1>;
895 replicator_out0: endpoint {
896 remote-endpoint = <&etr_in>;
901 replicator_out1: endpoint {
902 remote-endpoint = <&tpiu_in>;
909 replicator_in: endpoint {
910 remote-endpoint = <&etf_out>;
917 compatible = "arm,coresight-tmc", "arm,primecell";
918 reg = <0xfc322000 0x1000>;
920 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
921 clock-names = "apb_pclk", "atclk";
926 remote-endpoint = <&replicator_out0>;
933 compatible = "arm,coresight-etm4x", "arm,primecell";
934 reg = <0xfc33c000 0x1000>;
936 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
937 clock-names = "apb_pclk", "atclk";
944 remote-endpoint = <&kpss_in0>;
951 compatible = "arm,coresight-etm4x", "arm,primecell";
952 reg = <0xfc33d000 0x1000>;
954 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
955 clock-names = "apb_pclk", "atclk";
962 remote-endpoint = <&kpss_in1>;
969 compatible = "arm,coresight-etm4x", "arm,primecell";
970 reg = <0xfc33e000 0x1000>;
972 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
973 clock-names = "apb_pclk", "atclk";
980 remote-endpoint = <&kpss_in2>;
987 compatible = "arm,coresight-etm4x", "arm,primecell";
988 reg = <0xfc33f000 0x1000>;
990 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
991 clock-names = "apb_pclk", "atclk";
998 remote-endpoint = <&kpss_in3>;
1004 /* KPSS funnel, only 4 inputs are used */
1006 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1007 reg = <0xfc345000 0x1000>;
1009 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1010 clock-names = "apb_pclk", "atclk";
1013 #address-cells = <1>;
1018 kpss_in0: endpoint {
1019 remote-endpoint = <&etm0_out>;
1024 kpss_in1: endpoint {
1025 remote-endpoint = <&etm1_out>;
1030 kpss_in2: endpoint {
1031 remote-endpoint = <&etm2_out>;
1036 kpss_in3: endpoint {
1037 remote-endpoint = <&etm3_out>;
1044 kpss_out: endpoint {
1045 remote-endpoint = <&funnel1_in5>;
1051 gcc: clock-controller@fc400000 {
1052 compatible = "qcom,gcc-msm8974";
1055 #power-domain-cells = <1>;
1056 reg = <0xfc400000 0x4000>;
1059 rpm_msg_ram: memory@fc428000 {
1060 compatible = "qcom,rpm-msg-ram";
1061 reg = <0xfc428000 0x4000>;
1064 bimc: interconnect@fc380000 {
1065 reg = <0xfc380000 0x6a000>;
1066 compatible = "qcom,msm8974-bimc";
1067 #interconnect-cells = <1>;
1068 clock-names = "bus", "bus_a";
1069 clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
1070 <&rpmcc RPM_SMD_BIMC_A_CLK>;
1073 snoc: interconnect@fc460000 {
1074 reg = <0xfc460000 0x4000>;
1075 compatible = "qcom,msm8974-snoc";
1076 #interconnect-cells = <1>;
1077 clock-names = "bus", "bus_a";
1078 clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
1079 <&rpmcc RPM_SMD_SNOC_A_CLK>;
1082 pnoc: interconnect@fc468000 {
1083 reg = <0xfc468000 0x4000>;
1084 compatible = "qcom,msm8974-pnoc";
1085 #interconnect-cells = <1>;
1086 clock-names = "bus", "bus_a";
1087 clocks = <&rpmcc RPM_SMD_PNOC_CLK>,
1088 <&rpmcc RPM_SMD_PNOC_A_CLK>;
1091 ocmemnoc: interconnect@fc470000 {
1092 reg = <0xfc470000 0x4000>;
1093 compatible = "qcom,msm8974-ocmemnoc";
1094 #interconnect-cells = <1>;
1095 clock-names = "bus", "bus_a";
1096 clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
1097 <&rpmcc RPM_SMD_OCMEMGX_A_CLK>;
1100 mmssnoc: interconnect@fc478000 {
1101 reg = <0xfc478000 0x4000>;
1102 compatible = "qcom,msm8974-mmssnoc";
1103 #interconnect-cells = <1>;
1104 clock-names = "bus", "bus_a";
1105 clocks = <&mmcc MMSS_S0_AXI_CLK>,
1106 <&mmcc MMSS_S0_AXI_CLK>;
1109 cnoc: interconnect@fc480000 {
1110 reg = <0xfc480000 0x4000>;
1111 compatible = "qcom,msm8974-cnoc";
1112 #interconnect-cells = <1>;
1113 clock-names = "bus", "bus_a";
1114 clocks = <&rpmcc RPM_SMD_CNOC_CLK>,
1115 <&rpmcc RPM_SMD_CNOC_A_CLK>;
1118 tsens: thermal-sensor@fc4a9000 {
1119 compatible = "qcom,msm8974-tsens";
1120 reg = <0xfc4a9000 0x1000>, /* TM */
1121 <0xfc4a8000 0x1000>; /* SROT */
1122 nvmem-cells = <&tsens_calib>, <&tsens_backup>;
1123 nvmem-cell-names = "calib", "calib_backup";
1124 #qcom,sensors = <11>;
1125 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
1126 interrupt-names = "uplow";
1127 #thermal-sensor-cells = <1>;
1131 compatible = "qcom,pshold";
1132 reg = <0xfc4ab000 0x4>;
1135 qfprom: qfprom@fc4bc000 {
1136 compatible = "qcom,msm8974-qfprom", "qcom,qfprom";
1137 reg = <0xfc4bc000 0x2100>;
1138 #address-cells = <1>;
1140 tsens_calib: calib@d0 {
1143 tsens_backup: backup@440 {
1148 spmi_bus: spmi@fc4cf000 {
1149 compatible = "qcom,spmi-pmic-arb";
1150 reg-names = "core", "intr", "cnfg";
1151 reg = <0xfc4cf000 0x1000>,
1152 <0xfc4cb000 0x1000>,
1153 <0xfc4ca000 0x1000>;
1154 interrupt-names = "periph_irq";
1155 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1158 #address-cells = <2>;
1160 interrupt-controller;
1161 #interrupt-cells = <4>;
1164 bam_dmux_dma: dma-controller@fc834000 {
1165 compatible = "qcom,bam-v1.4.0";
1166 reg = <0xfc834000 0x7000>;
1167 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1173 qcom,powered-remotely;
1176 remoteproc_mss: remoteproc@fc880000 {
1177 compatible = "qcom,msm8974-mss-pil";
1178 reg = <0xfc880000 0x100>, <0xfc820000 0x020>;
1179 reg-names = "qdsp6", "rmb";
1181 interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
1182 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1183 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1184 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1185 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1186 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
1188 clocks = <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
1189 <&gcc GCC_MSS_CFG_AHB_CLK>,
1190 <&gcc GCC_BOOT_ROM_AHB_CLK>,
1192 clock-names = "iface", "bus", "mem", "xo";
1194 resets = <&gcc GCC_MSS_RESTART>;
1195 reset-names = "mss_restart";
1197 qcom,halt-regs = <&tcsr_mutex_block 0x1180 0x1200 0x1280>;
1199 qcom,smem-states = <&modem_smp2p_out 0>;
1200 qcom,smem-state-names = "stop";
1202 status = "disabled";
1205 memory-region = <&mba_region>;
1209 memory-region = <&mpss_region>;
1212 bam_dmux: bam-dmux {
1213 compatible = "qcom,bam-dmux";
1215 interrupt-parent = <&modem_smsm>;
1216 interrupts = <1 IRQ_TYPE_EDGE_BOTH>, <11 IRQ_TYPE_EDGE_BOTH>;
1217 interrupt-names = "pc", "pc-ack";
1219 qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>;
1220 qcom,smem-state-names = "pc", "pc-ack";
1222 dmas = <&bam_dmux_dma 4>, <&bam_dmux_dma 5>;
1223 dma-names = "tx", "rx";
1227 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
1229 qcom,ipc = <&apcs 8 12>;
1230 qcom,smd-edge = <0>;
1236 tcsr_mutex_block: syscon@fd484000 {
1237 compatible = "syscon";
1238 reg = <0xfd484000 0x2000>;
1241 tcsr: syscon@fd4a0000 {
1242 compatible = "syscon";
1243 reg = <0xfd4a0000 0x10000>;
1246 tlmm: pinctrl@fd510000 {
1247 compatible = "qcom,msm8974-pinctrl";
1248 reg = <0xfd510000 0x4000>;
1250 gpio-ranges = <&tlmm 0 0 146>;
1252 interrupt-controller;
1253 #interrupt-cells = <2>;
1254 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1256 sdc1_off: sdc1-off {
1260 drive-strength = <2>;
1266 drive-strength = <2>;
1272 drive-strength = <2>;
1276 sdc2_off: sdc2-off {
1280 drive-strength = <2>;
1286 drive-strength = <2>;
1292 drive-strength = <2>;
1298 drive-strength = <2>;
1302 blsp1_uart2_default: blsp1-uart2-default {
1305 function = "blsp_uart2";
1306 drive-strength = <2>;
1312 function = "blsp_uart2";
1313 drive-strength = <4>;
1318 blsp2_uart1_default: blsp2-uart1-default {
1320 pins = "gpio41", "gpio44";
1321 function = "blsp_uart7";
1322 drive-strength = <2>;
1327 pins = "gpio42", "gpio43";
1328 function = "blsp_uart7";
1329 drive-strength = <2>;
1334 blsp2_uart1_sleep: blsp2-uart1-sleep {
1335 pins = "gpio41", "gpio42", "gpio43", "gpio44";
1337 drive-strength = <2>;
1341 blsp2_uart4_default: blsp2-uart4-default {
1343 pins = "gpio53", "gpio56";
1344 function = "blsp_uart10";
1345 drive-strength = <2>;
1350 pins = "gpio54", "gpio55";
1351 function = "blsp_uart10";
1352 drive-strength = <2>;
1357 blsp1_i2c1_default: blsp1-i2c1-default {
1358 pins = "gpio2", "gpio3";
1359 function = "blsp_i2c1";
1360 drive-strength = <2>;
1364 blsp1_i2c1_sleep: blsp1-i2c1-sleep {
1365 pins = "gpio2", "gpio3";
1366 function = "blsp_i2c1";
1367 drive-strength = <2>;
1371 blsp1_i2c2_default: blsp1-i2c2-default {
1372 pins = "gpio6", "gpio7";
1373 function = "blsp_i2c2";
1374 drive-strength = <2>;
1378 blsp1_i2c2_sleep: blsp1-i2c2-sleep {
1379 pins = "gpio6", "gpio7";
1380 function = "blsp_i2c2";
1381 drive-strength = <2>;
1385 blsp1_i2c3_default: blsp1-i2c3-default {
1386 pins = "gpio10", "gpio11";
1387 function = "blsp_i2c3";
1388 drive-strength = <2>;
1392 blsp1_i2c3_sleep: blsp1-i2c3-sleep {
1393 pins = "gpio10", "gpio11";
1394 function = "blsp_i2c3";
1395 drive-strength = <2>;
1399 /* BLSP1_I2C4 info is missing */
1401 /* BLSP1_I2C5 info is missing */
1403 blsp1_i2c6_default: blsp1-i2c6-default {
1404 pins = "gpio29", "gpio30";
1405 function = "blsp_i2c6";
1406 drive-strength = <2>;
1410 blsp1_i2c6_sleep: blsp1-i2c6-sleep {
1411 pins = "gpio29", "gpio30";
1412 function = "blsp_i2c6";
1413 drive-strength = <2>;
1416 /* 6 interfaces per QUP, BLSP2 indexes are numbered (n)+6 */
1418 /* BLSP2_I2C1 info is missing */
1420 blsp2_i2c2_default: blsp2-i2c2-default {
1421 pins = "gpio47", "gpio48";
1422 function = "blsp_i2c8";
1423 drive-strength = <2>;
1427 blsp2_i2c2_sleep: blsp2-i2c2-sleep {
1428 pins = "gpio47", "gpio48";
1429 function = "blsp_i2c8";
1430 drive-strength = <2>;
1434 /* BLSP2_I2C3 info is missing */
1436 /* BLSP2_I2C4 info is missing */
1438 blsp2_i2c5_default: blsp2-i2c5-default {
1439 pins = "gpio83", "gpio84";
1440 function = "blsp_i2c11";
1441 drive-strength = <2>;
1445 blsp2_i2c5_sleep: blsp2-i2c5-sleep {
1446 pins = "gpio83", "gpio84";
1447 function = "blsp_i2c11";
1448 drive-strength = <2>;
1452 blsp2_i2c6_default: blsp2-i2c6-default {
1453 pins = "gpio87", "gpio88";
1454 function = "blsp_i2c12";
1455 drive-strength = <2>;
1459 blsp2_i2c6_sleep: blsp2-i2c6-sleep {
1460 pins = "gpio87", "gpio88";
1461 function = "blsp_i2c12";
1462 drive-strength = <2>;
1466 spi8_default: spi8_default {
1469 function = "blsp_spi8";
1473 function = "blsp_spi8";
1477 function = "blsp_spi8";
1481 function = "blsp_spi8";
1486 mmcc: clock-controller@fd8c0000 {
1487 compatible = "qcom,mmcc-msm8974";
1490 #power-domain-cells = <1>;
1491 reg = <0xfd8c0000 0x6000>;
1494 mdss: mdss@fd900000 {
1495 compatible = "qcom,mdss";
1496 reg = <0xfd900000 0x100>, <0xfd924000 0x1000>;
1497 reg-names = "mdss_phys", "vbif_phys";
1499 power-domains = <&mmcc MDSS_GDSC>;
1501 clocks = <&mmcc MDSS_AHB_CLK>,
1502 <&mmcc MDSS_AXI_CLK>,
1503 <&mmcc MDSS_VSYNC_CLK>;
1504 clock-names = "iface", "bus", "vsync";
1506 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1508 interrupt-controller;
1509 #interrupt-cells = <1>;
1511 status = "disabled";
1513 #address-cells = <1>;
1518 compatible = "qcom,mdp5";
1519 reg = <0xfd900100 0x22000>;
1520 reg-names = "mdp_phys";
1522 interrupt-parent = <&mdss>;
1525 clocks = <&mmcc MDSS_AHB_CLK>,
1526 <&mmcc MDSS_AXI_CLK>,
1527 <&mmcc MDSS_MDP_CLK>,
1528 <&mmcc MDSS_VSYNC_CLK>;
1529 clock-names = "iface", "bus", "core", "vsync";
1531 interconnects = <&mmssnoc MNOC_MAS_MDP_PORT0 &bimc BIMC_SLV_EBI_CH0>;
1532 interconnect-names = "mdp0-mem";
1535 #address-cells = <1>;
1540 mdp5_intf1_out: endpoint {
1541 remote-endpoint = <&dsi0_in>;
1547 dsi0: dsi@fd922800 {
1548 compatible = "qcom,mdss-dsi-ctrl";
1549 reg = <0xfd922800 0x1f8>;
1550 reg-names = "dsi_ctrl";
1552 interrupt-parent = <&mdss>;
1555 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>;
1556 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
1558 clocks = <&mmcc MDSS_MDP_CLK>,
1559 <&mmcc MDSS_AHB_CLK>,
1560 <&mmcc MDSS_AXI_CLK>,
1561 <&mmcc MDSS_BYTE0_CLK>,
1562 <&mmcc MDSS_PCLK0_CLK>,
1563 <&mmcc MDSS_ESC0_CLK>,
1564 <&mmcc MMSS_MISC_AHB_CLK>;
1565 clock-names = "mdp_core",
1574 phy-names = "dsi-phy";
1576 status = "disabled";
1578 #address-cells = <1>;
1582 #address-cells = <1>;
1588 remote-endpoint = <&mdp5_intf1_out>;
1594 dsi0_out: endpoint {
1600 dsi0_phy: dsi-phy@fd922a00 {
1601 compatible = "qcom,dsi-phy-28nm-hpm";
1602 reg = <0xfd922a00 0xd4>,
1605 reg-names = "dsi_pll",
1607 "dsi_phy_regulator";
1612 clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>;
1613 clock-names = "iface", "ref";
1615 status = "disabled";
1619 gpu: adreno@fdb00000 {
1620 compatible = "qcom,adreno-330.1", "qcom,adreno";
1621 reg = <0xfdb00000 0x10000>;
1622 reg-names = "kgsl_3d0_reg_memory";
1624 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1625 interrupt-names = "kgsl_3d0_irq";
1627 clocks = <&mmcc OXILI_GFX3D_CLK>,
1628 <&mmcc OXILICX_AHB_CLK>,
1629 <&mmcc OXILICX_AXI_CLK>;
1630 clock-names = "core", "iface", "mem_iface";
1633 power-domains = <&mmcc OXILICX_GDSC>;
1634 operating-points-v2 = <&gpu_opp_table>;
1636 interconnects = <&mmssnoc MNOC_MAS_GRAPHICS_3D &bimc BIMC_SLV_EBI_CH0>,
1637 <&ocmemnoc OCMEM_VNOC_MAS_GFX3D &ocmemnoc OCMEM_SLV_OCMEM>;
1638 interconnect-names = "gfx-mem", "ocmem";
1640 // iommus = <&gpu_iommu 0>;
1642 status = "disabled";
1644 gpu_opp_table: opp-table {
1645 compatible = "operating-points-v2";
1648 opp-hz = /bits/ 64 <320000000>;
1652 opp-hz = /bits/ 64 <200000000>;
1656 opp-hz = /bits/ 64 <27000000>;
1662 compatible = "qcom,msm8974-ocmem";
1663 reg = <0xfdd00000 0x2000>,
1664 <0xfec00000 0x180000>;
1665 reg-names = "ctrl", "mem";
1666 ranges = <0 0xfec00000 0x180000>;
1667 clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
1668 <&mmcc OCMEMCX_OCMEMNOC_CLK>;
1669 clock-names = "core", "iface";
1671 #address-cells = <1>;
1674 gmu_sram: gmu-sram@0 {
1675 reg = <0x0 0x100000>;
1679 remoteproc_adsp: remoteproc@fe200000 {
1680 compatible = "qcom,msm8974-adsp-pil";
1681 reg = <0xfe200000 0x100>;
1683 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
1684 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1685 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1686 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1687 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1688 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
1690 clocks = <&xo_board>;
1693 memory-region = <&adsp_region>;
1695 qcom,smem-states = <&adsp_smp2p_out 0>;
1696 qcom,smem-state-names = "stop";
1698 status = "disabled";
1701 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
1703 qcom,ipc = <&apcs 8 8>;
1704 qcom,smd-edge = <1>;
1706 #address-cells = <1>;
1711 imem: sram@fe805000 {
1712 compatible = "qcom,msm8974-imem", "syscon", "simple-mfd";
1713 reg = <0xfe805000 0x1000>;
1716 compatible = "syscon-reboot-mode";
1722 tcsr_mutex: tcsr-mutex {
1723 compatible = "qcom,tcsr-mutex";
1724 syscon = <&tcsr_mutex_block 0 0x80>;
1726 #hwlock-cells = <1>;
1731 polling-delay-passive = <250>;
1732 polling-delay = <1000>;
1734 thermal-sensors = <&tsens 5>;
1738 temperature = <75000>;
1739 hysteresis = <2000>;
1743 temperature = <110000>;
1744 hysteresis = <2000>;
1751 polling-delay-passive = <250>;
1752 polling-delay = <1000>;
1754 thermal-sensors = <&tsens 6>;
1758 temperature = <75000>;
1759 hysteresis = <2000>;
1763 temperature = <110000>;
1764 hysteresis = <2000>;
1771 polling-delay-passive = <250>;
1772 polling-delay = <1000>;
1774 thermal-sensors = <&tsens 7>;
1778 temperature = <75000>;
1779 hysteresis = <2000>;
1783 temperature = <110000>;
1784 hysteresis = <2000>;
1791 polling-delay-passive = <250>;
1792 polling-delay = <1000>;
1794 thermal-sensors = <&tsens 8>;
1798 temperature = <75000>;
1799 hysteresis = <2000>;
1803 temperature = <110000>;
1804 hysteresis = <2000>;
1811 polling-delay-passive = <250>;
1812 polling-delay = <1000>;
1814 thermal-sensors = <&tsens 1>;
1817 q6_dsp_alert0: trip-point0 {
1818 temperature = <90000>;
1819 hysteresis = <2000>;
1826 polling-delay-passive = <250>;
1827 polling-delay = <1000>;
1829 thermal-sensors = <&tsens 2>;
1832 modemtx_alert0: trip-point0 {
1833 temperature = <90000>;
1834 hysteresis = <2000>;
1841 polling-delay-passive = <250>;
1842 polling-delay = <1000>;
1844 thermal-sensors = <&tsens 3>;
1847 video_alert0: trip-point0 {
1848 temperature = <95000>;
1849 hysteresis = <2000>;
1856 polling-delay-passive = <250>;
1857 polling-delay = <1000>;
1859 thermal-sensors = <&tsens 4>;
1862 wlan_alert0: trip-point0 {
1863 temperature = <105000>;
1864 hysteresis = <2000>;
1871 polling-delay-passive = <250>;
1872 polling-delay = <1000>;
1874 thermal-sensors = <&tsens 9>;
1877 gpu1_alert0: trip-point0 {
1878 temperature = <90000>;
1879 hysteresis = <2000>;
1885 gpu-bottom-thermal {
1886 polling-delay-passive = <250>;
1887 polling-delay = <1000>;
1889 thermal-sensors = <&tsens 10>;
1892 gpu2_alert0: trip-point0 {
1893 temperature = <90000>;
1894 hysteresis = <2000>;
1902 compatible = "arm,armv7-timer";
1903 interrupts = <GIC_PPI 2 0xf08>,
1907 clock-frequency = <19200000>;
1910 vreg_boost: vreg-boost {
1911 compatible = "regulator-fixed";
1913 regulator-name = "vreg-boost";
1914 regulator-min-microvolt = <3150000>;
1915 regulator-max-microvolt = <3150000>;
1917 regulator-always-on;
1920 gpio = <&pm8941_gpios 21 GPIO_ACTIVE_HIGH>;
1923 pinctrl-names = "default";
1924 pinctrl-0 = <&boost_bypass_n_pin>;
1927 vreg_vph_pwr: vreg-vph-pwr {
1928 compatible = "regulator-fixed";
1929 regulator-name = "vph-pwr";
1931 regulator-min-microvolt = <3600000>;
1932 regulator-max-microvolt = <3600000>;
1934 regulator-always-on;