1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
6 #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
7 #include <dt-bindings/clock/qcom,rpmcc.h>
8 #include <dt-bindings/reset/qcom,gcc-msm8974.h>
9 #include <dt-bindings/gpio/gpio.h>
14 model = "Qualcomm MSM8974";
15 compatible = "qcom,msm8974";
16 interrupt-parent = <&intc>;
24 reg = <0x08000000 0x5100000>;
29 reg = <0x0d100000 0x100000>;
34 reg = <0x0d200000 0xa00000>;
38 adsp_region: adsp@dc00000 {
39 reg = <0x0dc00000 0x1900000>;
44 reg = <0x0f500000 0x500000>;
48 smem_region: smem@fa00000 {
49 reg = <0xfa00000 0x200000>;
54 reg = <0x0fc00000 0x160000>;
59 reg = <0x0fd60000 0x20000>;
64 reg = <0x0fd80000 0x180000>;
72 interrupts = <GIC_PPI 9 0xf04>;
75 compatible = "qcom,krait";
76 enable-method = "qcom,kpss-acc-v2";
79 next-level-cache = <&L2>;
82 cpu-idle-states = <&CPU_SPC>;
86 compatible = "qcom,krait";
87 enable-method = "qcom,kpss-acc-v2";
90 next-level-cache = <&L2>;
93 cpu-idle-states = <&CPU_SPC>;
97 compatible = "qcom,krait";
98 enable-method = "qcom,kpss-acc-v2";
101 next-level-cache = <&L2>;
104 cpu-idle-states = <&CPU_SPC>;
108 compatible = "qcom,krait";
109 enable-method = "qcom,kpss-acc-v2";
112 next-level-cache = <&L2>;
115 cpu-idle-states = <&CPU_SPC>;
119 compatible = "cache";
121 qcom,saw = <&saw_l2>;
126 compatible = "qcom,idle-state-spc",
128 entry-latency-us = <150>;
129 exit-latency-us = <200>;
130 min-residency-us = <2000>;
136 device_type = "memory";
142 polling-delay-passive = <250>;
143 polling-delay = <1000>;
145 thermal-sensors = <&tsens 5>;
149 temperature = <75000>;
154 temperature = <110000>;
162 polling-delay-passive = <250>;
163 polling-delay = <1000>;
165 thermal-sensors = <&tsens 6>;
169 temperature = <75000>;
174 temperature = <110000>;
182 polling-delay-passive = <250>;
183 polling-delay = <1000>;
185 thermal-sensors = <&tsens 7>;
189 temperature = <75000>;
194 temperature = <110000>;
202 polling-delay-passive = <250>;
203 polling-delay = <1000>;
205 thermal-sensors = <&tsens 8>;
209 temperature = <75000>;
214 temperature = <110000>;
223 compatible = "qcom,krait-pmu";
224 interrupts = <GIC_PPI 7 0xf04>;
229 compatible = "fixed-clock";
231 clock-frequency = <19200000>;
234 sleep_clk: sleep_clk {
235 compatible = "fixed-clock";
237 clock-frequency = <32768>;
242 compatible = "arm,armv7-timer";
243 interrupts = <GIC_PPI 2 0xf08>,
247 clock-frequency = <19200000>;
251 compatible = "qcom,msm8974-adsp-pil";
253 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
254 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
255 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
256 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
257 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
258 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
260 cx-supply = <&pm8841_s2>;
262 clocks = <&xo_board>;
265 memory-region = <&adsp_region>;
267 qcom,smem-states = <&adsp_smp2p_out 0>;
268 qcom,smem-state-names = "stop";
272 compatible = "qcom,smem";
274 memory-region = <&smem_region>;
275 qcom,rpm-msg-ram = <&rpm_msg_ram>;
277 hwlocks = <&tcsr_mutex 3>;
281 compatible = "qcom,smp2p";
282 qcom,smem = <443>, <429>;
284 interrupt-parent = <&intc>;
285 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
287 qcom,ipc = <&apcs 8 10>;
289 qcom,local-pid = <0>;
290 qcom,remote-pid = <2>;
292 adsp_smp2p_out: master-kernel {
293 qcom,entry-name = "master-kernel";
294 #qcom,smem-state-cells = <1>;
297 adsp_smp2p_in: slave-kernel {
298 qcom,entry-name = "slave-kernel";
300 interrupt-controller;
301 #interrupt-cells = <2>;
306 compatible = "qcom,smp2p";
307 qcom,smem = <435>, <428>;
309 interrupt-parent = <&intc>;
310 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
312 qcom,ipc = <&apcs 8 14>;
314 qcom,local-pid = <0>;
315 qcom,remote-pid = <1>;
317 modem_smp2p_out: master-kernel {
318 qcom,entry-name = "master-kernel";
319 #qcom,smem-state-cells = <1>;
322 modem_smp2p_in: slave-kernel {
323 qcom,entry-name = "slave-kernel";
325 interrupt-controller;
326 #interrupt-cells = <2>;
331 compatible = "qcom,smp2p";
332 qcom,smem = <451>, <431>;
334 interrupt-parent = <&intc>;
335 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
337 qcom,ipc = <&apcs 8 18>;
339 qcom,local-pid = <0>;
340 qcom,remote-pid = <4>;
342 wcnss_smp2p_out: master-kernel {
343 qcom,entry-name = "master-kernel";
345 #qcom,smem-state-cells = <1>;
348 wcnss_smp2p_in: slave-kernel {
349 qcom,entry-name = "slave-kernel";
351 interrupt-controller;
352 #interrupt-cells = <2>;
357 compatible = "qcom,smsm";
359 #address-cells = <1>;
362 qcom,ipc-1 = <&apcs 8 13>;
363 qcom,ipc-2 = <&apcs 8 9>;
364 qcom,ipc-3 = <&apcs 8 19>;
369 #qcom,smem-state-cells = <1>;
372 modem_smsm: modem@1 {
374 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
376 interrupt-controller;
377 #interrupt-cells = <2>;
382 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
384 interrupt-controller;
385 #interrupt-cells = <2>;
388 wcnss_smsm: wcnss@7 {
390 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
392 interrupt-controller;
393 #interrupt-cells = <2>;
399 compatible = "qcom,scm";
400 clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
401 clock-names = "core", "bus", "iface";
406 #address-cells = <1>;
409 compatible = "simple-bus";
411 intc: interrupt-controller@f9000000 {
412 compatible = "qcom,msm-qgic2";
413 interrupt-controller;
414 #interrupt-cells = <3>;
415 reg = <0xf9000000 0x1000>,
419 apcs: syscon@f9011000 {
420 compatible = "syscon";
421 reg = <0xf9011000 0x1000>;
424 qfprom: qfprom@fc4bc000 {
425 #address-cells = <1>;
427 compatible = "qcom,qfprom";
428 reg = <0xfc4bc000 0x1000>;
429 tsens_calib: calib@d0 {
432 tsens_backup: backup@440 {
437 tsens: thermal-sensor@fc4a9000 {
438 compatible = "qcom,msm8974-tsens";
439 reg = <0xfc4a9000 0x1000>, /* TM */
440 <0xfc4a8000 0x1000>; /* SROT */
441 nvmem-cells = <&tsens_calib>, <&tsens_backup>;
442 nvmem-cell-names = "calib", "calib_backup";
443 #qcom,sensors = <11>;
444 #thermal-sensor-cells = <1>;
448 #address-cells = <1>;
451 compatible = "arm,armv7-timer-mem";
452 reg = <0xf9020000 0x1000>;
453 clock-frequency = <19200000>;
457 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
458 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
459 reg = <0xf9021000 0x1000>,
465 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
466 reg = <0xf9023000 0x1000>;
472 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
473 reg = <0xf9024000 0x1000>;
479 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
480 reg = <0xf9025000 0x1000>;
486 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
487 reg = <0xf9026000 0x1000>;
493 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
494 reg = <0xf9027000 0x1000>;
500 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
501 reg = <0xf9028000 0x1000>;
506 saw0: power-controller@f9089000 {
507 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
508 reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
511 saw1: power-controller@f9099000 {
512 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
513 reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
516 saw2: power-controller@f90a9000 {
517 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
518 reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
521 saw3: power-controller@f90b9000 {
522 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
523 reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
526 saw_l2: power-controller@f9012000 {
527 compatible = "qcom,saw2";
528 reg = <0xf9012000 0x1000>;
532 acc0: clock-controller@f9088000 {
533 compatible = "qcom,kpss-acc-v2";
534 reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
537 acc1: clock-controller@f9098000 {
538 compatible = "qcom,kpss-acc-v2";
539 reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
542 acc2: clock-controller@f90a8000 {
543 compatible = "qcom,kpss-acc-v2";
544 reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
547 acc3: clock-controller@f90b8000 {
548 compatible = "qcom,kpss-acc-v2";
549 reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
553 compatible = "qcom,pshold";
554 reg = <0xfc4ab000 0x4>;
557 gcc: clock-controller@fc400000 {
558 compatible = "qcom,gcc-msm8974";
561 #power-domain-cells = <1>;
562 reg = <0xfc400000 0x4000>;
565 tcsr: syscon@fd4a0000 {
566 compatible = "syscon";
567 reg = <0xfd4a0000 0x10000>;
570 tcsr_mutex_block: syscon@fd484000 {
571 compatible = "syscon";
572 reg = <0xfd484000 0x2000>;
575 mmcc: clock-controller@fd8c0000 {
576 compatible = "qcom,mmcc-msm8974";
579 #power-domain-cells = <1>;
580 reg = <0xfd8c0000 0x6000>;
583 tcsr_mutex: tcsr-mutex {
584 compatible = "qcom,tcsr-mutex";
585 syscon = <&tcsr_mutex_block 0 0x80>;
590 rpm_msg_ram: memory@fc428000 {
591 compatible = "qcom,rpm-msg-ram";
592 reg = <0xfc428000 0x4000>;
595 blsp1_uart1: serial@f991d000 {
596 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
597 reg = <0xf991d000 0x1000>;
598 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
599 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
600 clock-names = "core", "iface";
604 blsp1_uart2: serial@f991e000 {
605 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
606 reg = <0xf991e000 0x1000>;
607 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
608 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
609 clock-names = "core", "iface";
614 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
615 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
616 reg-names = "hc_mem", "core_mem";
617 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
618 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
619 interrupt-names = "hc_irq", "pwr_irq";
620 clocks = <&gcc GCC_SDCC1_APPS_CLK>,
621 <&gcc GCC_SDCC1_AHB_CLK>,
623 clock-names = "core", "iface", "xo";
628 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
629 reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
630 reg-names = "hc_mem", "core_mem";
631 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
632 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
633 interrupt-names = "hc_irq", "pwr_irq";
634 clocks = <&gcc GCC_SDCC3_APPS_CLK>,
635 <&gcc GCC_SDCC3_AHB_CLK>,
637 clock-names = "core", "iface", "xo";
642 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
643 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
644 reg-names = "hc_mem", "core_mem";
645 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
646 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
647 interrupt-names = "hc_irq", "pwr_irq";
648 clocks = <&gcc GCC_SDCC2_APPS_CLK>,
649 <&gcc GCC_SDCC2_AHB_CLK>,
651 clock-names = "core", "iface", "xo";
656 compatible = "qcom,ci-hdrc";
657 reg = <0xf9a55000 0x200>,
659 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
660 clocks = <&gcc GCC_USB_HS_AHB_CLK>,
661 <&gcc GCC_USB_HS_SYSTEM_CLK>;
662 clock-names = "iface", "core";
663 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
664 assigned-clock-rates = <75000000>;
665 resets = <&gcc GCC_USB_HS_BCR>;
666 reset-names = "core";
669 ahb-burst-config = <0>;
670 phy-names = "usb-phy";
676 compatible = "qcom,usb-hs-phy-msm8974",
679 clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
680 clock-names = "ref", "sleep";
681 resets = <&gcc GCC_USB2A_PHY_BCR>, <&otg 0>;
682 reset-names = "phy", "por";
687 compatible = "qcom,usb-hs-phy-msm8974",
690 clocks = <&xo_board>, <&gcc GCC_USB2B_PHY_SLEEP_CLK>;
691 clock-names = "ref", "sleep";
692 resets = <&gcc GCC_USB2B_PHY_BCR>, <&otg 1>;
693 reset-names = "phy", "por";
700 compatible = "qcom,prng";
701 reg = <0xf9bff000 0x200>;
702 clocks = <&gcc GCC_PRNG_AHB_CLK>;
703 clock-names = "core";
706 msmgpio: pinctrl@fd510000 {
707 compatible = "qcom,msm8974-pinctrl";
708 reg = <0xfd510000 0x4000>;
711 interrupt-controller;
712 #interrupt-cells = <2>;
713 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
718 compatible = "qcom,i2c-qup-v2.1.1";
719 reg = <0xf9923000 0x1000>;
720 interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
721 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
722 clock-names = "core", "iface";
723 #address-cells = <1>;
729 compatible = "qcom,i2c-qup-v2.1.1";
730 reg = <0xf9924000 0x1000>;
731 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
732 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
733 clock-names = "core", "iface";
734 #address-cells = <1>;
738 blsp_i2c3: i2c@f9925000 {
740 compatible = "qcom,i2c-qup-v2.1.1";
741 reg = <0xf9925000 0x1000>;
742 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
743 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
744 clock-names = "core", "iface";
745 #address-cells = <1>;
749 blsp_i2c8: i2c@f9964000 {
751 compatible = "qcom,i2c-qup-v2.1.1";
752 reg = <0xf9964000 0x1000>;
753 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
754 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
755 clock-names = "core", "iface";
756 #address-cells = <1>;
760 blsp_i2c11: i2c@f9967000 {
762 compatible = "qcom,i2c-qup-v2.1.1";
763 reg = <0xf9967000 0x1000>;
764 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
765 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
766 clock-names = "core", "iface";
767 #address-cells = <1>;
769 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
770 dma-names = "tx", "rx";
773 blsp_i2c12: i2c@f9968000 {
775 compatible = "qcom,i2c-qup-v2.1.1";
776 reg = <0xf9968000 0x1000>;
777 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
778 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
779 clock-names = "core", "iface";
780 #address-cells = <1>;
784 spmi_bus: spmi@fc4cf000 {
785 compatible = "qcom,spmi-pmic-arb";
786 reg-names = "core", "intr", "cnfg";
787 reg = <0xfc4cf000 0x1000>,
790 interrupt-names = "periph_irq";
791 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
794 #address-cells = <2>;
796 interrupt-controller;
797 #interrupt-cells = <4>;
800 blsp2_dma: dma-controller@f9944000 {
801 compatible = "qcom,bam-v1.4.0";
802 reg = <0xf9944000 0x19000>;
803 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
804 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
805 clock-names = "bam_clk";
811 compatible = "arm,coresight-tmc", "arm,primecell";
812 reg = <0xfc322000 0x1000>;
814 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
815 clock-names = "apb_pclk", "atclk";
820 remote-endpoint = <&replicator_out0>;
827 compatible = "arm,coresight-tpiu", "arm,primecell";
828 reg = <0xfc318000 0x1000>;
830 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
831 clock-names = "apb_pclk", "atclk";
836 remote-endpoint = <&replicator_out1>;
842 replicator@fc31c000 {
843 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
844 reg = <0xfc31c000 0x1000>;
846 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
847 clock-names = "apb_pclk", "atclk";
850 #address-cells = <1>;
855 replicator_out0: endpoint {
856 remote-endpoint = <&etr_in>;
861 replicator_out1: endpoint {
862 remote-endpoint = <&tpiu_in>;
869 replicator_in: endpoint {
870 remote-endpoint = <&etf_out>;
877 compatible = "arm,coresight-tmc", "arm,primecell";
878 reg = <0xfc307000 0x1000>;
880 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
881 clock-names = "apb_pclk", "atclk";
886 remote-endpoint = <&replicator_in>;
894 remote-endpoint = <&merger_out>;
901 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
902 reg = <0xfc31b000 0x1000>;
904 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
905 clock-names = "apb_pclk", "atclk";
908 #address-cells = <1>;
912 * Not described input ports:
913 * 0 - connected trought funnel to Audio, Modem and
914 * Resource and Power Manager CPU's
915 * 2...7 - not-connected
919 merger_in1: endpoint {
920 remote-endpoint = <&funnel1_out>;
927 merger_out: endpoint {
928 remote-endpoint = <&etf_in>;
935 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
936 reg = <0xfc31a000 0x1000>;
938 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
939 clock-names = "apb_pclk", "atclk";
942 #address-cells = <1>;
946 * Not described input ports:
948 * 1 - connected trought funnel to Multimedia CPU
949 * 2 - connected to Wireless CPU
953 * 7 - connected to STM
957 funnel1_in5: endpoint {
958 remote-endpoint = <&kpss_out>;
965 funnel1_out: endpoint {
966 remote-endpoint = <&merger_in1>;
972 funnel@fc345000 { /* KPSS funnel only 4 inputs are used */
973 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
974 reg = <0xfc345000 0x1000>;
976 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
977 clock-names = "apb_pclk", "atclk";
980 #address-cells = <1>;
986 remote-endpoint = <&etm0_out>;
992 remote-endpoint = <&etm1_out>;
998 remote-endpoint = <&etm2_out>;
1003 kpss_in3: endpoint {
1004 remote-endpoint = <&etm3_out>;
1011 kpss_out: endpoint {
1012 remote-endpoint = <&funnel1_in5>;
1019 compatible = "arm,coresight-etm4x", "arm,primecell";
1020 reg = <0xfc33c000 0x1000>;
1022 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1023 clock-names = "apb_pclk", "atclk";
1029 etm0_out: endpoint {
1030 remote-endpoint = <&kpss_in0>;
1037 compatible = "arm,coresight-etm4x", "arm,primecell";
1038 reg = <0xfc33d000 0x1000>;
1040 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1041 clock-names = "apb_pclk", "atclk";
1047 etm1_out: endpoint {
1048 remote-endpoint = <&kpss_in1>;
1055 compatible = "arm,coresight-etm4x", "arm,primecell";
1056 reg = <0xfc33e000 0x1000>;
1058 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1059 clock-names = "apb_pclk", "atclk";
1065 etm2_out: endpoint {
1066 remote-endpoint = <&kpss_in2>;
1073 compatible = "arm,coresight-etm4x", "arm,primecell";
1074 reg = <0xfc33f000 0x1000>;
1076 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1077 clock-names = "apb_pclk", "atclk";
1083 etm3_out: endpoint {
1084 remote-endpoint = <&kpss_in3>;
1090 mdss: mdss@fd900000 {
1091 status = "disabled";
1093 compatible = "qcom,mdss";
1094 reg = <0xfd900000 0x100>,
1095 <0xfd924000 0x1000>;
1096 reg-names = "mdss_phys",
1099 power-domains = <&mmcc MDSS_GDSC>;
1101 clocks = <&mmcc MDSS_AHB_CLK>,
1102 <&mmcc MDSS_AXI_CLK>,
1103 <&mmcc MDSS_VSYNC_CLK>;
1104 clock-names = "iface",
1108 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1110 interrupt-controller;
1111 #interrupt-cells = <1>;
1113 #address-cells = <1>;
1118 status = "disabled";
1120 compatible = "qcom,mdp5";
1121 reg = <0xfd900100 0x22000>;
1122 reg-names = "mdp_phys";
1124 interrupt-parent = <&mdss>;
1127 clocks = <&mmcc MDSS_AHB_CLK>,
1128 <&mmcc MDSS_AXI_CLK>,
1129 <&mmcc MDSS_MDP_CLK>,
1130 <&mmcc MDSS_VSYNC_CLK>;
1131 clock-names = "iface",
1137 #address-cells = <1>;
1142 mdp5_intf1_out: endpoint {
1143 remote-endpoint = <&dsi0_in>;
1149 dsi0: dsi@fd922800 {
1150 status = "disabled";
1152 compatible = "qcom,mdss-dsi-ctrl";
1153 reg = <0xfd922800 0x1f8>;
1154 reg-names = "dsi_ctrl";
1156 interrupt-parent = <&mdss>;
1157 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
1159 assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
1160 <&mmcc PCLK0_CLK_SRC>;
1161 assigned-clock-parents = <&dsi_phy0 0>,
1164 clocks = <&mmcc MDSS_MDP_CLK>,
1165 <&mmcc MDSS_AHB_CLK>,
1166 <&mmcc MDSS_AXI_CLK>,
1167 <&mmcc MDSS_BYTE0_CLK>,
1168 <&mmcc MDSS_PCLK0_CLK>,
1169 <&mmcc MDSS_ESC0_CLK>,
1170 <&mmcc MMSS_MISC_AHB_CLK>;
1171 clock-names = "mdp_core",
1180 phy-names = "dsi-phy";
1183 #address-cells = <1>;
1189 remote-endpoint = <&mdp5_intf1_out>;
1195 dsi0_out: endpoint {
1201 dsi_phy0: dsi-phy@fd922a00 {
1202 status = "disabled";
1204 compatible = "qcom,dsi-phy-28nm-hpm";
1205 reg = <0xfd922a00 0xd4>,
1208 reg-names = "dsi_pll",
1210 "dsi_phy_regulator";
1214 qcom,dsi-phy-index = <0>;
1216 clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>;
1217 clock-names = "iface", "ref";
1223 compatible = "qcom,smd";
1226 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
1228 qcom,ipc = <&apcs 8 8>;
1229 qcom,smd-edge = <1>;
1233 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
1235 qcom,ipc = <&apcs 8 12>;
1236 qcom,smd-edge = <0>;
1240 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
1241 qcom,ipc = <&apcs 8 0>;
1242 qcom,smd-edge = <15>;
1245 compatible = "qcom,rpm-msm8974";
1246 qcom,smd-channels = "rpm_requests";
1248 rpmcc: clock-controller {
1249 compatible = "qcom,rpmcc-msm8974", "qcom,rpmcc";
1254 compatible = "qcom,rpm-pm8841-regulators";
1267 compatible = "qcom,rpm-pm8941-regulators";
1298 pm8941_lvs1: lvs1 {};
1299 pm8941_lvs2: lvs2 {};
1300 pm8941_lvs3: lvs3 {};
1306 vreg_boost: vreg-boost {
1307 compatible = "regulator-fixed";
1309 regulator-name = "vreg-boost";
1310 regulator-min-microvolt = <3150000>;
1311 regulator-max-microvolt = <3150000>;
1313 regulator-always-on;
1316 gpio = <&pm8941_gpios 21 GPIO_ACTIVE_HIGH>;
1319 pinctrl-names = "default";
1320 pinctrl-0 = <&boost_bypass_n_pin>;
1322 vreg_vph_pwr: vreg-vph-pwr {
1323 compatible = "regulator-fixed";
1324 regulator-name = "vph-pwr";
1326 regulator-min-microvolt = <3600000>;
1327 regulator-max-microvolt = <3600000>;
1329 regulator-always-on;