3 #include <dt-bindings/interrupt-controller/arm-gic.h>
4 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
5 #include <dt-bindings/gpio/gpio.h>
6 #include "skeleton.dtsi"
9 model = "Qualcomm MSM8974";
10 compatible = "qcom,msm8974";
11 interrupt-parent = <&intc>;
19 reg = <0x08000000 0x5100000>;
24 reg = <0x0d100000 0x100000>;
29 reg = <0x0d200000 0xa00000>;
34 reg = <0x0dc00000 0x1900000>;
39 reg = <0x0f500000 0x500000>;
43 smem_region: smem@fa00000 {
44 reg = <0xfa00000 0x200000>;
49 reg = <0x0fc00000 0x160000>;
54 reg = <0x0fd60000 0x20000>;
59 reg = <0x0fd80000 0x180000>;
64 reg = <0x0ff00000 0x10100000>;
72 interrupts = <1 9 0xf04>;
75 compatible = "qcom,krait";
76 enable-method = "qcom,kpss-acc-v2";
79 next-level-cache = <&L2>;
82 cpu-idle-states = <&CPU_SPC>;
86 compatible = "qcom,krait";
87 enable-method = "qcom,kpss-acc-v2";
90 next-level-cache = <&L2>;
93 cpu-idle-states = <&CPU_SPC>;
97 compatible = "qcom,krait";
98 enable-method = "qcom,kpss-acc-v2";
101 next-level-cache = <&L2>;
104 cpu-idle-states = <&CPU_SPC>;
108 compatible = "qcom,krait";
109 enable-method = "qcom,kpss-acc-v2";
112 next-level-cache = <&L2>;
115 cpu-idle-states = <&CPU_SPC>;
119 compatible = "cache";
121 qcom,saw = <&saw_l2>;
126 compatible = "qcom,idle-state-spc",
128 entry-latency-us = <150>;
129 exit-latency-us = <200>;
130 min-residency-us = <2000>;
137 polling-delay-passive = <250>;
138 polling-delay = <1000>;
140 thermal-sensors = <&tsens 5>;
144 temperature = <75000>;
149 temperature = <110000>;
157 polling-delay-passive = <250>;
158 polling-delay = <1000>;
160 thermal-sensors = <&tsens 6>;
164 temperature = <75000>;
169 temperature = <110000>;
177 polling-delay-passive = <250>;
178 polling-delay = <1000>;
180 thermal-sensors = <&tsens 7>;
184 temperature = <75000>;
189 temperature = <110000>;
197 polling-delay-passive = <250>;
198 polling-delay = <1000>;
200 thermal-sensors = <&tsens 8>;
204 temperature = <75000>;
209 temperature = <110000>;
218 compatible = "qcom,krait-pmu";
219 interrupts = <1 7 0xf04>;
224 compatible = "fixed-clock";
226 clock-frequency = <19200000>;
230 compatible = "fixed-clock";
232 clock-frequency = <32768>;
237 compatible = "arm,armv7-timer";
238 interrupts = <1 2 0xf08>,
242 clock-frequency = <19200000>;
246 compatible = "qcom,smem";
248 memory-region = <&smem_region>;
249 qcom,rpm-msg-ram = <&rpm_msg_ram>;
251 hwlocks = <&tcsr_mutex 3>;
255 compatible = "qcom,smp2p";
256 qcom,smem = <435>, <428>;
258 interrupt-parent = <&intc>;
259 interrupts = <0 27 IRQ_TYPE_EDGE_RISING>;
261 qcom,ipc = <&apcs 8 14>;
263 qcom,local-pid = <0>;
264 qcom,remote-pid = <1>;
266 modem_smp2p_out: master-kernel {
267 qcom,entry-name = "master-kernel";
268 #qcom,smem-state-cells = <1>;
271 modem_smp2p_in: slave-kernel {
272 qcom,entry-name = "slave-kernel";
274 interrupt-controller;
275 #interrupt-cells = <2>;
280 compatible = "qcom,smp2p";
281 qcom,smem = <451>, <431>;
283 interrupt-parent = <&intc>;
284 interrupts = <0 143 IRQ_TYPE_EDGE_RISING>;
286 qcom,ipc = <&apcs 8 18>;
288 qcom,local-pid = <0>;
289 qcom,remote-pid = <4>;
291 wcnss_smp2p_out: master-kernel {
292 qcom,entry-name = "master-kernel";
294 #qcom,smem-state-cells = <1>;
297 wcnss_smp2p_in: slave-kernel {
298 qcom,entry-name = "slave-kernel";
300 interrupt-controller;
301 #interrupt-cells = <2>;
306 compatible = "qcom,smsm";
308 #address-cells = <1>;
311 qcom,ipc-1 = <&apcs 8 13>;
312 qcom,ipc-2 = <&apcs 8 9>;
313 qcom,ipc-3 = <&apcs 8 19>;
318 #qcom,smem-state-cells = <1>;
321 modem_smsm: modem@1 {
323 interrupts = <0 26 IRQ_TYPE_EDGE_RISING>;
325 interrupt-controller;
326 #interrupt-cells = <2>;
331 interrupts = <0 157 IRQ_TYPE_EDGE_RISING>;
333 interrupt-controller;
334 #interrupt-cells = <2>;
337 wcnss_smsm: wcnss@7 {
339 interrupts = <0 144 IRQ_TYPE_EDGE_RISING>;
341 interrupt-controller;
342 #interrupt-cells = <2>;
348 compatible = "qcom,scm";
349 clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
350 clock-names = "core", "bus", "iface";
355 #address-cells = <1>;
358 compatible = "simple-bus";
360 intc: interrupt-controller@f9000000 {
361 compatible = "qcom,msm-qgic2";
362 interrupt-controller;
363 #interrupt-cells = <3>;
364 reg = <0xf9000000 0x1000>,
368 apcs: syscon@f9011000 {
369 compatible = "syscon";
370 reg = <0xf9011000 0x1000>;
373 qfprom: qfprom@fc4bc000 {
374 #address-cells = <1>;
376 compatible = "qcom,qfprom";
377 reg = <0xfc4bc000 0x1000>;
378 tsens_calib: calib@d0 {
381 tsens_backup: backup@440 {
386 tsens: thermal-sensor@fc4a8000 {
387 compatible = "qcom,msm8974-tsens";
388 reg = <0xfc4a8000 0x2000>;
389 nvmem-cells = <&tsens_calib>, <&tsens_backup>;
390 nvmem-cell-names = "calib", "calib_backup";
391 #thermal-sensor-cells = <1>;
395 #address-cells = <1>;
398 compatible = "arm,armv7-timer-mem";
399 reg = <0xf9020000 0x1000>;
400 clock-frequency = <19200000>;
404 interrupts = <0 8 0x4>,
406 reg = <0xf9021000 0x1000>,
412 interrupts = <0 9 0x4>;
413 reg = <0xf9023000 0x1000>;
419 interrupts = <0 10 0x4>;
420 reg = <0xf9024000 0x1000>;
426 interrupts = <0 11 0x4>;
427 reg = <0xf9025000 0x1000>;
433 interrupts = <0 12 0x4>;
434 reg = <0xf9026000 0x1000>;
440 interrupts = <0 13 0x4>;
441 reg = <0xf9027000 0x1000>;
447 interrupts = <0 14 0x4>;
448 reg = <0xf9028000 0x1000>;
453 saw0: power-controller@f9089000 {
454 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
455 reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
458 saw1: power-controller@f9099000 {
459 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
460 reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
463 saw2: power-controller@f90a9000 {
464 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
465 reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
468 saw3: power-controller@f90b9000 {
469 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
470 reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
473 saw_l2: power-controller@f9012000 {
474 compatible = "qcom,saw2";
475 reg = <0xf9012000 0x1000>;
479 acc0: clock-controller@f9088000 {
480 compatible = "qcom,kpss-acc-v2";
481 reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
484 acc1: clock-controller@f9098000 {
485 compatible = "qcom,kpss-acc-v2";
486 reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
489 acc2: clock-controller@f90a8000 {
490 compatible = "qcom,kpss-acc-v2";
491 reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
494 acc3: clock-controller@f90b8000 {
495 compatible = "qcom,kpss-acc-v2";
496 reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
500 compatible = "qcom,pshold";
501 reg = <0xfc4ab000 0x4>;
504 gcc: clock-controller@fc400000 {
505 compatible = "qcom,gcc-msm8974";
508 #power-domain-cells = <1>;
509 reg = <0xfc400000 0x4000>;
512 tcsr_mutex_block: syscon@fd484000 {
513 compatible = "syscon";
514 reg = <0xfd484000 0x2000>;
517 mmcc: clock-controller@fd8c0000 {
518 compatible = "qcom,mmcc-msm8974";
521 #power-domain-cells = <1>;
522 reg = <0xfd8c0000 0x6000>;
525 tcsr_mutex: tcsr-mutex {
526 compatible = "qcom,tcsr-mutex";
527 syscon = <&tcsr_mutex_block 0 0x80>;
532 rpm_msg_ram: memory@fc428000 {
533 compatible = "qcom,rpm-msg-ram";
534 reg = <0xfc428000 0x4000>;
537 blsp1_uart1: serial@f991d000 {
538 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
539 reg = <0xf991d000 0x1000>;
540 interrupts = <0 107 0x0>;
541 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
542 clock-names = "core", "iface";
546 blsp1_uart2: serial@f991e000 {
547 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
548 reg = <0xf991e000 0x1000>;
549 interrupts = <0 108 0x0>;
550 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
551 clock-names = "core", "iface";
556 compatible = "qcom,sdhci-msm-v4";
557 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
558 reg-names = "hc_mem", "core_mem";
559 interrupts = <0 123 0>, <0 138 0>;
560 interrupt-names = "hc_irq", "pwr_irq";
561 clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
562 clock-names = "core", "iface";
567 compatible = "qcom,sdhci-msm-v4";
568 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
569 reg-names = "hc_mem", "core_mem";
570 interrupts = <0 125 0>, <0 221 0>;
571 interrupt-names = "hc_irq", "pwr_irq";
572 clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
573 clock-names = "core", "iface";
578 compatible = "qcom,prng";
579 reg = <0xf9bff000 0x200>;
580 clocks = <&gcc GCC_PRNG_AHB_CLK>;
581 clock-names = "core";
584 msmgpio: pinctrl@fd510000 {
585 compatible = "qcom,msm8974-pinctrl";
586 reg = <0xfd510000 0x4000>;
589 interrupt-controller;
590 #interrupt-cells = <2>;
591 interrupts = <0 208 0>;
596 compatible = "qcom,i2c-qup-v2.1.1";
597 reg = <0xf9924000 0x1000>;
598 interrupts = <0 96 IRQ_TYPE_NONE>;
599 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
600 clock-names = "core", "iface";
601 #address-cells = <1>;
605 blsp_i2c8: i2c@f9964000 {
607 compatible = "qcom,i2c-qup-v2.1.1";
608 reg = <0xf9964000 0x1000>;
609 interrupts = <0 102 IRQ_TYPE_NONE>;
610 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
611 clock-names = "core", "iface";
612 #address-cells = <1>;
616 blsp_i2c11: i2c@f9967000 {
618 compatible = "qcom,i2c-qup-v2.1.1";
619 reg = <0xf9967000 0x1000>;
620 interrupts = <0 105 IRQ_TYPE_NONE>;
621 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
622 clock-names = "core", "iface";
623 #address-cells = <1>;
625 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
626 dma-names = "tx", "rx";
629 spmi_bus: spmi@fc4cf000 {
630 compatible = "qcom,spmi-pmic-arb";
631 reg-names = "core", "intr", "cnfg";
632 reg = <0xfc4cf000 0x1000>,
635 interrupt-names = "periph_irq";
636 interrupts = <0 190 0>;
639 #address-cells = <2>;
641 interrupt-controller;
642 #interrupt-cells = <4>;
645 blsp2_dma: dma-controller@f9944000 {
646 compatible = "qcom,bam-v1.4.0";
647 reg = <0xf9944000 0x19000>;
648 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
649 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
650 clock-names = "bam_clk";
657 compatible = "qcom,smd";
660 interrupts = <0 25 IRQ_TYPE_EDGE_RISING>;
662 qcom,ipc = <&apcs 8 12>;
667 interrupts = <0 168 1>;
668 qcom,ipc = <&apcs 8 0>;
669 qcom,smd-edge = <15>;
672 compatible = "qcom,rpm-msm8974";
673 qcom,smd-channels = "rpm_requests";
676 compatible = "qcom,rpm-pm8841-regulators";
689 compatible = "qcom,rpm-pm8941-regulators";
721 pm8941_lvs1: lvs1 {};
722 pm8941_lvs2: lvs2 {};
723 pm8941_lvs3: lvs3 {};
725 pm8941_5vs1: 5vs1 {};
726 pm8941_5vs2: 5vs2 {};
732 vreg_boost: vreg-boost {
733 compatible = "regulator-fixed";
735 regulator-name = "vreg-boost";
736 regulator-min-microvolt = <3150000>;
737 regulator-max-microvolt = <3150000>;
742 gpio = <&pm8941_gpios 21 GPIO_ACTIVE_HIGH>;
745 pinctrl-names = "default";
746 pinctrl-0 = <&boost_bypass_n_pin>;
748 vreg_vph_pwr: vreg-vph-pwr {
749 compatible = "regulator-fixed";
750 regulator-name = "vph-pwr";
752 regulator-min-microvolt = <3600000>;
753 regulator-max-microvolt = <3600000>;