arch/arm/boot/dts/qcom-msm8974.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /dts-v1/;
   3
   4 #include <dt-bindings/interconnect/qcom,msm8974.h>
   5 #include <dt-bindings/interrupt-controller/arm-gic.h>
   6 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
   7 #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
   8 #include <dt-bindings/clock/qcom,rpmcc.h>
   9 #include <dt-bindings/reset/qcom,gcc-msm8974.h>
  10 #include <dt-bindings/gpio/gpio.h>
  11
  12 / {
  13         #address-cells = <1>;
  14         #size-cells = <1>;
  15         interrupt-parent = <&intc>;
  16
  17         clocks {
  18                 xo_board: xo_board {
  19                         compatible = "fixed-clock";
  20                         #clock-cells = <0>;
  21                         clock-frequency = <19200000>;
  22                 };
  23
  24                 sleep_clk: sleep_clk {
  25                         compatible = "fixed-clock";
  26                         #clock-cells = <0>;
  27                         clock-frequency = <32768>;
  28                 };
  29         };
  30
  31         cpus {
  32                 #address-cells = <1>;
  33                 #size-cells = <0>;
  34                 interrupts = <GIC_PPI 9 0xf04>;
  35
  36                 CPU0: cpu@0 {
  37                         compatible = "qcom,krait";
  38                         enable-method = "qcom,kpss-acc-v2";
  39                         device_type = "cpu";
  40                         reg = <0>;
  41                         next-level-cache = <&L2>;
  42                         qcom,acc = <&acc0>;
  43                         qcom,saw = <&saw0>;
  44                         cpu-idle-states = <&CPU_SPC>;
  45                 };
  46
  47                 CPU1: cpu@1 {
  48                         compatible = "qcom,krait";
  49                         enable-method = "qcom,kpss-acc-v2";
  50                         device_type = "cpu";
  51                         reg = <1>;
  52                         next-level-cache = <&L2>;
  53                         qcom,acc = <&acc1>;
  54                         qcom,saw = <&saw1>;
  55                         cpu-idle-states = <&CPU_SPC>;
  56                 };
  57
  58                 CPU2: cpu@2 {
  59                         compatible = "qcom,krait";
  60                         enable-method = "qcom,kpss-acc-v2";
  61                         device_type = "cpu";
  62                         reg = <2>;
  63                         next-level-cache = <&L2>;
  64                         qcom,acc = <&acc2>;
  65                         qcom,saw = <&saw2>;
  66                         cpu-idle-states = <&CPU_SPC>;
  67                 };
  68
  69                 CPU3: cpu@3 {
  70                         compatible = "qcom,krait";
  71                         enable-method = "qcom,kpss-acc-v2";
  72                         device_type = "cpu";
  73                         reg = <3>;
  74                         next-level-cache = <&L2>;
  75                         qcom,acc = <&acc3>;
  76                         qcom,saw = <&saw3>;
  77                         cpu-idle-states = <&CPU_SPC>;
  78                 };
  79
  80                 L2: l2-cache {
  81                         compatible = "cache";
  82                         cache-level = <2>;
  83                         qcom,saw = <&saw_l2>;
  84                 };
  85
  86                 idle-states {
  87                         CPU_SPC: spc {
  88                                 compatible = "qcom,idle-state-spc",
  89                                                 "arm,idle-state";
  90                                 entry-latency-us = <150>;
  91                                 exit-latency-us = <200>;
  92                                 min-residency-us = <2000>;
  93                         };
  94                 };
  95         };
  96
  97         firmware {
  98                 scm {
  99                         compatible = "qcom,scm";
 100                         clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
 101                         clock-names = "core", "bus", "iface";
 102                 };
 103         };
 104
 105         memory {
 106                 device_type = "memory";
 107                 reg = <0x0 0x0>;
 108         };
 109
 110         pmu {
 111                 compatible = "qcom,krait-pmu";
 112                 interrupts = <GIC_PPI 7 0xf04>;
 113         };
 114
 115         reserved-memory {
 116                 #address-cells = <1>;
 117                 #size-cells = <1>;
 118                 ranges;
 119
 120                 mpss_region: mpss@8000000 {
 121                         reg = <0x08000000 0x5100000>;
 122                         no-map;
 123                 };
 124
 125                 mba_region: mba@d100000 {
 126                         reg = <0x0d100000 0x100000>;
 127                         no-map;
 128                 };
 129
 130                 wcnss_region: wcnss@d200000 {
 131                         reg = <0x0d200000 0xa00000>;
 132                         no-map;
 133                 };
 134
 135                 adsp_region: adsp@dc00000 {
 136                         reg = <0x0dc00000 0x1900000>;
 137                         no-map;
 138                 };
 139
 140                 venus_region: memory@f500000 {
 141                         reg = <0x0f500000 0x500000>;
 142                         no-map;
 143                 };
 144
 145                 smem_region: smem@fa00000 {
 146                         reg = <0xfa00000 0x200000>;
 147                         no-map;
 148                 };
 149
 150                 tz_region: memory@fc00000 {
 151                         reg = <0x0fc00000 0x160000>;
 152                         no-map;
 153                 };
 154
 155                 rfsa_mem: memory@fd60000 {
 156                         reg = <0x0fd60000 0x20000>;
 157                         no-map;
 158                 };
 159
 160                 rmtfs@fd80000 {
 161                         compatible = "qcom,rmtfs-mem";
 162                         reg = <0x0fd80000 0x180000>;
 163                         no-map;
 164
 165                         qcom,client-id = <1>;
 166                 };
 167         };
 168
 169         smem {
 170                 compatible = "qcom,smem";
 171
 172                 memory-region = <&smem_region>;
 173                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
 174
 175                 hwlocks = <&tcsr_mutex 3>;
 176         };
 177
 178         smp2p-adsp {
 179                 compatible = "qcom,smp2p";
 180                 qcom,smem = <443>, <429>;
 181
 182                 interrupt-parent = <&intc>;
 183                 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
 184
 185                 qcom,ipc = <&apcs 8 10>;
 186
 187                 qcom,local-pid = <0>;
 188                 qcom,remote-pid = <2>;
 189
 190                 adsp_smp2p_out: master-kernel {
 191                         qcom,entry-name = "master-kernel";
 192                         #qcom,smem-state-cells = <1>;
 193                 };
 194
 195                 adsp_smp2p_in: slave-kernel {
 196                         qcom,entry-name = "slave-kernel";
 197
 198                         interrupt-controller;
 199                         #interrupt-cells = <2>;
 200                 };
 201         };
 202
 203         smp2p-modem {
 204                 compatible = "qcom,smp2p";
 205                 qcom,smem = <435>, <428>;
 206
 207                 interrupt-parent = <&intc>;
 208                 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
 209
 210                 qcom,ipc = <&apcs 8 14>;
 211
 212                 qcom,local-pid = <0>;
 213                 qcom,remote-pid = <1>;
 214
 215                 modem_smp2p_out: master-kernel {
 216                         qcom,entry-name = "master-kernel";
 217                         #qcom,smem-state-cells = <1>;
 218                 };
 219
 220                 modem_smp2p_in: slave-kernel {
 221                         qcom,entry-name = "slave-kernel";
 222
 223                         interrupt-controller;
 224                         #interrupt-cells = <2>;
 225                 };
 226         };
 227
 228         smp2p-wcnss {
 229                 compatible = "qcom,smp2p";
 230                 qcom,smem = <451>, <431>;
 231
 232                 interrupt-parent = <&intc>;
 233                 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
 234
 235                 qcom,ipc = <&apcs 8 18>;
 236
 237                 qcom,local-pid = <0>;
 238                 qcom,remote-pid = <4>;
 239
 240                 wcnss_smp2p_out: master-kernel {
 241                         qcom,entry-name = "master-kernel";
 242
 243                         #qcom,smem-state-cells = <1>;
 244                 };
 245
 246                 wcnss_smp2p_in: slave-kernel {
 247                         qcom,entry-name = "slave-kernel";
 248
 249                         interrupt-controller;
 250                         #interrupt-cells = <2>;
 251                 };
 252         };
 253
 254         smsm {
 255                 compatible = "qcom,smsm";
 256
 257                 #address-cells = <1>;
 258                 #size-cells = <0>;
 259
 260                 qcom,ipc-1 = <&apcs 8 13>;
 261                 qcom,ipc-2 = <&apcs 8 9>;
 262                 qcom,ipc-3 = <&apcs 8 19>;
 263
 264                 apps_smsm: apps@0 {
 265                         reg = <0>;
 266
 267                         #qcom,smem-state-cells = <1>;
 268                 };
 269
 270                 modem_smsm: modem@1 {
 271                         reg = <1>;
 272                         interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
 273
 274                         interrupt-controller;
 275                         #interrupt-cells = <2>;
 276                 };
 277
 278                 adsp_smsm: adsp@2 {
 279                         reg = <2>;
 280                         interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
 281
 282                         interrupt-controller;
 283                         #interrupt-cells = <2>;
 284                 };
 285
 286                 wcnss_smsm: wcnss@7 {
 287                         reg = <7>;
 288                         interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
 289
 290                         interrupt-controller;
 291                         #interrupt-cells = <2>;
 292                 };
 293         };
 294
 295         smd {
 296                 compatible = "qcom,smd";
 297
 298                 rpm {
 299                         interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
 300                         qcom,ipc = <&apcs 8 0>;
 301                         qcom,smd-edge = <15>;
 302
 303                         rpm_requests: rpm_requests {
 304                                 compatible = "qcom,rpm-msm8974";
 305                                 qcom,smd-channels = "rpm_requests";
 306
 307                                 rpmcc: clock-controller {
 308                                         compatible = "qcom,rpmcc-msm8974", "qcom,rpmcc";
 309                                         #clock-cells = <1>;
 310                                 };
 311                         };
 312                 };
 313         };
 314
 315         soc: soc {
 316                 #address-cells = <1>;
 317                 #size-cells = <1>;
 318                 ranges;
 319                 compatible = "simple-bus";
 320
 321                 intc: interrupt-controller@f9000000 {
 322                         compatible = "qcom,msm-qgic2";
 323                         interrupt-controller;
 324                         #interrupt-cells = <3>;
 325                         reg = <0xf9000000 0x1000>,
 326                               <0xf9002000 0x1000>;
 327                 };
 328
 329                 apcs: syscon@f9011000 {
 330                         compatible = "syscon";
 331                         reg = <0xf9011000 0x1000>;
 332                 };
 333
 334                 timer@f9020000 {
 335                         #address-cells = <1>;
 336                         #size-cells = <1>;
 337                         ranges;
 338                         compatible = "arm,armv7-timer-mem";
 339                         reg = <0xf9020000 0x1000>;
 340                         clock-frequency = <19200000>;
 341
 342                         frame@f9021000 {
 343                                 frame-number = <0>;
 344                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 345                                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 346                                 reg = <0xf9021000 0x1000>,
 347                                       <0xf9022000 0x1000>;
 348                         };
 349
 350                         frame@f9023000 {
 351                                 frame-number = <1>;
 352                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 353                                 reg = <0xf9023000 0x1000>;
 354                                 status = "disabled";
 355                         };
 356
 357                         frame@f9024000 {
 358                                 frame-number = <2>;
 359                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 360                                 reg = <0xf9024000 0x1000>;
 361                                 status = "disabled";
 362                         };
 363
 364                         frame@f9025000 {
 365                                 frame-number = <3>;
 366                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 367                                 reg = <0xf9025000 0x1000>;
 368                                 status = "disabled";
 369                         };
 370
 371                         frame@f9026000 {
 372                                 frame-number = <4>;
 373                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 374                                 reg = <0xf9026000 0x1000>;
 375                                 status = "disabled";
 376                         };
 377
 378                         frame@f9027000 {
 379                                 frame-number = <5>;
 380                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 381                                 reg = <0xf9027000 0x1000>;
 382                                 status = "disabled";
 383                         };
 384
 385                         frame@f9028000 {
 386                                 frame-number = <6>;
 387                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 388                                 reg = <0xf9028000 0x1000>;
 389                                 status = "disabled";
 390                         };
 391                 };
 392
 393                 saw0: power-controller@f9089000 {
 394                         compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
 395                         reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
 396                 };
 397
 398                 saw1: power-controller@f9099000 {
 399                         compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
 400                         reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
 401                 };
 402
 403                 saw2: power-controller@f90a9000 {
 404                         compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
 405                         reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
 406                 };
 407
 408                 saw3: power-controller@f90b9000 {
 409                         compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
 410                         reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
 411                 };
 412
 413                 saw_l2: power-controller@f9012000 {
 414                         compatible = "qcom,saw2";
 415                         reg = <0xf9012000 0x1000>;
 416                         regulator;
 417                 };
 418
 419                 acc0: clock-controller@f9088000 {
 420                         compatible = "qcom,kpss-acc-v2";
 421                         reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
 422                 };
 423
 424                 acc1: clock-controller@f9098000 {
 425                         compatible = "qcom,kpss-acc-v2";
 426                         reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
 427                 };
 428
 429                 acc2: clock-controller@f90a8000 {
 430                         compatible = "qcom,kpss-acc-v2";
 431                         reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
 432                 };
 433
 434                 acc3: clock-controller@f90b8000 {
 435                         compatible = "qcom,kpss-acc-v2";
 436                         reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
 437                 };
 438
 439                 sdhc_1: sdhci@f9824900 {
 440                         compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
 441                         reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
 442                         reg-names = "hc_mem", "core_mem";
 443                         interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 444                                      <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
 445                         interrupt-names = "hc_irq", "pwr_irq";
 446                         clocks = <&gcc GCC_SDCC1_APPS_CLK>,
 447                                  <&gcc GCC_SDCC1_AHB_CLK>,
 448                                  <&xo_board>;
 449                         clock-names = "core", "iface", "xo";
 450                         bus-width = <8>;
 451                         non-removable;
 452
 453                         status = "disabled";
 454                 };
 455
 456                 sdhc_3: sdhci@f9864900 {
 457                         compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
 458                         reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
 459                         reg-names = "hc_mem", "core_mem";
 460                         interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
 461                                      <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
 462                         interrupt-names = "hc_irq", "pwr_irq";
 463                         clocks = <&gcc GCC_SDCC3_APPS_CLK>,
 464                                  <&gcc GCC_SDCC3_AHB_CLK>,
 465                                  <&xo_board>;
 466                         clock-names = "core", "iface", "xo";
 467                         bus-width = <4>;
 468
 469                         #address-cells = <1>;
 470                         #size-cells = <0>;
 471
 472                         status = "disabled";
 473                 };
 474
 475                 sdhc_2: sdhci@f98a4900 {
 476                         compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
 477                         reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
 478                         reg-names = "hc_mem", "core_mem";
 479                         interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
 480                                      <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
 481                         interrupt-names = "hc_irq", "pwr_irq";
 482                         clocks = <&gcc GCC_SDCC2_APPS_CLK>,
 483                                  <&gcc GCC_SDCC2_AHB_CLK>,
 484                                  <&xo_board>;
 485                         clock-names = "core", "iface", "xo";
 486                         bus-width = <4>;
 487
 488                         #address-cells = <1>;
 489                         #size-cells = <0>;
 490
 491                         status = "disabled";
 492                 };
 493
 494                 blsp1_uart1: serial@f991d000 {
 495                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 496                         reg = <0xf991d000 0x1000>;
 497                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 498                         clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 499                         clock-names = "core", "iface";
 500                         status = "disabled";
 501                 };
 502
 503                 blsp1_uart2: serial@f991e000 {
 504                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 505                         reg = <0xf991e000 0x1000>;
 506                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 507                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 508                         clock-names = "core", "iface";
 509                         status = "disabled";
 510                 };
 511
 512                 blsp1_i2c1: i2c@f9923000 {
 513                         status = "disabled";
 514                         compatible = "qcom,i2c-qup-v2.1.1";
 515                         reg = <0xf9923000 0x1000>;
 516                         interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
 517                         clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 518                         clock-names = "core", "iface";
 519                         pinctrl-names = "default", "sleep";
 520                         pinctrl-0 = <&blsp1_i2c1_default>;
 521                         pinctrl-1 = <&blsp1_i2c1_sleep>;
 522                         #address-cells = <1>;
 523                         #size-cells = <0>;
 524                 };
 525
 526                 blsp1_i2c2: i2c@f9924000 {
 527                         status = "disabled";
 528                         compatible = "qcom,i2c-qup-v2.1.1";
 529                         reg = <0xf9924000 0x1000>;
 530                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 531                         clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 532                         clock-names = "core", "iface";
 533                         pinctrl-names = "default", "sleep";
 534                         pinctrl-0 = <&blsp1_i2c2_default>;
 535                         pinctrl-1 = <&blsp1_i2c2_sleep>;
 536                         #address-cells = <1>;
 537                         #size-cells = <0>;
 538                 };
 539
 540                 blsp1_i2c3: i2c@f9925000 {
 541                         status = "disabled";
 542                         compatible = "qcom,i2c-qup-v2.1.1";
 543                         reg = <0xf9925000 0x1000>;
 544                         interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
 545                         clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 546                         clock-names = "core", "iface";
 547                         pinctrl-names = "default", "sleep";
 548                         pinctrl-0 = <&blsp1_i2c3_default>;
 549                         pinctrl-1 = <&blsp1_i2c3_sleep>;
 550                         #address-cells = <1>;
 551                         #size-cells = <0>;
 552                 };
 553
 554                 blsp1_i2c6: i2c@f9928000 {
 555                         status = "disabled";
 556                         compatible = "qcom,i2c-qup-v2.1.1";
 557                         reg = <0xf9928000 0x1000>;
 558                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 559                         clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 560                         clock-names = "core", "iface";
 561                         pinctrl-names = "default", "sleep";
 562                         pinctrl-0 = <&blsp1_i2c6_default>;
 563                         pinctrl-1 = <&blsp1_i2c6_sleep>;
 564                         #address-cells = <1>;
 565                         #size-cells = <0>;
 566                 };
 567
 568                 blsp2_dma: dma-controller@f9944000 {
 569                         compatible = "qcom,bam-v1.4.0";
 570                         reg = <0xf9944000 0x19000>;
 571                         interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
 572                         clocks = <&gcc GCC_BLSP2_AHB_CLK>;
 573                         clock-names = "bam_clk";
 574                         #dma-cells = <1>;
 575                         qcom,ee = <0>;
 576                 };
 577
 578                 blsp2_uart1: serial@f995d000 {
 579                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 580                         reg = <0xf995d000 0x1000>;
 581                         interrupts = <GIC_SPI 113 IRQ_TYPE_NONE>;
 582                         clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
 583                         clock-names = "core", "iface";
 584                         status = "disabled";
 585                 };
 586
 587                 blsp2_uart2: serial@f995e000 {
 588                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 589                         reg = <0xf995e000 0x1000>;
 590                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 591                         clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
 592                         clock-names = "core", "iface";
 593                         status = "disabled";
 594                 };
 595
 596                 blsp2_uart4: serial@f9960000 {
 597                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 598                         reg = <0xf9960000 0x1000>;
 599                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 600                         clocks = <&gcc GCC_BLSP2_UART4_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
 601                         clock-names = "core", "iface";
 602                         status = "disabled";
 603                 };
 604
 605                 blsp2_i2c2: i2c@f9964000 {
 606                         status = "disabled";
 607                         compatible = "qcom,i2c-qup-v2.1.1";
 608                         reg = <0xf9964000 0x1000>;
 609                         interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 610                         clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
 611                         clock-names = "core", "iface";
 612                         pinctrl-names = "default", "sleep";
 613                         pinctrl-0 = <&blsp2_i2c2_default>;
 614                         pinctrl-1 = <&blsp2_i2c2_sleep>;
 615                         #address-cells = <1>;
 616                         #size-cells = <0>;
 617                 };
 618
 619                 blsp2_i2c5: i2c@f9967000 {
 620                         status = "disabled";
 621                         compatible = "qcom,i2c-qup-v2.1.1";
 622                         reg = <0xf9967000 0x1000>;
 623                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 624                         clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
 625                         clock-names = "core", "iface";
 626                         dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
 627                         dma-names = "tx", "rx";
 628                         pinctrl-names = "default", "sleep";
 629                         pinctrl-0 = <&blsp2_i2c5_default>;
 630                         pinctrl-1 = <&blsp2_i2c5_sleep>;
 631                         #address-cells = <1>;
 632                         #size-cells = <0>;
 633                 };
 634
 635                 blsp2_i2c6: i2c@f9968000 {
 636                         status = "disabled";
 637                         compatible = "qcom,i2c-qup-v2.1.1";
 638                         reg = <0xf9968000 0x1000>;
 639                         interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
 640                         clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
 641                         clock-names = "core", "iface";
 642                         #address-cells = <1>;
 643                         #size-cells = <0>;
 644                 };
 645
 646                 otg: usb@f9a55000 {
 647                         compatible = "qcom,ci-hdrc";
 648                         reg = <0xf9a55000 0x200>,
 649                               <0xf9a55200 0x200>;
 650                         interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
 651                         clocks = <&gcc GCC_USB_HS_AHB_CLK>,
 652                                  <&gcc GCC_USB_HS_SYSTEM_CLK>;
 653                         clock-names = "iface", "core";
 654                         assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
 655                         assigned-clock-rates = <75000000>;
 656                         resets = <&gcc GCC_USB_HS_BCR>;
 657                         reset-names = "core";
 658                         phy_type = "ulpi";
 659                         dr_mode = "otg";
 660                         ahb-burst-config = <0>;
 661                         phy-names = "usb-phy";
 662                         status = "disabled";
 663                         #reset-cells = <1>;
 664
 665                         ulpi {
 666                                 usb_hs1_phy: phy@a {
 667                                         compatible = "qcom,usb-hs-phy-msm8974",
 668                                                      "qcom,usb-hs-phy";
 669                                         #phy-cells = <0>;
 670                                         clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
 671                                         clock-names = "ref", "sleep";
 672                                         resets = <&gcc GCC_USB2A_PHY_BCR>, <&otg 0>;
 673                                         reset-names = "phy", "por";
 674                                         status = "disabled";
 675                                 };
 676
 677                                 usb_hs2_phy: phy@b {
 678                                         compatible = "qcom,usb-hs-phy-msm8974",
 679                                                      "qcom,usb-hs-phy";
 680                                         #phy-cells = <0>;
 681                                         clocks = <&xo_board>, <&gcc GCC_USB2B_PHY_SLEEP_CLK>;
 682                                         clock-names = "ref", "sleep";
 683                                         resets = <&gcc GCC_USB2B_PHY_BCR>, <&otg 1>;
 684                                         reset-names = "phy", "por";
 685                                         status = "disabled";
 686                                 };
 687                         };
 688                 };
 689
 690                 rng@f9bff000 {
 691                         compatible = "qcom,prng";
 692                         reg = <0xf9bff000 0x200>;
 693                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 694                         clock-names = "core";
 695                 };
 696
 697                 pronto: remoteproc@fb21b000 {
 698                         compatible = "qcom,pronto-v2-pil", "qcom,pronto";
 699                         reg = <0xfb204000 0x2000>, <0xfb202000 0x1000>, <0xfb21b000 0x3000>;
 700                         reg-names = "ccu", "dxe", "pmu";
 701
 702                         memory-region = <&wcnss_region>;
 703
 704                         interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
 705                                               <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
 706                                               <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
 707                                               <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
 708                                               <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
 709                         interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
 710
 711                         qcom,smem-states = <&wcnss_smp2p_out 0>;
 712                         qcom,smem-state-names = "stop";
 713
 714                         status = "disabled";
 715
 716                         iris {
 717                                 compatible = "qcom,wcn3680";
 718
 719                                 clocks = <&rpmcc RPM_SMD_CXO_A2>;
 720                                 clock-names = "xo";
 721                         };
 722
 723                         smd-edge {
 724                                 interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
 725
 726                                 qcom,ipc = <&apcs 8 17>;
 727                                 qcom,smd-edge = <6>;
 728
 729                                 wcnss {
 730                                         compatible = "qcom,wcnss";
 731                                         qcom,smd-channels = "WCNSS_CTRL";
 732                                         status = "disabled";
 733
 734                                         qcom,mmio = <&pronto>;
 735
 736                                         bt {
 737                                                 compatible = "qcom,wcnss-bt";
 738                                         };
 739
 740                                         wifi {
 741                                                 compatible = "qcom,wcnss-wlan";
 742
 743                                                 interrupts = <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>,
 744                                                              <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>;
 745                                                 interrupt-names = "tx", "rx";
 746
 747                                                 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
 748                                                 qcom,smem-state-names = "tx-enable",
 749                                                                         "tx-rings-empty";
 750                                         };
 751                                 };
 752                         };
 753                 };
 754
 755                 etf@fc307000 {
 756                         compatible = "arm,coresight-tmc", "arm,primecell";
 757                         reg = <0xfc307000 0x1000>;
 758
 759                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
 760                         clock-names = "apb_pclk", "atclk";
 761
 762                         out-ports {
 763                                 port {
 764                                         etf_out: endpoint {
 765                                                 remote-endpoint = <&replicator_in>;
 766                                         };
 767                                 };
 768                         };
 769
 770                         in-ports {
 771                                 port {
 772                                         etf_in: endpoint {
 773                                                 remote-endpoint = <&merger_out>;
 774                                         };
 775                                 };
 776                         };
 777                 };
 778
 779                 tpiu@fc318000 {
 780                         compatible = "arm,coresight-tpiu", "arm,primecell";
 781                         reg = <0xfc318000 0x1000>;
 782
 783                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
 784                         clock-names = "apb_pclk", "atclk";
 785
 786                         in-ports {
 787                                 port {
 788                                         tpiu_in: endpoint {
 789                                                 remote-endpoint = <&replicator_out1>;
 790                                         };
 791                                  };
 792                         };
 793                 };
 794
 795                 funnel@fc31a000 {
 796                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 797                         reg = <0xfc31a000 0x1000>;
 798
 799                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
 800                         clock-names = "apb_pclk", "atclk";
 801
 802                         in-ports {
 803                                 #address-cells = <1>;
 804                                 #size-cells = <0>;
 805
 806                                 /*
 807                                  * Not described input ports:
 808                                  * 0 - not-connected
 809                                  * 1 - connected trought funnel to Multimedia CPU
 810                                  * 2 - connected to Wireless CPU
 811                                  * 3 - not-connected
 812                                  * 4 - not-connected
 813                                  * 6 - not-connected
 814                                  * 7 - connected to STM
 815                                  */
 816                                 port@5 {
 817                                         reg = <5>;
 818                                         funnel1_in5: endpoint {
 819                                                 remote-endpoint = <&kpss_out>;
 820                                         };
 821                                 };
 822                         };
 823
 824                         out-ports {
 825                                 port {
 826                                         funnel1_out: endpoint {
 827                                                 remote-endpoint = <&merger_in1>;
 828                                         };
 829                                 };
 830                         };
 831                 };
 832
 833                 funnel@fc31b000 {
 834                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 835                         reg = <0xfc31b000 0x1000>;
 836
 837                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
 838                         clock-names = "apb_pclk", "atclk";
 839
 840                         in-ports {
 841                                 #address-cells = <1>;
 842                                 #size-cells = <0>;
 843
 844                                 /*
 845                                  * Not described input ports:
 846                                  * 0 - connected trought funnel to Audio, Modem and
 847                                  *     Resource and Power Manager CPU's
 848                                  * 2...7 - not-connected
 849                                  */
 850                                 port@1 {
 851                                         reg = <1>;
 852                                         merger_in1: endpoint {
 853                                                 remote-endpoint = <&funnel1_out>;
 854                                         };
 855                                 };
 856                         };
 857
 858                         out-ports {
 859                                 port {
 860                                         merger_out: endpoint {
 861                                                 remote-endpoint = <&etf_in>;
 862                                         };
 863                                 };
 864                         };
 865                 };
 866
 867                 replicator@fc31c000 {
 868                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
 869                         reg = <0xfc31c000 0x1000>;
 870
 871                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
 872                         clock-names = "apb_pclk", "atclk";
 873
 874                         out-ports {
 875                                 #address-cells = <1>;
 876                                 #size-cells = <0>;
 877
 878                                 port@0 {
 879                                         reg = <0>;
 880                                         replicator_out0: endpoint {
 881                                                 remote-endpoint = <&etr_in>;
 882                                         };
 883                                 };
 884                                 port@1 {
 885                                         reg = <1>;
 886                                         replicator_out1: endpoint {
 887                                                 remote-endpoint = <&tpiu_in>;
 888                                         };
 889                                 };
 890                         };
 891
 892                         in-ports {
 893                                 port {
 894                                         replicator_in: endpoint {
 895                                                 remote-endpoint = <&etf_out>;
 896                                         };
 897                                 };
 898                         };
 899                 };
 900
 901                 etr@fc322000 {
 902                         compatible = "arm,coresight-tmc", "arm,primecell";
 903                         reg = <0xfc322000 0x1000>;
 904
 905                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
 906                         clock-names = "apb_pclk", "atclk";
 907
 908                         in-ports {
 909                                 port {
 910                                         etr_in: endpoint {
 911                                                 remote-endpoint = <&replicator_out0>;
 912                                         };
 913                                 };
 914                         };
 915                 };
 916
 917                 etm@fc33c000 {
 918                         compatible = "arm,coresight-etm4x", "arm,primecell";
 919                         reg = <0xfc33c000 0x1000>;
 920
 921                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
 922                         clock-names = "apb_pclk", "atclk";
 923
 924                         cpu = <&CPU0>;
 925
 926                         out-ports {
 927                                 port {
 928                                         etm0_out: endpoint {
 929                                                 remote-endpoint = <&kpss_in0>;
 930                                         };
 931                                 };
 932                         };
 933                 };
 934
 935                 etm@fc33d000 {
 936                         compatible = "arm,coresight-etm4x", "arm,primecell";
 937                         reg = <0xfc33d000 0x1000>;
 938
 939                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
 940                         clock-names = "apb_pclk", "atclk";
 941
 942                         cpu = <&CPU1>;
 943
 944                         out-ports {
 945                                 port {
 946                                         etm1_out: endpoint {
 947                                                 remote-endpoint = <&kpss_in1>;
 948                                         };
 949                                 };
 950                         };
 951                 };
 952
 953                 etm@fc33e000 {
 954                         compatible = "arm,coresight-etm4x", "arm,primecell";
 955                         reg = <0xfc33e000 0x1000>;
 956
 957                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
 958                         clock-names = "apb_pclk", "atclk";
 959
 960                         cpu = <&CPU2>;
 961
 962                         out-ports {
 963                                 port {
 964                                         etm2_out: endpoint {
 965                                                 remote-endpoint = <&kpss_in2>;
 966                                         };
 967                                 };
 968                         };
 969                 };
 970
 971                 etm@fc33f000 {
 972                         compatible = "arm,coresight-etm4x", "arm,primecell";
 973                         reg = <0xfc33f000 0x1000>;
 974
 975                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
 976                         clock-names = "apb_pclk", "atclk";
 977
 978                         cpu = <&CPU3>;
 979
 980                         out-ports {
 981                                 port {
 982                                         etm3_out: endpoint {
 983                                                 remote-endpoint = <&kpss_in3>;
 984                                         };
 985                                 };
 986                         };
 987                 };
 988
 989                 /* KPSS funnel, only 4 inputs are used */
 990                 funnel@fc345000 {
 991                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 992                         reg = <0xfc345000 0x1000>;
 993
 994                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
 995                         clock-names = "apb_pclk", "atclk";
 996
 997                         in-ports {
 998                                 #address-cells = <1>;
 999                                 #size-cells = <0>;
1000
1001                                 port@0 {
1002                                         reg = <0>;
1003                                         kpss_in0: endpoint {
1004                                                 remote-endpoint = <&etm0_out>;
1005                                         };
1006                                 };
1007                                 port@1 {
1008                                         reg = <1>;
1009                                         kpss_in1: endpoint {
1010                                                 remote-endpoint = <&etm1_out>;
1011                                         };
1012                                 };
1013                                 port@2 {
1014                                         reg = <2>;
1015                                         kpss_in2: endpoint {
1016                                                 remote-endpoint = <&etm2_out>;
1017                                         };
1018                                 };
1019                                 port@3 {
1020                                         reg = <3>;
1021                                         kpss_in3: endpoint {
1022                                                 remote-endpoint = <&etm3_out>;
1023                                         };
1024                                 };
1025                         };
1026
1027                         out-ports {
1028                                 port {
1029                                         kpss_out: endpoint {
1030                                                 remote-endpoint = <&funnel1_in5>;
1031                                         };
1032                                 };
1033                         };
1034                 };
1035
1036                 gcc: clock-controller@fc400000 {
1037                         compatible = "qcom,gcc-msm8974";
1038                         #clock-cells = <1>;
1039                         #reset-cells = <1>;
1040                         #power-domain-cells = <1>;
1041                         reg = <0xfc400000 0x4000>;
1042                 };
1043
1044                 rpm_msg_ram: memory@fc428000 {
1045                         compatible = "qcom,rpm-msg-ram";
1046                         reg = <0xfc428000 0x4000>;
1047                 };
1048
1049                 bimc: interconnect@fc380000 {
1050                         reg = <0xfc380000 0x6a000>;
1051                         compatible = "qcom,msm8974-bimc";
1052                         #interconnect-cells = <1>;
1053                         clock-names = "bus", "bus_a";
1054                         clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
1055                                  <&rpmcc RPM_SMD_BIMC_A_CLK>;
1056                 };
1057
1058                 snoc: interconnect@fc460000 {
1059                         reg = <0xfc460000 0x4000>;
1060                         compatible = "qcom,msm8974-snoc";
1061                         #interconnect-cells = <1>;
1062                         clock-names = "bus", "bus_a";
1063                         clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
1064                                  <&rpmcc RPM_SMD_SNOC_A_CLK>;
1065                 };
1066
1067                 pnoc: interconnect@fc468000 {
1068                         reg = <0xfc468000 0x4000>;
1069                         compatible = "qcom,msm8974-pnoc";
1070                         #interconnect-cells = <1>;
1071                         clock-names = "bus", "bus_a";
1072                         clocks = <&rpmcc RPM_SMD_PNOC_CLK>,
1073                                  <&rpmcc RPM_SMD_PNOC_A_CLK>;
1074                 };
1075
1076                 ocmemnoc: interconnect@fc470000 {
1077                         reg = <0xfc470000 0x4000>;
1078                         compatible = "qcom,msm8974-ocmemnoc";
1079                         #interconnect-cells = <1>;
1080                         clock-names = "bus", "bus_a";
1081                         clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
1082                                  <&rpmcc RPM_SMD_OCMEMGX_A_CLK>;
1083                 };
1084
1085                 mmssnoc: interconnect@fc478000 {
1086                         reg = <0xfc478000 0x4000>;
1087                         compatible = "qcom,msm8974-mmssnoc";
1088                         #interconnect-cells = <1>;
1089                         clock-names = "bus", "bus_a";
1090                         clocks = <&mmcc MMSS_S0_AXI_CLK>,
1091                                  <&mmcc MMSS_S0_AXI_CLK>;
1092                 };
1093
1094                 cnoc: interconnect@fc480000 {
1095                         reg = <0xfc480000 0x4000>;
1096                         compatible = "qcom,msm8974-cnoc";
1097                         #interconnect-cells = <1>;
1098                         clock-names = "bus", "bus_a";
1099                         clocks = <&rpmcc RPM_SMD_CNOC_CLK>,
1100                                  <&rpmcc RPM_SMD_CNOC_A_CLK>;
1101                 };
1102
1103                 tsens: thermal-sensor@fc4a9000 {
1104                         compatible = "qcom,msm8974-tsens";
1105                         reg = <0xfc4a9000 0x1000>, /* TM */
1106                               <0xfc4a8000 0x1000>; /* SROT */
1107                         nvmem-cells = <&tsens_calib>, <&tsens_backup>;
1108                         nvmem-cell-names = "calib", "calib_backup";
1109                         #qcom,sensors = <11>;
1110                         interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
1111                         interrupt-names = "uplow";
1112                         #thermal-sensor-cells = <1>;
1113                 };
1114
1115                 restart@fc4ab000 {
1116                         compatible = "qcom,pshold";
1117                         reg = <0xfc4ab000 0x4>;
1118                 };
1119
1120                 qfprom: qfprom@fc4bc000 {
1121                         #address-cells = <1>;
1122                         #size-cells = <1>;
1123                         compatible = "qcom,qfprom";
1124                         reg = <0xfc4bc000 0x1000>;
1125                         tsens_calib: calib@d0 {
1126                                 reg = <0xd0 0x18>;
1127                         };
1128                         tsens_backup: backup@440 {
1129                                 reg = <0x440 0x10>;
1130                         };
1131                 };
1132
1133                 spmi_bus: spmi@fc4cf000 {
1134                         compatible = "qcom,spmi-pmic-arb";
1135                         reg-names = "core", "intr", "cnfg";
1136                         reg = <0xfc4cf000 0x1000>,
1137                               <0xfc4cb000 0x1000>,
1138                               <0xfc4ca000 0x1000>;
1139                         interrupt-names = "periph_irq";
1140                         interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1141                         qcom,ee = <0>;
1142                         qcom,channel = <0>;
1143                         #address-cells = <2>;
1144                         #size-cells = <0>;
1145                         interrupt-controller;
1146                         #interrupt-cells = <4>;
1147                 };
1148
1149                 remoteproc_mss: remoteproc@fc880000 {
1150                         compatible = "qcom,msm8974-mss-pil";
1151                         reg = <0xfc880000 0x100>, <0xfc820000 0x020>;
1152                         reg-names = "qdsp6", "rmb";
1153
1154                         interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
1155                                               <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1156                                               <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1157                                               <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1158                                               <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1159                         interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
1160
1161                         clocks = <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
1162                                  <&gcc GCC_MSS_CFG_AHB_CLK>,
1163                                  <&gcc GCC_BOOT_ROM_AHB_CLK>,
1164                                  <&xo_board>;
1165                         clock-names = "iface", "bus", "mem", "xo";
1166
1167                         resets = <&gcc GCC_MSS_RESTART>;
1168                         reset-names = "mss_restart";
1169
1170                         qcom,halt-regs = <&tcsr_mutex_block 0x1180 0x1200 0x1280>;
1171
1172                         qcom,smem-states = <&modem_smp2p_out 0>;
1173                         qcom,smem-state-names = "stop";
1174
1175                         mba {
1176                                 memory-region = <&mba_region>;
1177                         };
1178
1179                         mpss {
1180                                 memory-region = <&mpss_region>;
1181                         };
1182
1183                         smd-edge {
1184                                 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
1185
1186                                 qcom,ipc = <&apcs 8 12>;
1187                                 qcom,smd-edge = <0>;
1188
1189                                 label = "modem";
1190                         };
1191                 };
1192
1193                 tcsr_mutex_block: syscon@fd484000 {
1194                         compatible = "syscon";
1195                         reg = <0xfd484000 0x2000>;
1196                 };
1197
1198                 tcsr: syscon@fd4a0000 {
1199                         compatible = "syscon";
1200                         reg = <0xfd4a0000 0x10000>;
1201                 };
1202
1203                 tlmm: pinctrl@fd510000 {
1204                         compatible = "qcom,msm8974-pinctrl";
1205                         reg = <0xfd510000 0x4000>;
1206                         gpio-controller;
1207                         gpio-ranges = <&tlmm 0 0 146>;
1208                         #gpio-cells = <2>;
1209                         interrupt-controller;
1210                         #interrupt-cells = <2>;
1211                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1212
1213                         sdc1_off: sdc1-off {
1214                                 clk {
1215                                         pins = "sdc1_clk";
1216                                         bias-disable;
1217                                         drive-strength = <2>;
1218                                 };
1219
1220                                 cmd {
1221                                         pins = "sdc1_cmd";
1222                                         bias-pull-up;
1223                                         drive-strength = <2>;
1224                                 };
1225
1226                                 data {
1227                                         pins = "sdc1_data";
1228                                         bias-pull-up;
1229                                         drive-strength = <2>;
1230                                 };
1231                         };
1232
1233                         sdc2_off: sdc2-off {
1234                                 clk {
1235                                         pins = "sdc2_clk";
1236                                         bias-disable;
1237                                         drive-strength = <2>;
1238                                 };
1239
1240                                 cmd {
1241                                         pins = "sdc2_cmd";
1242                                         bias-pull-up;
1243                                         drive-strength = <2>;
1244                                 };
1245
1246                                 data {
1247                                         pins = "sdc2_data";
1248                                         bias-pull-up;
1249                                         drive-strength = <2>;
1250                                 };
1251
1252                                 cd {
1253                                         pins = "gpio54";
1254                                         bias-disable;
1255                                         drive-strength = <2>;
1256                                 };
1257                         };
1258
1259                         blsp1_uart2_active: blsp1-uart2-active {
1260                                 rx {
1261                                         pins = "gpio5";
1262                                         function = "blsp_uart2";
1263                                         drive-strength = <2>;
1264                                         bias-pull-up;
1265                                 };
1266
1267                                 tx {
1268                                         pins = "gpio4";
1269                                         function = "blsp_uart2";
1270                                         drive-strength = <4>;
1271                                         bias-disable;
1272                                 };
1273                         };
1274
1275                         blsp2_uart1_active: blsp2-uart1-active {
1276                                 tx-rts {
1277                                         pins = "gpio41", "gpio44";
1278                                         function = "blsp_uart7";
1279                                         drive-strength = <2>;
1280                                         bias-disable;
1281                                 };
1282
1283                                 rx-cts {
1284                                         pins = "gpio42", "gpio43";
1285                                         function = "blsp_uart7";
1286                                         drive-strength = <2>;
1287                                         bias-pull-up;
1288                                 };
1289                         };
1290
1291                         blsp2_uart1_sleep: blsp2-uart1-sleep {
1292                                 pins = "gpio41", "gpio42", "gpio43", "gpio44";
1293                                 function = "gpio";
1294                                 drive-strength = <2>;
1295                                 bias-pull-down;
1296                         };
1297
1298                         blsp2_uart4_active: blsp2-uart4-active {
1299                                 tx-rts {
1300                                         pins = "gpio53", "gpio56";
1301                                         function = "blsp_uart10";
1302                                         drive-strength = <2>;
1303                                         bias-disable;
1304                                 };
1305
1306                                 rx-cts {
1307                                         pins = "gpio54", "gpio55";
1308                                         function = "blsp_uart10";
1309                                         drive-strength = <2>;
1310                                         bias-pull-up;
1311                                 };
1312                         };
1313
1314                         blsp1_i2c1_default: blsp1-i2c1-default {
1315                                 pins = "gpio2", "gpio3";
1316                                 function = "blsp_i2c1";
1317                                 drive-strength = <2>;
1318                                 bias-disable;
1319                         };
1320
1321                         blsp1_i2c1_sleep: blsp1-i2c1-sleep {
1322                                 pins = "gpio2", "gpio3";
1323                                 function = "blsp_i2c1";
1324                                 drive-strength = <2>;
1325                                 bias-pull-up;
1326                         };
1327
1328                         blsp1_i2c2_default: blsp1-i2c2-default {
1329                                 pins = "gpio6", "gpio7";
1330                                 function = "blsp_i2c2";
1331                                 drive-strength = <2>;
1332                                 bias-disable;
1333                         };
1334
1335                         blsp1_i2c2_sleep: blsp1-i2c2-sleep {
1336                                 pins = "gpio6", "gpio7";
1337                                 function = "blsp_i2c2";
1338                                 drive-strength = <2>;
1339                                 bias-pull-up;
1340                         };
1341
1342                         blsp1_i2c3_default: blsp1-i2c3-default {
1343                                 pins = "gpio10", "gpio11";
1344                                 function = "blsp_i2c3";
1345                                 drive-strength = <2>;
1346                                 bias-disable;
1347                         };
1348
1349                         blsp1_i2c3_sleep: blsp1-i2c3-sleep {
1350                                 pins = "gpio10", "gpio11";
1351                                 function = "blsp_i2c3";
1352                                 drive-strength = <2>;
1353                                 bias-pull-up;
1354                         };
1355
1356                         /* BLSP1_I2C4 info is missing */
1357
1358                         /* BLSP1_I2C5 info is missing */
1359
1360                         blsp1_i2c6_default: blsp1-i2c6-default {
1361                                 pins = "gpio29", "gpio30";
1362                                 function = "blsp_i2c6";
1363                                 drive-strength = <2>;
1364                                 bias-disable;
1365                         };
1366
1367                         blsp1_i2c6_sleep: blsp1-i2c6-sleep {
1368                                 pins = "gpio29", "gpio30";
1369                                 function = "blsp_i2c6";
1370                                 drive-strength = <2>;
1371                                 bias-pull-up;
1372                         };
1373                         /* 6 interfaces per QUP, BLSP2 indexes are numbered (n)+6 */
1374
1375                         /* BLSP2_I2C1 info is missing */
1376
1377                         blsp2_i2c2_default: blsp2-i2c2-default {
1378                                 pins = "gpio47", "gpio48";
1379                                 function = "blsp_i2c8";
1380                                 drive-strength = <2>;
1381                                 bias-disable;
1382                         };
1383
1384                         blsp2_i2c2_sleep: blsp2-i2c2-sleep {
1385                                 pins = "gpio47", "gpio48";
1386                                 function = "blsp_i2c8";
1387                                 drive-strength = <2>;
1388                                 bias-pull-up;
1389                         };
1390
1391                         /* BLSP2_I2C3 info is missing */
1392
1393                         /* BLSP2_I2C4 info is missing */
1394
1395                         blsp2_i2c5_default: blsp2-i2c5-default {
1396                                 pins = "gpio83", "gpio84";
1397                                 function = "blsp_i2c11";
1398                                 drive-strength = <2>;
1399                                 bias-disable;
1400                         };
1401
1402                         blsp2_i2c5_sleep: blsp2-i2c5-sleep {
1403                                 pins = "gpio83", "gpio84";
1404                                 function = "blsp_i2c11";
1405                                 drive-strength = <2>;
1406                                 bias-pull-up;
1407                         };
1408
1409                         /* BLSP2_I2C6 info is missing - nobody uses it though? */
1410
1411                         spi8_default: spi8_default {
1412                                 mosi {
1413                                         pins = "gpio45";
1414                                         function = "blsp_spi8";
1415                                 };
1416                                 miso {
1417                                         pins = "gpio46";
1418                                         function = "blsp_spi8";
1419                                 };
1420                                 cs {
1421                                         pins = "gpio47";
1422                                         function = "blsp_spi8";
1423                                 };
1424                                 clk {
1425                                         pins = "gpio48";
1426                                         function = "blsp_spi8";
1427                                 };
1428                         };
1429                 };
1430
1431                 mmcc: clock-controller@fd8c0000 {
1432                         compatible = "qcom,mmcc-msm8974";
1433                         #clock-cells = <1>;
1434                         #reset-cells = <1>;
1435                         #power-domain-cells = <1>;
1436                         reg = <0xfd8c0000 0x6000>;
1437                 };
1438
1439                 mdss: mdss@fd900000 {
1440                         compatible = "qcom,mdss";
1441                         reg = <0xfd900000 0x100>, <0xfd924000 0x1000>;
1442                         reg-names = "mdss_phys", "vbif_phys";
1443
1444                         power-domains = <&mmcc MDSS_GDSC>;
1445
1446                         clocks = <&mmcc MDSS_AHB_CLK>,
1447                                  <&mmcc MDSS_AXI_CLK>,
1448                                  <&mmcc MDSS_VSYNC_CLK>;
1449                         clock-names = "iface", "bus", "vsync";
1450
1451                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1452
1453                         interrupt-controller;
1454                         #interrupt-cells = <1>;
1455
1456                         status = "disabled";
1457
1458                         #address-cells = <1>;
1459                         #size-cells = <1>;
1460                         ranges;
1461
1462                         mdp: mdp@fd900000 {
1463                                 compatible = "qcom,mdp5";
1464                                 reg = <0xfd900100 0x22000>;
1465                                 reg-names = "mdp_phys";
1466
1467                                 interrupt-parent = <&mdss>;
1468                                 interrupts = <0>;
1469
1470                                 clocks = <&mmcc MDSS_AHB_CLK>,
1471                                          <&mmcc MDSS_AXI_CLK>,
1472                                          <&mmcc MDSS_MDP_CLK>,
1473                                          <&mmcc MDSS_VSYNC_CLK>;
1474                                 clock-names = "iface", "bus", "core", "vsync";
1475
1476                                 interconnects = <&mmssnoc MNOC_MAS_MDP_PORT0 &bimc BIMC_SLV_EBI_CH0>;
1477                                 interconnect-names = "mdp0-mem";
1478
1479                                 ports {
1480                                         #address-cells = <1>;
1481                                         #size-cells = <0>;
1482
1483                                         port@0 {
1484                                                 reg = <0>;
1485                                                 mdp5_intf1_out: endpoint {
1486                                                         remote-endpoint = <&dsi0_in>;
1487                                                 };
1488                                         };
1489                                 };
1490                         };
1491
1492                         dsi0: dsi@fd922800 {
1493                                 compatible = "qcom,mdss-dsi-ctrl";
1494                                 reg = <0xfd922800 0x1f8>;
1495                                 reg-names = "dsi_ctrl";
1496
1497                                 interrupt-parent = <&mdss>;
1498                                 interrupts = <4>;
1499
1500                                 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>;
1501                                 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
1502
1503                                 clocks = <&mmcc MDSS_MDP_CLK>,
1504                                          <&mmcc MDSS_AHB_CLK>,
1505                                          <&mmcc MDSS_AXI_CLK>,
1506                                          <&mmcc MDSS_BYTE0_CLK>,
1507                                          <&mmcc MDSS_PCLK0_CLK>,
1508                                          <&mmcc MDSS_ESC0_CLK>,
1509                                          <&mmcc MMSS_MISC_AHB_CLK>;
1510                                 clock-names = "mdp_core",
1511                                               "iface",
1512                                               "bus",
1513                                               "byte",
1514                                               "pixel",
1515                                               "core",
1516                                               "core_mmss";
1517
1518                                 phys = <&dsi0_phy>;
1519                                 phy-names = "dsi-phy";
1520
1521                                 status = "disabled";
1522
1523                                 #address-cells = <1>;
1524                                 #size-cells = <0>;
1525
1526                                 ports {
1527                                         #address-cells = <1>;
1528                                         #size-cells = <0>;
1529
1530                                         port@0 {
1531                                                 reg = <0>;
1532                                                 dsi0_in: endpoint {
1533                                                         remote-endpoint = <&mdp5_intf1_out>;
1534                                                 };
1535                                         };
1536
1537                                         port@1 {
1538                                                 reg = <1>;
1539                                                 dsi0_out: endpoint {
1540                                                 };
1541                                         };
1542                                 };
1543                         };
1544
1545                         dsi0_phy: dsi-phy@fd922a00 {
1546                                 compatible = "qcom,dsi-phy-28nm-hpm";
1547                                 reg = <0xfd922a00 0xd4>,
1548                                       <0xfd922b00 0x280>,
1549                                       <0xfd922d80 0x30>;
1550                                 reg-names = "dsi_pll",
1551                                             "dsi_phy",
1552                                             "dsi_phy_regulator";
1553
1554                                 #clock-cells = <1>;
1555                                 #phy-cells = <0>;
1556
1557                                 clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>;
1558                                 clock-names = "iface", "ref";
1559
1560                                 status = "disabled";
1561                         };
1562                 };
1563
1564                 gpu: adreno@fdb00000 {
1565                         compatible = "qcom,adreno-330.1", "qcom,adreno";
1566                         reg = <0xfdb00000 0x10000>;
1567                         reg-names = "kgsl_3d0_reg_memory";
1568
1569                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1570                         interrupt-names = "kgsl_3d0_irq";
1571
1572                         clocks = <&mmcc OXILI_GFX3D_CLK>,
1573                                  <&mmcc OXILICX_AHB_CLK>,
1574                                  <&mmcc OXILICX_AXI_CLK>;
1575                         clock-names = "core", "iface", "mem_iface";
1576
1577                         sram = <&gmu_sram>;
1578                         power-domains = <&mmcc OXILICX_GDSC>;
1579                         operating-points-v2 = <&gpu_opp_table>;
1580
1581                         interconnects = <&mmssnoc MNOC_MAS_GRAPHICS_3D &bimc BIMC_SLV_EBI_CH0>,
1582                                         <&ocmemnoc OCMEM_VNOC_MAS_GFX3D &ocmemnoc OCMEM_SLV_OCMEM>;
1583                         interconnect-names = "gfx-mem", "ocmem";
1584
1585                         // iommus = <&gpu_iommu 0>;
1586
1587                         status = "disabled";
1588
1589                         gpu_opp_table: opp_table {
1590                                 compatible = "operating-points-v2";
1591
1592                                 opp-320000000 {
1593                                         opp-hz = /bits/ 64 <320000000>;
1594                                 };
1595
1596                                 opp-200000000 {
1597                                         opp-hz = /bits/ 64 <200000000>;
1598                                 };
1599
1600                                 opp-27000000 {
1601                                         opp-hz = /bits/ 64 <27000000>;
1602                                 };
1603                         };
1604                 };
1605
1606                 ocmem@fdd00000 {
1607                         compatible = "qcom,msm8974-ocmem";
1608                         reg = <0xfdd00000 0x2000>,
1609                               <0xfec00000 0x180000>;
1610                         reg-names = "ctrl", "mem";
1611                         clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
1612                                  <&mmcc OCMEMCX_OCMEMNOC_CLK>;
1613                         clock-names = "core", "iface";
1614
1615                         #address-cells = <1>;
1616                         #size-cells = <1>;
1617
1618                         gmu_sram: gmu-sram@0 {
1619                                 reg = <0x0 0x100000>;
1620                         };
1621                 };
1622
1623                 remoteproc_adsp: remoteproc@fe200000 {
1624                         compatible = "qcom,msm8974-adsp-pil";
1625                         reg = <0xfe200000 0x100>;
1626
1627                         interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
1628                                                <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1629                                                <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1630                                                <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1631                                                <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1632                         interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
1633
1634                         clocks = <&xo_board>;
1635                         clock-names = "xo";
1636
1637                         memory-region = <&adsp_region>;
1638
1639                         qcom,smem-states = <&adsp_smp2p_out 0>;
1640                         qcom,smem-state-names = "stop";
1641
1642                         smd-edge {
1643                                 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
1644
1645                                 qcom,ipc = <&apcs 8 8>;
1646                                 qcom,smd-edge = <1>;
1647                                 label = "lpass";
1648                                 #address-cells = <1>;
1649                                 #size-cells = <0>;
1650                         };
1651                 };
1652
1653                 imem: imem@fe805000 {
1654                         compatible = "syscon", "simple-mfd";
1655                         reg = <0xfe805000 0x1000>;
1656
1657                         reboot-mode {
1658                                 compatible = "syscon-reboot-mode";
1659                                 offset = <0x65c>;
1660                         };
1661                 };
1662         };
1663
1664         tcsr_mutex: tcsr-mutex {
1665                 compatible = "qcom,tcsr-mutex";
1666                 syscon = <&tcsr_mutex_block 0 0x80>;
1667
1668                 #hwlock-cells = <1>;
1669         };
1670
1671         thermal-zones {
1672                 cpu0-thermal {
1673                         polling-delay-passive = <250>;
1674                         polling-delay = <1000>;
1675
1676                         thermal-sensors = <&tsens 5>;
1677
1678                         trips {
1679                                 cpu_alert0: trip0 {
1680                                         temperature = <75000>;
1681                                         hysteresis = <2000>;
1682                                         type = "passive";
1683                                 };
1684                                 cpu_crit0: trip1 {
1685                                         temperature = <110000>;
1686                                         hysteresis = <2000>;
1687                                         type = "critical";
1688                                 };
1689                         };
1690                 };
1691
1692                 cpu1-thermal {
1693                         polling-delay-passive = <250>;
1694                         polling-delay = <1000>;
1695
1696                         thermal-sensors = <&tsens 6>;
1697
1698                         trips {
1699                                 cpu_alert1: trip0 {
1700                                         temperature = <75000>;
1701                                         hysteresis = <2000>;
1702                                         type = "passive";
1703                                 };
1704                                 cpu_crit1: trip1 {
1705                                         temperature = <110000>;
1706                                         hysteresis = <2000>;
1707                                         type = "critical";
1708                                 };
1709                         };
1710                 };
1711
1712                 cpu2-thermal {
1713                         polling-delay-passive = <250>;
1714                         polling-delay = <1000>;
1715
1716                         thermal-sensors = <&tsens 7>;
1717
1718                         trips {
1719                                 cpu_alert2: trip0 {
1720                                         temperature = <75000>;
1721                                         hysteresis = <2000>;
1722                                         type = "passive";
1723                                 };
1724                                 cpu_crit2: trip1 {
1725                                         temperature = <110000>;
1726                                         hysteresis = <2000>;
1727                                         type = "critical";
1728                                 };
1729                         };
1730                 };
1731
1732                 cpu3-thermal {
1733                         polling-delay-passive = <250>;
1734                         polling-delay = <1000>;
1735
1736                         thermal-sensors = <&tsens 8>;
1737
1738                         trips {
1739                                 cpu_alert3: trip0 {
1740                                         temperature = <75000>;
1741                                         hysteresis = <2000>;
1742                                         type = "passive";
1743                                 };
1744                                 cpu_crit3: trip1 {
1745                                         temperature = <110000>;
1746                                         hysteresis = <2000>;
1747                                         type = "critical";
1748                                 };
1749                         };
1750                 };
1751
1752                 q6-dsp-thermal {
1753                         polling-delay-passive = <250>;
1754                         polling-delay = <1000>;
1755
1756                         thermal-sensors = <&tsens 1>;
1757
1758                         trips {
1759                                 q6_dsp_alert0: trip-point0 {
1760                                         temperature = <90000>;
1761                                         hysteresis = <2000>;
1762                                         type = "hot";
1763                                 };
1764                         };
1765                 };
1766
1767                 modemtx-thermal {
1768                         polling-delay-passive = <250>;
1769                         polling-delay = <1000>;
1770
1771                         thermal-sensors = <&tsens 2>;
1772
1773                         trips {
1774                                 modemtx_alert0: trip-point0 {
1775                                         temperature = <90000>;
1776                                         hysteresis = <2000>;
1777                                         type = "hot";
1778                                 };
1779                         };
1780                 };
1781
1782                 video-thermal {
1783                         polling-delay-passive = <250>;
1784                         polling-delay = <1000>;
1785
1786                         thermal-sensors = <&tsens 3>;
1787
1788                         trips {
1789                                 video_alert0: trip-point0 {
1790                                         temperature = <95000>;
1791                                         hysteresis = <2000>;
1792                                         type = "hot";
1793                                 };
1794                         };
1795                 };
1796
1797                 wlan-thermal {
1798                         polling-delay-passive = <250>;
1799                         polling-delay = <1000>;
1800
1801                         thermal-sensors = <&tsens 4>;
1802
1803                         trips {
1804                                 wlan_alert0: trip-point0 {
1805                                         temperature = <105000>;
1806                                         hysteresis = <2000>;
1807                                         type = "hot";
1808                                 };
1809                         };
1810                 };
1811
1812                 gpu-top-thermal {
1813                         polling-delay-passive = <250>;
1814                         polling-delay = <1000>;
1815
1816                         thermal-sensors = <&tsens 9>;
1817
1818                         trips {
1819                                 gpu1_alert0: trip-point0 {
1820                                         temperature = <90000>;
1821                                         hysteresis = <2000>;
1822                                         type = "hot";
1823                                 };
1824                         };
1825                 };
1826
1827                 gpu-bottom-thermal {
1828                         polling-delay-passive = <250>;
1829                         polling-delay = <1000>;
1830
1831                         thermal-sensors = <&tsens 10>;
1832
1833                         trips {
1834                                 gpu2_alert0: trip-point0 {
1835                                         temperature = <90000>;
1836                                         hysteresis = <2000>;
1837                                         type = "hot";
1838                                 };
1839                         };
1840                 };
1841         };
1842
1843         timer {
1844                 compatible = "arm,armv7-timer";
1845                 interrupts = <GIC_PPI 2 0xf08>,
1846                              <GIC_PPI 3 0xf08>,
1847                              <GIC_PPI 4 0xf08>,
1848                              <GIC_PPI 1 0xf08>;
1849                 clock-frequency = <19200000>;
1850         };
1851
1852         vreg_boost: vreg-boost {
1853                 compatible = "regulator-fixed";
1854
1855                 regulator-name = "vreg-boost";
1856                 regulator-min-microvolt = <3150000>;
1857                 regulator-max-microvolt = <3150000>;
1858
1859                 regulator-always-on;
1860                 regulator-boot-on;
1861
1862                 gpio = <&pm8941_gpios 21 GPIO_ACTIVE_HIGH>;
1863                 enable-active-high;
1864
1865                 pinctrl-names = "default";
1866                 pinctrl-0 = <&boost_bypass_n_pin>;
1867         };
1868
1869         vreg_vph_pwr: vreg-vph-pwr {
1870                 compatible = "regulator-fixed";
1871                 regulator-name = "vph-pwr";
1872
1873                 regulator-min-microvolt = <3600000>;
1874                 regulator-max-microvolt = <3600000>;
1875
1876                 regulator-always-on;
1877         };
1878 };