1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
6 #include <dt-bindings/clock/qcom,lcc-msm8960.h>
7 #include <dt-bindings/mfd/qcom-rpm.h>
8 #include <dt-bindings/soc/qcom,gsbi.h>
13 model = "Qualcomm MSM8960";
14 compatible = "qcom,msm8960";
15 interrupt-parent = <&intc>;
20 interrupts = <1 14 0x304>;
23 compatible = "qcom,krait";
24 enable-method = "qcom,kpss-acc-v1";
27 next-level-cache = <&L2>;
33 compatible = "qcom,krait";
34 enable-method = "qcom,kpss-acc-v1";
37 next-level-cache = <&L2>;
49 device_type = "memory";
54 compatible = "qcom,krait-pmu";
55 interrupts = <1 10 0x304>;
60 cxo_board: cxo_board {
61 compatible = "fixed-clock";
63 clock-frequency = <19200000>;
64 clock-output-names = "cxo_board";
67 pxo_board: pxo_board {
68 compatible = "fixed-clock";
70 clock-frequency = <27000000>;
71 clock-output-names = "pxo_board";
75 compatible = "fixed-clock";
77 clock-frequency = <32768>;
78 clock-output-names = "sleep_clk";
82 /* Temporary fixed regulator */
83 vsdcc_fixed: vsdcc-regulator {
84 compatible = "regulator-fixed";
85 regulator-name = "SDCC Power";
86 regulator-min-microvolt = <2700000>;
87 regulator-max-microvolt = <2700000>;
95 compatible = "simple-bus";
97 intc: interrupt-controller@2000000 {
98 compatible = "qcom,msm-qgic2";
100 #interrupt-cells = <3>;
101 reg = <0x02000000 0x1000>,
106 compatible = "qcom,kpss-timer",
107 "qcom,kpss-wdt-msm8960", "qcom,msm-timer";
108 interrupts = <1 1 0x301>,
111 reg = <0x0200a000 0x100>;
112 clock-frequency = <27000000>,
114 cpu-offset = <0x80000>;
117 msmgpio: pinctrl@800000 {
118 compatible = "qcom,msm8960-pinctrl";
120 gpio-ranges = <&msmgpio 0 0 152>;
122 interrupts = <0 16 0x4>;
123 interrupt-controller;
124 #interrupt-cells = <2>;
125 reg = <0x800000 0x4000>;
128 gcc: clock-controller@900000 {
129 compatible = "qcom,gcc-msm8960";
131 #power-domain-cells = <1>;
133 reg = <0x900000 0x4000>;
134 clocks = <&cxo_board>,
137 clock-names = "cxo", "pxo", "pll4";
140 lcc: clock-controller@28000000 {
141 compatible = "qcom,lcc-msm8960";
142 reg = <0x28000000 0x1000>;
145 clocks = <&pxo_board>,
154 "codec_i2s_mic_codec_clk",
155 "spare_i2s_mic_codec_clk",
156 "codec_i2s_spkr_codec_clk",
157 "spare_i2s_spkr_codec_clk",
161 clock-controller@4000000 {
162 compatible = "qcom,mmcc-msm8960";
163 reg = <0x4000000 0x1000>;
165 #power-domain-cells = <1>;
167 clocks = <&pxo_board>,
185 l2cc: clock-controller@2011000 {
186 compatible = "qcom,kpss-gcc", "syscon";
187 reg = <0x2011000 0x1000>;
191 compatible = "qcom,rpm-msm8960";
192 reg = <0x108000 0x1000>;
193 qcom,ipc = <&l2cc 0x8 2>;
195 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
196 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
197 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
198 interrupt-names = "ack", "err", "wakeup";
201 compatible = "qcom,rpm-pm8921-regulators";
205 acc0: clock-controller@2088000 {
206 compatible = "qcom,kpss-acc-v1";
207 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
210 acc1: clock-controller@2098000 {
211 compatible = "qcom,kpss-acc-v1";
212 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
215 saw0: regulator@2089000 {
216 compatible = "qcom,saw2";
217 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
221 saw1: regulator@2099000 {
222 compatible = "qcom,saw2";
223 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
227 gsbi5: gsbi@16400000 {
228 compatible = "qcom,gsbi-v1.0.0";
230 reg = <0x16400000 0x100>;
231 clocks = <&gcc GSBI5_H_CLK>;
232 clock-names = "iface";
233 #address-cells = <1>;
237 syscon-tcsr = <&tcsr>;
239 gsbi5_serial: serial@16440000 {
240 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
241 reg = <0x16440000 0x1000>,
243 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
244 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
245 clock-names = "core", "iface";
251 compatible = "qcom,ssbi";
252 reg = <0x500000 0x1000>;
253 qcom,controller-type = "pmic-arbiter";
256 compatible = "qcom,pm8921";
257 interrupt-parent = <&msmgpio>;
258 interrupts = <104 8>;
259 #interrupt-cells = <2>;
260 interrupt-controller;
261 #address-cells = <1>;
265 compatible = "qcom,pm8921-pwrkey";
267 interrupt-parent = <&pmicintc>;
268 interrupts = <50 1>, <51 1>;
274 compatible = "qcom,pm8921-keypad";
276 interrupt-parent = <&pmicintc>;
277 interrupts = <74 1>, <75 1>;
284 compatible = "qcom,pm8921-rtc";
285 interrupt-parent = <&pmicintc>;
294 compatible = "qcom,prng";
295 reg = <0x1a500000 0x200>;
296 clocks = <&gcc PRNG_CLK>;
297 clock-names = "core";
301 compatible = "simple-bus";
302 #address-cells = <1>;
305 sdcc1: mmc@12400000 {
307 compatible = "arm,pl18x", "arm,primecell";
308 arm,primecell-periphid = <0x00051180>;
309 reg = <0x12400000 0x8000>;
310 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
311 interrupt-names = "cmd_irq";
312 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
313 clock-names = "mclk", "apb_pclk";
315 max-frequency = <96000000>;
319 vmmc-supply = <&vsdcc_fixed>;
322 sdcc3: mmc@12180000 {
323 compatible = "arm,pl18x", "arm,primecell";
324 arm,primecell-periphid = <0x00051180>;
326 reg = <0x12180000 0x8000>;
327 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
328 interrupt-names = "cmd_irq";
329 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
330 clock-names = "mclk", "apb_pclk";
334 max-frequency = <192000000>;
336 vmmc-supply = <&vsdcc_fixed>;
340 tcsr: syscon@1a400000 {
341 compatible = "qcom,tcsr-msm8960", "syscon";
342 reg = <0x1a400000 0x100>;
345 gsbi1: gsbi@16000000 {
346 compatible = "qcom,gsbi-v1.0.0";
348 reg = <0x16000000 0x100>;
349 clocks = <&gcc GSBI1_H_CLK>;
350 clock-names = "iface";
351 #address-cells = <1>;
355 gsbi1_spi: spi@16080000 {
356 compatible = "qcom,spi-qup-v1.1.1";
357 #address-cells = <1>;
359 reg = <0x16080000 0x1000>;
360 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
361 spi-max-frequency = <24000000>;
362 cs-gpios = <&msmgpio 8 0>;
364 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
365 clock-names = "core", "iface";