1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
6 #include <dt-bindings/mfd/qcom-rpm.h>
7 #include <dt-bindings/soc/qcom,gsbi.h>
12 model = "Qualcomm MSM8960";
13 compatible = "qcom,msm8960";
14 interrupt-parent = <&intc>;
19 interrupts = <1 14 0x304>;
22 compatible = "qcom,krait";
23 enable-method = "qcom,kpss-acc-v1";
26 next-level-cache = <&L2>;
32 compatible = "qcom,krait";
33 enable-method = "qcom,kpss-acc-v1";
36 next-level-cache = <&L2>;
48 device_type = "memory";
53 compatible = "qcom,krait-pmu";
54 interrupts = <1 10 0x304>;
60 compatible = "fixed-clock";
62 clock-frequency = <19200000>;
63 clock-output-names = "cxo_board";
67 compatible = "fixed-clock";
69 clock-frequency = <27000000>;
70 clock-output-names = "pxo_board";
74 compatible = "fixed-clock";
76 clock-frequency = <32768>;
77 clock-output-names = "sleep_clk";
81 /* Temporary fixed regulator */
82 vsdcc_fixed: vsdcc-regulator {
83 compatible = "regulator-fixed";
84 regulator-name = "SDCC Power";
85 regulator-min-microvolt = <2700000>;
86 regulator-max-microvolt = <2700000>;
94 compatible = "simple-bus";
96 intc: interrupt-controller@2000000 {
97 compatible = "qcom,msm-qgic2";
99 #interrupt-cells = <3>;
100 reg = <0x02000000 0x1000>,
105 compatible = "qcom,kpss-timer",
106 "qcom,kpss-wdt-msm8960", "qcom,msm-timer";
107 interrupts = <1 1 0x301>,
110 reg = <0x0200a000 0x100>;
111 clock-frequency = <27000000>,
113 cpu-offset = <0x80000>;
116 msmgpio: pinctrl@800000 {
117 compatible = "qcom,msm8960-pinctrl";
119 gpio-ranges = <&msmgpio 0 0 152>;
121 interrupts = <0 16 0x4>;
122 interrupt-controller;
123 #interrupt-cells = <2>;
124 reg = <0x800000 0x4000>;
127 gcc: clock-controller@900000 {
128 compatible = "qcom,gcc-msm8960";
130 #power-domain-cells = <1>;
132 reg = <0x900000 0x4000>;
135 lcc: clock-controller@28000000 {
136 compatible = "qcom,lcc-msm8960";
137 reg = <0x28000000 0x1000>;
142 clock-controller@4000000 {
143 compatible = "qcom,mmcc-msm8960";
144 reg = <0x4000000 0x1000>;
146 #power-domain-cells = <1>;
150 l2cc: clock-controller@2011000 {
151 compatible = "qcom,kpss-gcc", "syscon";
152 reg = <0x2011000 0x1000>;
156 compatible = "qcom,rpm-msm8960";
157 reg = <0x108000 0x1000>;
158 qcom,ipc = <&l2cc 0x8 2>;
160 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
161 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
162 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
163 interrupt-names = "ack", "err", "wakeup";
166 compatible = "qcom,rpm-pm8921-regulators";
170 acc0: clock-controller@2088000 {
171 compatible = "qcom,kpss-acc-v1";
172 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
175 acc1: clock-controller@2098000 {
176 compatible = "qcom,kpss-acc-v1";
177 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
180 saw0: regulator@2089000 {
181 compatible = "qcom,saw2";
182 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
186 saw1: regulator@2099000 {
187 compatible = "qcom,saw2";
188 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
192 gsbi5: gsbi@16400000 {
193 compatible = "qcom,gsbi-v1.0.0";
195 reg = <0x16400000 0x100>;
196 clocks = <&gcc GSBI5_H_CLK>;
197 clock-names = "iface";
198 #address-cells = <1>;
202 syscon-tcsr = <&tcsr>;
204 gsbi5_serial: serial@16440000 {
205 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
206 reg = <0x16440000 0x1000>,
208 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
209 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
210 clock-names = "core", "iface";
216 compatible = "qcom,ssbi";
217 reg = <0x500000 0x1000>;
218 qcom,controller-type = "pmic-arbiter";
221 compatible = "qcom,pm8921";
222 interrupt-parent = <&msmgpio>;
223 interrupts = <104 8>;
224 #interrupt-cells = <2>;
225 interrupt-controller;
226 #address-cells = <1>;
230 compatible = "qcom,pm8921-pwrkey";
232 interrupt-parent = <&pmicintc>;
233 interrupts = <50 1>, <51 1>;
239 compatible = "qcom,pm8921-keypad";
241 interrupt-parent = <&pmicintc>;
242 interrupts = <74 1>, <75 1>;
249 compatible = "qcom,pm8921-rtc";
250 interrupt-parent = <&pmicintc>;
259 compatible = "qcom,prng";
260 reg = <0x1a500000 0x200>;
261 clocks = <&gcc PRNG_CLK>;
262 clock-names = "core";
266 compatible = "simple-bus";
267 #address-cells = <1>;
270 sdcc1: mmc@12400000 {
272 compatible = "arm,pl18x", "arm,primecell";
273 arm,primecell-periphid = <0x00051180>;
274 reg = <0x12400000 0x8000>;
275 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
276 interrupt-names = "cmd_irq";
277 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
278 clock-names = "mclk", "apb_pclk";
280 max-frequency = <96000000>;
284 vmmc-supply = <&vsdcc_fixed>;
287 sdcc3: mmc@12180000 {
288 compatible = "arm,pl18x", "arm,primecell";
289 arm,primecell-periphid = <0x00051180>;
291 reg = <0x12180000 0x8000>;
292 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
293 interrupt-names = "cmd_irq";
294 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
295 clock-names = "mclk", "apb_pclk";
299 max-frequency = <192000000>;
301 vmmc-supply = <&vsdcc_fixed>;
305 tcsr: syscon@1a400000 {
306 compatible = "qcom,tcsr-msm8960", "syscon";
307 reg = <0x1a400000 0x100>;
311 compatible = "qcom,gsbi-v1.0.0";
313 reg = <0x16000000 0x100>;
314 clocks = <&gcc GSBI1_H_CLK>;
315 clock-names = "iface";
316 #address-cells = <1>;
321 compatible = "qcom,spi-qup-v1.1.1";
322 #address-cells = <1>;
324 reg = <0x16080000 0x1000>;
325 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
326 spi-max-frequency = <24000000>;
327 cs-gpios = <&msmgpio 8 0>;
329 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
330 clock-names = "core", "iface";