arch/arm/boot/dts/qcom-msm8960.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /dts-v1/;
   3
   4 #include <dt-bindings/interrupt-controller/arm-gic.h>
   5 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
   6 #include <dt-bindings/clock/qcom,lcc-msm8960.h>
   7 #include <dt-bindings/mfd/qcom-rpm.h>
   8 #include <dt-bindings/soc/qcom,gsbi.h>
   9
  10 / {
  11         #address-cells = <1>;
  12         #size-cells = <1>;
  13         model = "Qualcomm MSM8960";
  14         compatible = "qcom,msm8960";
  15         interrupt-parent = <&intc>;
  16
  17         cpus {
  18                 #address-cells = <1>;
  19                 #size-cells = <0>;
  20                 interrupts = <1 14 0x304>;
  21
  22                 cpu@0 {
  23                         compatible = "qcom,krait";
  24                         enable-method = "qcom,kpss-acc-v1";
  25                         device_type = "cpu";
  26                         reg = <0>;
  27                         next-level-cache = <&L2>;
  28                         qcom,acc = <&acc0>;
  29                         qcom,saw = <&saw0>;
  30                 };
  31
  32                 cpu@1 {
  33                         compatible = "qcom,krait";
  34                         enable-method = "qcom,kpss-acc-v1";
  35                         device_type = "cpu";
  36                         reg = <1>;
  37                         next-level-cache = <&L2>;
  38                         qcom,acc = <&acc1>;
  39                         qcom,saw = <&saw1>;
  40                 };
  41
  42                 L2: l2-cache {
  43                         compatible = "cache";
  44                         cache-level = <2>;
  45                 };
  46         };
  47
  48         memory {
  49                 device_type = "memory";
  50                 reg = <0x0 0x0>;
  51         };
  52
  53         cpu-pmu {
  54                 compatible = "qcom,krait-pmu";
  55                 interrupts = <1 10 0x304>;
  56                 qcom,no-pc-write;
  57         };
  58
  59         clocks {
  60                 cxo_board: cxo_board {
  61                         compatible = "fixed-clock";
  62                         #clock-cells = <0>;
  63                         clock-frequency = <19200000>;
  64                         clock-output-names = "cxo_board";
  65                 };
  66
  67                 pxo_board: pxo_board {
  68                         compatible = "fixed-clock";
  69                         #clock-cells = <0>;
  70                         clock-frequency = <27000000>;
  71                         clock-output-names = "pxo_board";
  72                 };
  73
  74                 sleep_clk {
  75                         compatible = "fixed-clock";
  76                         #clock-cells = <0>;
  77                         clock-frequency = <32768>;
  78                         clock-output-names = "sleep_clk";
  79                 };
  80         };
  81
  82         /* Temporary fixed regulator */
  83         vsdcc_fixed: vsdcc-regulator {
  84                 compatible = "regulator-fixed";
  85                 regulator-name = "SDCC Power";
  86                 regulator-min-microvolt = <2700000>;
  87                 regulator-max-microvolt = <2700000>;
  88                 regulator-always-on;
  89         };
  90
  91         soc: soc {
  92                 #address-cells = <1>;
  93                 #size-cells = <1>;
  94                 ranges;
  95                 compatible = "simple-bus";
  96
  97                 intc: interrupt-controller@2000000 {
  98                         compatible = "qcom,msm-qgic2";
  99                         interrupt-controller;
 100                         #interrupt-cells = <3>;
 101                         reg = <0x02000000 0x1000>,
 102                               <0x02002000 0x1000>;
 103                 };
 104
 105                 timer@200a000 {
 106                         compatible = "qcom,kpss-timer",
 107                                      "qcom,kpss-wdt-msm8960", "qcom,msm-timer";
 108                         interrupts = <1 1 0x301>,
 109                                      <1 2 0x301>,
 110                                      <1 3 0x301>;
 111                         reg = <0x0200a000 0x100>;
 112                         clock-frequency = <27000000>,
 113                                           <32768>;
 114                         cpu-offset = <0x80000>;
 115                 };
 116
 117                 msmgpio: pinctrl@800000 {
 118                         compatible = "qcom,msm8960-pinctrl";
 119                         gpio-controller;
 120                         gpio-ranges = <&msmgpio 0 0 152>;
 121                         #gpio-cells = <2>;
 122                         interrupts = <0 16 0x4>;
 123                         interrupt-controller;
 124                         #interrupt-cells = <2>;
 125                         reg = <0x800000 0x4000>;
 126                 };
 127
 128                 gcc: clock-controller@900000 {
 129                         compatible = "qcom,gcc-msm8960";
 130                         #clock-cells = <1>;
 131                         #power-domain-cells = <1>;
 132                         #reset-cells = <1>;
 133                         reg = <0x900000 0x4000>;
 134                         clocks = <&cxo_board>,
 135                                  <&pxo_board>,
 136                                  <&lcc PLL4>;
 137                         clock-names = "cxo", "pxo", "pll4";
 138                 };
 139
 140                 lcc: clock-controller@28000000 {
 141                         compatible = "qcom,lcc-msm8960";
 142                         reg = <0x28000000 0x1000>;
 143                         #clock-cells = <1>;
 144                         #reset-cells = <1>;
 145                         clocks = <&pxo_board>,
 146                                  <&gcc PLL4_VOTE>,
 147                                  <0>,
 148                                  <0>, <0>,
 149                                  <0>, <0>,
 150                                  <0>;
 151                         clock-names = "pxo",
 152                                       "pll4_vote",
 153                                       "mi2s_codec_clk",
 154                                       "codec_i2s_mic_codec_clk",
 155                                       "spare_i2s_mic_codec_clk",
 156                                       "codec_i2s_spkr_codec_clk",
 157                                       "spare_i2s_spkr_codec_clk",
 158                                       "pcm_codec_clk";
 159                 };
 160
 161                 clock-controller@4000000 {
 162                         compatible = "qcom,mmcc-msm8960";
 163                         reg = <0x4000000 0x1000>;
 164                         #clock-cells = <1>;
 165                         #power-domain-cells = <1>;
 166                         #reset-cells = <1>;
 167                         clocks = <&pxo_board>,
 168                                  <&gcc PLL3>,
 169                                  <&gcc PLL8_VOTE>,
 170                                  <0>,
 171                                  <0>,
 172                                  <0>,
 173                                  <0>,
 174                                  <0>;
 175                         clock-names = "pxo",
 176                                       "pll3",
 177                                       "pll8_vote",
 178                                       "dsi1pll",
 179                                       "dsi1pllbyte",
 180                                       "dsi2pll",
 181                                       "dsi2pllbyte",
 182                                       "hdmipll";
 183                 };
 184
 185                 l2cc: clock-controller@2011000 {
 186                         compatible = "qcom,kpss-gcc", "syscon";
 187                         reg = <0x2011000 0x1000>;
 188                 };
 189
 190                 rpm: rpm@108000 {
 191                         compatible = "qcom,rpm-msm8960";
 192                         reg = <0x108000 0x1000>;
 193                         qcom,ipc = <&l2cc 0x8 2>;
 194
 195                         interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
 196                                      <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
 197                                      <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
 198                         interrupt-names = "ack", "err", "wakeup";
 199
 200                         regulators {
 201                                 compatible = "qcom,rpm-pm8921-regulators";
 202                         };
 203                 };
 204
 205                 acc0: clock-controller@2088000 {
 206                         compatible = "qcom,kpss-acc-v1";
 207                         reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
 208                 };
 209
 210                 acc1: clock-controller@2098000 {
 211                         compatible = "qcom,kpss-acc-v1";
 212                         reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
 213                 };
 214
 215                 saw0: regulator@2089000 {
 216                         compatible = "qcom,saw2";
 217                         reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
 218                         regulator;
 219                 };
 220
 221                 saw1: regulator@2099000 {
 222                         compatible = "qcom,saw2";
 223                         reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
 224                         regulator;
 225                 };
 226
 227                 gsbi5: gsbi@16400000 {
 228                         compatible = "qcom,gsbi-v1.0.0";
 229                         cell-index = <5>;
 230                         reg = <0x16400000 0x100>;
 231                         clocks = <&gcc GSBI5_H_CLK>;
 232                         clock-names = "iface";
 233                         #address-cells = <1>;
 234                         #size-cells = <1>;
 235                         ranges;
 236
 237                         syscon-tcsr = <&tcsr>;
 238
 239                         gsbi5_serial: serial@16440000 {
 240                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 241                                 reg = <0x16440000 0x1000>,
 242                                       <0x16400000 0x1000>;
 243                                 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 244                                 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
 245                                 clock-names = "core", "iface";
 246                                 status = "disabled";
 247                         };
 248                 };
 249
 250                 qcom,ssbi@500000 {
 251                         compatible = "qcom,ssbi";
 252                         reg = <0x500000 0x1000>;
 253                         qcom,controller-type = "pmic-arbiter";
 254
 255                         pmicintc: pmic@0 {
 256                                 compatible = "qcom,pm8921";
 257                                 interrupt-parent = <&msmgpio>;
 258                                 interrupts = <104 8>;
 259                                 #interrupt-cells = <2>;
 260                                 interrupt-controller;
 261                                 #address-cells = <1>;
 262                                 #size-cells = <0>;
 263
 264                                 pwrkey@1c {
 265                                         compatible = "qcom,pm8921-pwrkey";
 266                                         reg = <0x1c>;
 267                                         interrupt-parent = <&pmicintc>;
 268                                         interrupts = <50 1>, <51 1>;
 269                                         debounce = <15625>;
 270                                         pull-up;
 271                                 };
 272
 273                                 keypad@148 {
 274                                         compatible = "qcom,pm8921-keypad";
 275                                         reg = <0x148>;
 276                                         interrupt-parent = <&pmicintc>;
 277                                         interrupts = <74 1>, <75 1>;
 278                                         debounce = <15>;
 279                                         scan-delay = <32>;
 280                                         row-hold = <91500>;
 281                                 };
 282
 283                                 rtc@11d {
 284                                         compatible = "qcom,pm8921-rtc";
 285                                         interrupt-parent = <&pmicintc>;
 286                                         interrupts = <39 1>;
 287                                         reg = <0x11d>;
 288                                         allow-set-time;
 289                                 };
 290                         };
 291                 };
 292
 293                 rng@1a500000 {
 294                         compatible = "qcom,prng";
 295                         reg = <0x1a500000 0x200>;
 296                         clocks = <&gcc PRNG_CLK>;
 297                         clock-names = "core";
 298                 };
 299
 300                 amba {
 301                         compatible = "simple-bus";
 302                         #address-cells = <1>;
 303                         #size-cells = <1>;
 304                         ranges;
 305                         sdcc1: mmc@12400000 {
 306                                 status = "disabled";
 307                                 compatible = "arm,pl18x", "arm,primecell";
 308                                 arm,primecell-periphid = <0x00051180>;
 309                                 reg = <0x12400000 0x8000>;
 310                                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 311                                 interrupt-names = "cmd_irq";
 312                                 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
 313                                 clock-names = "mclk", "apb_pclk";
 314                                 bus-width = <8>;
 315                                 max-frequency = <96000000>;
 316                                 non-removable;
 317                                 cap-sd-highspeed;
 318                                 cap-mmc-highspeed;
 319                                 vmmc-supply = <&vsdcc_fixed>;
 320                         };
 321
 322                         sdcc3: mmc@12180000 {
 323                                 compatible = "arm,pl18x", "arm,primecell";
 324                                 arm,primecell-periphid = <0x00051180>;
 325                                 status = "disabled";
 326                                 reg = <0x12180000 0x8000>;
 327                                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 328                                 interrupt-names = "cmd_irq";
 329                                 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
 330                                 clock-names = "mclk", "apb_pclk";
 331                                 bus-width = <4>;
 332                                 cap-sd-highspeed;
 333                                 cap-mmc-highspeed;
 334                                 max-frequency = <192000000>;
 335                                 no-1-8-v;
 336                                 vmmc-supply = <&vsdcc_fixed>;
 337                         };
 338                 };
 339
 340                 tcsr: syscon@1a400000 {
 341                         compatible = "qcom,tcsr-msm8960", "syscon";
 342                         reg = <0x1a400000 0x100>;
 343                 };
 344
 345                 gsbi1: gsbi@16000000 {
 346                         compatible = "qcom,gsbi-v1.0.0";
 347                         cell-index = <1>;
 348                         reg = <0x16000000 0x100>;
 349                         clocks = <&gcc GSBI1_H_CLK>;
 350                         clock-names = "iface";
 351                         #address-cells = <1>;
 352                         #size-cells = <1>;
 353                         ranges;
 354
 355                         gsbi1_spi: spi@16080000 {
 356                                 compatible = "qcom,spi-qup-v1.1.1";
 357                                 #address-cells = <1>;
 358                                 #size-cells = <0>;
 359                                 reg = <0x16080000 0x1000>;
 360                                 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
 361                                 spi-max-frequency = <24000000>;
 362                                 cs-gpios = <&msmgpio 8 0>;
 363
 364                                 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
 365                                 clock-names = "core", "iface";
 366                                 status = "disabled";
 367                         };
 368                 };
 369         };
 370 };