3 /include/ "skeleton.dtsi"
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
7 #include <dt-bindings/mfd/qcom-rpm.h>
8 #include <dt-bindings/soc/qcom,gsbi.h>
11 model = "Qualcomm MSM8960";
12 compatible = "qcom,msm8960";
13 interrupt-parent = <&intc>;
18 interrupts = <1 14 0x304>;
21 compatible = "qcom,krait";
22 enable-method = "qcom,kpss-acc-v1";
25 next-level-cache = <&L2>;
31 compatible = "qcom,krait";
32 enable-method = "qcom,kpss-acc-v1";
35 next-level-cache = <&L2>;
47 compatible = "qcom,krait-pmu";
48 interrupts = <1 10 0x304>;
54 compatible = "fixed-clock";
56 clock-frequency = <19200000>;
57 clock-output-names = "cxo_board";
61 compatible = "fixed-clock";
63 clock-frequency = <27000000>;
64 clock-output-names = "pxo_board";
68 compatible = "fixed-clock";
70 clock-frequency = <32768>;
71 clock-output-names = "sleep_clk";
79 compatible = "simple-bus";
81 intc: interrupt-controller@2000000 {
82 compatible = "qcom,msm-qgic2";
84 #interrupt-cells = <3>;
85 reg = <0x02000000 0x1000>,
90 compatible = "qcom,kpss-timer",
91 "qcom,kpss-wdt-msm8960", "qcom,msm-timer";
92 interrupts = <1 1 0x301>,
95 reg = <0x0200a000 0x100>;
96 clock-frequency = <27000000>,
98 cpu-offset = <0x80000>;
101 msmgpio: pinctrl@800000 {
102 compatible = "qcom,msm8960-pinctrl";
105 interrupts = <0 16 0x4>;
106 interrupt-controller;
107 #interrupt-cells = <2>;
108 reg = <0x800000 0x4000>;
111 gcc: clock-controller@900000 {
112 compatible = "qcom,gcc-msm8960";
115 reg = <0x900000 0x4000>;
118 lcc: clock-controller@28000000 {
119 compatible = "qcom,lcc-msm8960";
120 reg = <0x28000000 0x1000>;
125 clock-controller@4000000 {
126 compatible = "qcom,mmcc-msm8960";
127 reg = <0x4000000 0x1000>;
132 l2cc: clock-controller@2011000 {
133 compatible = "syscon";
134 reg = <0x2011000 0x1000>;
138 compatible = "qcom,rpm-msm8960";
139 reg = <0x108000 0x1000>;
140 qcom,ipc = <&l2cc 0x8 2>;
142 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
143 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
144 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
145 interrupt-names = "ack", "err", "wakeup";
148 compatible = "qcom,rpm-pm8921-regulators";
152 acc0: clock-controller@2088000 {
153 compatible = "qcom,kpss-acc-v1";
154 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
157 acc1: clock-controller@2098000 {
158 compatible = "qcom,kpss-acc-v1";
159 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
162 saw0: regulator@2089000 {
163 compatible = "qcom,saw2";
164 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
168 saw1: regulator@2099000 {
169 compatible = "qcom,saw2";
170 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
174 gsbi5: gsbi@16400000 {
175 compatible = "qcom,gsbi-v1.0.0";
177 reg = <0x16400000 0x100>;
178 clocks = <&gcc GSBI5_H_CLK>;
179 clock-names = "iface";
180 #address-cells = <1>;
184 syscon-tcsr = <&tcsr>;
186 gsbi5_serial: serial@16440000 {
187 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
188 reg = <0x16440000 0x1000>,
190 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
191 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
192 clock-names = "core", "iface";
198 compatible = "qcom,ssbi";
199 reg = <0x500000 0x1000>;
200 qcom,controller-type = "pmic-arbiter";
203 compatible = "qcom,pm8921";
204 interrupt-parent = <&msmgpio>;
205 interrupts = <104 8>;
206 #interrupt-cells = <2>;
207 interrupt-controller;
208 #address-cells = <1>;
212 compatible = "qcom,pm8921-pwrkey";
214 interrupt-parent = <&pmicintc>;
215 interrupts = <50 1>, <51 1>;
221 compatible = "qcom,pm8921-keypad";
223 interrupt-parent = <&pmicintc>;
224 interrupts = <74 1>, <75 1>;
231 compatible = "qcom,pm8921-rtc";
232 interrupt-parent = <&pmicintc>;
241 compatible = "qcom,prng";
242 reg = <0x1a500000 0x200>;
243 clocks = <&gcc PRNG_CLK>;
244 clock-names = "core";
247 /* Temporary fixed regulator */
248 vsdcc_fixed: vsdcc-regulator {
249 compatible = "regulator-fixed";
250 regulator-name = "SDCC Power";
251 regulator-min-microvolt = <2700000>;
252 regulator-max-microvolt = <2700000>;
257 compatible = "simple-bus";
258 #address-cells = <1>;
261 sdcc1: sdcc@12400000 {
263 compatible = "arm,pl18x", "arm,primecell";
264 arm,primecell-periphid = <0x00051180>;
265 reg = <0x12400000 0x8000>;
266 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
267 interrupt-names = "cmd_irq";
268 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
269 clock-names = "mclk", "apb_pclk";
271 max-frequency = <96000000>;
275 vmmc-supply = <&vsdcc_fixed>;
278 sdcc3: sdcc@12180000 {
279 compatible = "arm,pl18x", "arm,primecell";
280 arm,primecell-periphid = <0x00051180>;
282 reg = <0x12180000 0x8000>;
283 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
284 interrupt-names = "cmd_irq";
285 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
286 clock-names = "mclk", "apb_pclk";
290 max-frequency = <192000000>;
292 vmmc-supply = <&vsdcc_fixed>;
296 tcsr: syscon@1a400000 {
297 compatible = "qcom,tcsr-msm8960", "syscon";
298 reg = <0x1a400000 0x100>;
302 compatible = "qcom,gsbi-v1.0.0";
304 reg = <0x16000000 0x100>;
305 clocks = <&gcc GSBI1_H_CLK>;
306 clock-names = "iface";
307 #address-cells = <1>;
312 compatible = "qcom,spi-qup-v1.1.1";
313 #address-cells = <1>;
315 reg = <0x16080000 0x1000>;
316 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
317 spi-max-frequency = <24000000>;
318 cs-gpios = <&msmgpio 8 0>;
320 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
321 clock-names = "core", "iface";