arch/arm/boot/dts/qcom-msm8960.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /dts-v1/;
   3
   4 #include <dt-bindings/interrupt-controller/arm-gic.h>
   5 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
   6 #include <dt-bindings/mfd/qcom-rpm.h>
   7 #include <dt-bindings/soc/qcom,gsbi.h>
   8
   9 / {
  10         #address-cells = <1>;
  11         #size-cells = <1>;
  12         model = "Qualcomm MSM8960";
  13         compatible = "qcom,msm8960";
  14         interrupt-parent = <&intc>;
  15
  16         cpus {
  17                 #address-cells = <1>;
  18                 #size-cells = <0>;
  19                 interrupts = <1 14 0x304>;
  20
  21                 cpu@0 {
  22                         compatible = "qcom,krait";
  23                         enable-method = "qcom,kpss-acc-v1";
  24                         device_type = "cpu";
  25                         reg = <0>;
  26                         next-level-cache = <&L2>;
  27                         qcom,acc = <&acc0>;
  28                         qcom,saw = <&saw0>;
  29                 };
  30
  31                 cpu@1 {
  32                         compatible = "qcom,krait";
  33                         enable-method = "qcom,kpss-acc-v1";
  34                         device_type = "cpu";
  35                         reg = <1>;
  36                         next-level-cache = <&L2>;
  37                         qcom,acc = <&acc1>;
  38                         qcom,saw = <&saw1>;
  39                 };
  40
  41                 L2: l2-cache {
  42                         compatible = "cache";
  43                         cache-level = <2>;
  44                 };
  45         };
  46
  47         memory {
  48                 device_type = "memory";
  49                 reg = <0x0 0x0>;
  50         };
  51
  52         cpu-pmu {
  53                 compatible = "qcom,krait-pmu";
  54                 interrupts = <1 10 0x304>;
  55                 qcom,no-pc-write;
  56         };
  57
  58         clocks {
  59                 cxo_board {
  60                         compatible = "fixed-clock";
  61                         #clock-cells = <0>;
  62                         clock-frequency = <19200000>;
  63                         clock-output-names = "cxo_board";
  64                 };
  65
  66                 pxo_board {
  67                         compatible = "fixed-clock";
  68                         #clock-cells = <0>;
  69                         clock-frequency = <27000000>;
  70                         clock-output-names = "pxo_board";
  71                 };
  72
  73                 sleep_clk {
  74                         compatible = "fixed-clock";
  75                         #clock-cells = <0>;
  76                         clock-frequency = <32768>;
  77                         clock-output-names = "sleep_clk";
  78                 };
  79         };
  80
  81         soc: soc {
  82                 #address-cells = <1>;
  83                 #size-cells = <1>;
  84                 ranges;
  85                 compatible = "simple-bus";
  86
  87                 intc: interrupt-controller@2000000 {
  88                         compatible = "qcom,msm-qgic2";
  89                         interrupt-controller;
  90                         #interrupt-cells = <3>;
  91                         reg = <0x02000000 0x1000>,
  92                               <0x02002000 0x1000>;
  93                 };
  94
  95                 timer@200a000 {
  96                         compatible = "qcom,kpss-timer",
  97                                      "qcom,kpss-wdt-msm8960", "qcom,msm-timer";
  98                         interrupts = <1 1 0x301>,
  99                                      <1 2 0x301>,
 100                                      <1 3 0x301>;
 101                         reg = <0x0200a000 0x100>;
 102                         clock-frequency = <27000000>,
 103                                           <32768>;
 104                         cpu-offset = <0x80000>;
 105                 };
 106
 107                 msmgpio: pinctrl@800000 {
 108                         compatible = "qcom,msm8960-pinctrl";
 109                         gpio-controller;
 110                         #gpio-cells = <2>;
 111                         interrupts = <0 16 0x4>;
 112                         interrupt-controller;
 113                         #interrupt-cells = <2>;
 114                         reg = <0x800000 0x4000>;
 115                 };
 116
 117                 gcc: clock-controller@900000 {
 118                         compatible = "qcom,gcc-msm8960";
 119                         #clock-cells = <1>;
 120                         #reset-cells = <1>;
 121                         reg = <0x900000 0x4000>;
 122                 };
 123
 124                 lcc: clock-controller@28000000 {
 125                         compatible = "qcom,lcc-msm8960";
 126                         reg = <0x28000000 0x1000>;
 127                         #clock-cells = <1>;
 128                         #reset-cells = <1>;
 129                 };
 130
 131                 clock-controller@4000000 {
 132                         compatible = "qcom,mmcc-msm8960";
 133                         reg = <0x4000000 0x1000>;
 134                         #clock-cells = <1>;
 135                         #reset-cells = <1>;
 136                 };
 137
 138                 l2cc: clock-controller@2011000 {
 139                         compatible      = "syscon";
 140                         reg             = <0x2011000 0x1000>;
 141                 };
 142
 143                 rpm@108000 {
 144                         compatible      = "qcom,rpm-msm8960";
 145                         reg             = <0x108000 0x1000>;
 146                         qcom,ipc        = <&l2cc 0x8 2>;
 147
 148                         interrupts      = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
 149                                           <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
 150                                           <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
 151                         interrupt-names = "ack", "err", "wakeup";
 152
 153                         regulators {
 154                                 compatible = "qcom,rpm-pm8921-regulators";
 155                         };
 156                 };
 157
 158                 acc0: clock-controller@2088000 {
 159                         compatible = "qcom,kpss-acc-v1";
 160                         reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
 161                 };
 162
 163                 acc1: clock-controller@2098000 {
 164                         compatible = "qcom,kpss-acc-v1";
 165                         reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
 166                 };
 167
 168                 saw0: regulator@2089000 {
 169                         compatible = "qcom,saw2";
 170                         reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
 171                         regulator;
 172                 };
 173
 174                 saw1: regulator@2099000 {
 175                         compatible = "qcom,saw2";
 176                         reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
 177                         regulator;
 178                 };
 179
 180                 gsbi5: gsbi@16400000 {
 181                         compatible = "qcom,gsbi-v1.0.0";
 182                         cell-index = <5>;
 183                         reg = <0x16400000 0x100>;
 184                         clocks = <&gcc GSBI5_H_CLK>;
 185                         clock-names = "iface";
 186                         #address-cells = <1>;
 187                         #size-cells = <1>;
 188                         ranges;
 189
 190                         syscon-tcsr = <&tcsr>;
 191
 192                         gsbi5_serial: serial@16440000 {
 193                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 194                                 reg = <0x16440000 0x1000>,
 195                                       <0x16400000 0x1000>;
 196                                 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 197                                 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
 198                                 clock-names = "core", "iface";
 199                                 status = "disabled";
 200                         };
 201                 };
 202
 203                 qcom,ssbi@500000 {
 204                         compatible = "qcom,ssbi";
 205                         reg = <0x500000 0x1000>;
 206                         qcom,controller-type = "pmic-arbiter";
 207
 208                         pmicintc: pmic@0 {
 209                                 compatible = "qcom,pm8921";
 210                                 interrupt-parent = <&msmgpio>;
 211                                 interrupts = <104 8>;
 212                                 #interrupt-cells = <2>;
 213                                 interrupt-controller;
 214                                 #address-cells = <1>;
 215                                 #size-cells = <0>;
 216
 217                                 pwrkey@1c {
 218                                         compatible = "qcom,pm8921-pwrkey";
 219                                         reg = <0x1c>;
 220                                         interrupt-parent = <&pmicintc>;
 221                                         interrupts = <50 1>, <51 1>;
 222                                         debounce = <15625>;
 223                                         pull-up;
 224                                 };
 225
 226                                 keypad@148 {
 227                                         compatible = "qcom,pm8921-keypad";
 228                                         reg = <0x148>;
 229                                         interrupt-parent = <&pmicintc>;
 230                                         interrupts = <74 1>, <75 1>;
 231                                         debounce = <15>;
 232                                         scan-delay = <32>;
 233                                         row-hold = <91500>;
 234                                 };
 235
 236                                 rtc@11d {
 237                                         compatible = "qcom,pm8921-rtc";
 238                                         interrupt-parent = <&pmicintc>;
 239                                         interrupts = <39 1>;
 240                                         reg = <0x11d>;
 241                                         allow-set-time;
 242                                 };
 243                         };
 244                 };
 245
 246                 rng@1a500000 {
 247                         compatible = "qcom,prng";
 248                         reg = <0x1a500000 0x200>;
 249                         clocks = <&gcc PRNG_CLK>;
 250                         clock-names = "core";
 251                 };
 252
 253                 /* Temporary fixed regulator */
 254                 vsdcc_fixed: vsdcc-regulator {
 255                         compatible = "regulator-fixed";
 256                         regulator-name = "SDCC Power";
 257                         regulator-min-microvolt = <2700000>;
 258                         regulator-max-microvolt = <2700000>;
 259                         regulator-always-on;
 260                 };
 261
 262                 amba {
 263                         compatible = "simple-bus";
 264                         #address-cells = <1>;
 265                         #size-cells = <1>;
 266                         ranges;
 267                         sdcc1: sdcc@12400000 {
 268                                 status          = "disabled";
 269                                 compatible      = "arm,pl18x", "arm,primecell";
 270                                 arm,primecell-periphid = <0x00051180>;
 271                                 reg             = <0x12400000 0x8000>;
 272                                 interrupts      = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 273                                 interrupt-names = "cmd_irq";
 274                                 clocks          = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
 275                                 clock-names     = "mclk", "apb_pclk";
 276                                 bus-width       = <8>;
 277                                 max-frequency   = <96000000>;
 278                                 non-removable;
 279                                 cap-sd-highspeed;
 280                                 cap-mmc-highspeed;
 281                                 vmmc-supply = <&vsdcc_fixed>;
 282                         };
 283
 284                         sdcc3: sdcc@12180000 {
 285                                 compatible      = "arm,pl18x", "arm,primecell";
 286                                 arm,primecell-periphid = <0x00051180>;
 287                                 status          = "disabled";
 288                                 reg             = <0x12180000 0x8000>;
 289                                 interrupts      = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 290                                 interrupt-names = "cmd_irq";
 291                                 clocks          = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
 292                                 clock-names     = "mclk", "apb_pclk";
 293                                 bus-width       = <4>;
 294                                 cap-sd-highspeed;
 295                                 cap-mmc-highspeed;
 296                                 max-frequency   = <192000000>;
 297                                 no-1-8-v;
 298                                 vmmc-supply = <&vsdcc_fixed>;
 299                         };
 300                 };
 301
 302                 tcsr: syscon@1a400000 {
 303                         compatible = "qcom,tcsr-msm8960", "syscon";
 304                         reg = <0x1a400000 0x100>;
 305                 };
 306
 307                 gsbi@16000000 {
 308                         compatible = "qcom,gsbi-v1.0.0";
 309                         cell-index = <1>;
 310                         reg = <0x16000000 0x100>;
 311                         clocks = <&gcc GSBI1_H_CLK>;
 312                         clock-names = "iface";
 313                         #address-cells = <1>;
 314                         #size-cells = <1>;
 315                         ranges;
 316
 317                         spi@16080000 {
 318                                 compatible = "qcom,spi-qup-v1.1.1";
 319                                 #address-cells = <1>;
 320                                 #size-cells = <0>;
 321                                 reg = <0x16080000 0x1000>;
 322                                 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
 323                                 spi-max-frequency = <24000000>;
 324                                 cs-gpios = <&msmgpio 8 0>;
 325
 326                                 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
 327                                 clock-names = "core", "iface";
 328                                 status = "disabled";
 329                         };
 330                 };
 331         };
 332 };