arch/arm/boot/dts/qcom-msm8660.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /dts-v1/;
   3
   4 #include <dt-bindings/interrupt-controller/irq.h>
   5 #include <dt-bindings/interrupt-controller/arm-gic.h>
   6 #include <dt-bindings/clock/qcom,gcc-msm8660.h>
   7 #include <dt-bindings/soc/qcom,gsbi.h>
   8
   9 / {
  10         #address-cells = <1>;
  11         #size-cells = <1>;
  12         model = "Qualcomm MSM8660";
  13         compatible = "qcom,msm8660";
  14         interrupt-parent = <&intc>;
  15
  16         cpus {
  17                 #address-cells = <1>;
  18                 #size-cells = <0>;
  19
  20                 cpu@0 {
  21                         compatible = "qcom,scorpion";
  22                         enable-method = "qcom,gcc-msm8660";
  23                         device_type = "cpu";
  24                         reg = <0>;
  25                         next-level-cache = <&L2>;
  26                 };
  27
  28                 cpu@1 {
  29                         compatible = "qcom,scorpion";
  30                         enable-method = "qcom,gcc-msm8660";
  31                         device_type = "cpu";
  32                         reg = <1>;
  33                         next-level-cache = <&L2>;
  34                 };
  35
  36                 L2: l2-cache {
  37                         compatible = "cache";
  38                         cache-level = <2>;
  39                 };
  40         };
  41
  42         memory {
  43                 device_type = "memory";
  44                 reg = <0x0 0x0>;
  45         };
  46
  47         cpu-pmu {
  48                 compatible = "qcom,scorpion-mp-pmu";
  49                 interrupts = <1 9 0x304>;
  50         };
  51
  52         clocks {
  53                 cxo_board: cxo-board-clk {
  54                         compatible = "fixed-clock";
  55                         #clock-cells = <0>;
  56                         clock-frequency = <19200000>;
  57                         clock-output-names = "cxo_board";
  58                 };
  59
  60                 pxo_board: pxo-board-clk {
  61                         compatible = "fixed-clock";
  62                         #clock-cells = <0>;
  63                         clock-frequency = <27000000>;
  64                         clock-output-names = "pxo_board";
  65                 };
  66
  67                 sleep-clk {
  68                         compatible = "fixed-clock";
  69                         #clock-cells = <0>;
  70                         clock-frequency = <32768>;
  71                         clock-output-names = "sleep_clk";
  72                 };
  73         };
  74
  75         /*
  76          * These channels from the ADC are simply hardware monitors.
  77          * That is why the ADC is referred to as "HKADC" - HouseKeeping
  78          * ADC.
  79          */
  80         iio-hwmon {
  81                 compatible = "iio-hwmon";
  82                 io-channels = <&xoadc 0x00 0x01>, /* Battery */
  83                             <&xoadc 0x00 0x02>, /* DC in (charger) */
  84                             <&xoadc 0x00 0x04>, /* VPH the main system voltage */
  85                             <&xoadc 0x00 0x0b>, /* Die temperature */
  86                             <&xoadc 0x00 0x0c>, /* Reference voltage 1.25V */
  87                             <&xoadc 0x00 0x0d>, /* Reference voltage 0.625V */
  88                             <&xoadc 0x00 0x0e>; /* Reference voltage 0.325V */
  89         };
  90
  91         soc: soc {
  92                 #address-cells = <1>;
  93                 #size-cells = <1>;
  94                 ranges;
  95                 compatible = "simple-bus";
  96
  97                 intc: interrupt-controller@2080000 {
  98                         compatible = "qcom,msm-8660-qgic";
  99                         interrupt-controller;
 100                         #interrupt-cells = <3>;
 101                         reg = < 0x02080000 0x1000 >,
 102                               < 0x02081000 0x1000 >;
 103                 };
 104
 105                 timer@2000000 {
 106                         compatible = "qcom,scss-timer", "qcom,msm-timer";
 107                         interrupts = <1 0 0x301>,
 108                                      <1 1 0x301>,
 109                                      <1 2 0x301>;
 110                         reg = <0x02000000 0x100>;
 111                         clock-frequency = <27000000>,
 112                                           <32768>;
 113                         cpu-offset = <0x40000>;
 114                 };
 115
 116                 tlmm: pinctrl@800000 {
 117                         compatible = "qcom,msm8660-pinctrl";
 118                         reg = <0x800000 0x4000>;
 119
 120                         gpio-controller;
 121                         gpio-ranges = <&tlmm 0 0 173>;
 122                         #gpio-cells = <2>;
 123                         interrupts = <0 16 0x4>;
 124                         interrupt-controller;
 125                         #interrupt-cells = <2>;
 126
 127                 };
 128
 129                 gcc: clock-controller@900000 {
 130                         compatible = "qcom,gcc-msm8660";
 131                         #clock-cells = <1>;
 132                         #power-domain-cells = <1>;
 133                         #reset-cells = <1>;
 134                         reg = <0x900000 0x4000>;
 135                         clocks = <&pxo_board>, <&cxo_board>;
 136                         clock-names = "pxo", "cxo";
 137                 };
 138
 139                 gsbi1: gsbi@16000000 {
 140                         compatible = "qcom,gsbi-v1.0.0";
 141                         cell-index = <12>;
 142                         reg = <0x16000000 0x100>;
 143                         clocks = <&gcc GSBI1_H_CLK>;
 144                         clock-names = "iface";
 145                         #address-cells = <1>;
 146                         #size-cells = <1>;
 147                         ranges;
 148
 149                         syscon-tcsr = <&tcsr>;
 150
 151                         status = "disabled";
 152
 153                         gsbi1_spi: spi@16080000 {
 154                                 compatible = "qcom,spi-qup-v1.1.1";
 155                                 reg = <0x16080000 0x1000>;
 156                                 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
 157                                 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
 158                                 clock-names = "core", "iface";
 159                                 #address-cells = <1>;
 160                                 #size-cells = <0>;
 161                                 status = "disabled";
 162                         };
 163                 };
 164
 165                 gsbi3: gsbi@16200000 {
 166                         compatible = "qcom,gsbi-v1.0.0";
 167                         cell-index = <12>;
 168                         reg = <0x16200000 0x100>;
 169                         clocks = <&gcc GSBI3_H_CLK>;
 170                         clock-names = "iface";
 171                         #address-cells = <1>;
 172                         #size-cells = <1>;
 173                         ranges;
 174
 175                         syscon-tcsr = <&tcsr>;
 176                         status = "disabled";
 177
 178                         gsbi3_i2c: i2c@16280000 {
 179                                 compatible = "qcom,i2c-qup-v1.1.1";
 180                                 reg = <0x16280000 0x1000>;
 181                                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
 182                                 clocks = <&gcc GSBI3_QUP_CLK>, <&gcc GSBI3_H_CLK>;
 183                                 clock-names = "core", "iface";
 184                                 #address-cells = <1>;
 185                                 #size-cells = <0>;
 186                                 status = "disabled";
 187                         };
 188                 };
 189
 190                 gsbi6: gsbi@16500000 {
 191                         compatible = "qcom,gsbi-v1.0.0";
 192                         cell-index = <12>;
 193                         reg = <0x16500000 0x100>;
 194                         clocks = <&gcc GSBI6_H_CLK>;
 195                         clock-names = "iface";
 196                         #address-cells = <1>;
 197                         #size-cells = <1>;
 198                         ranges;
 199                         status = "disabled";
 200
 201                         syscon-tcsr = <&tcsr>;
 202
 203                         gsbi6_serial: serial@16540000 {
 204                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 205                                 reg = <0x16540000 0x1000>,
 206                                       <0x16500000 0x1000>;
 207                                 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
 208                                 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
 209                                 clock-names = "core", "iface";
 210                                 status = "disabled";
 211                         };
 212
 213                         gsbi6_i2c: i2c@16580000 {
 214                                 compatible = "qcom,i2c-qup-v1.1.1";
 215                                 reg = <0x16580000 0x1000>;
 216                                 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
 217                                 clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
 218                                 clock-names = "core", "iface";
 219                                 #address-cells = <1>;
 220                                 #size-cells = <0>;
 221                                 status = "disabled";
 222                         };
 223                 };
 224
 225                 gsbi7: gsbi@16600000 {
 226                         compatible = "qcom,gsbi-v1.0.0";
 227                         cell-index = <12>;
 228                         reg = <0x16600000 0x100>;
 229                         clocks = <&gcc GSBI7_H_CLK>;
 230                         clock-names = "iface";
 231                         #address-cells = <1>;
 232                         #size-cells = <1>;
 233                         ranges;
 234                         status = "disabled";
 235
 236                         syscon-tcsr = <&tcsr>;
 237
 238                         gsbi7_serial: serial@16640000 {
 239                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 240                                 reg = <0x16640000 0x1000>,
 241                                       <0x16600000 0x1000>;
 242                                 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
 243                                 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
 244                                 clock-names = "core", "iface";
 245                                 status = "disabled";
 246                         };
 247
 248                         gsbi7_i2c: i2c@16680000 {
 249                                 compatible = "qcom,i2c-qup-v1.1.1";
 250                                 reg = <0x16680000 0x1000>;
 251                                 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
 252                                 clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>;
 253                                 clock-names = "core", "iface";
 254                                 #address-cells = <1>;
 255                                 #size-cells = <0>;
 256                                 status = "disabled";
 257                         };
 258                 };
 259
 260                 gsbi8: gsbi@19800000 {
 261                         compatible = "qcom,gsbi-v1.0.0";
 262                         cell-index = <12>;
 263                         reg = <0x19800000 0x100>;
 264                         clocks = <&gcc GSBI8_H_CLK>;
 265                         clock-names = "iface";
 266                         #address-cells = <1>;
 267                         #size-cells = <1>;
 268                         ranges;
 269
 270                         syscon-tcsr = <&tcsr>;
 271                         status = "disabled";
 272
 273                         gsbi8_i2c: i2c@19880000 {
 274                                 compatible = "qcom,i2c-qup-v1.1.1";
 275                                 reg = <0x19880000 0x1000>;
 276                                 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
 277                                 clocks = <&gcc GSBI8_QUP_CLK>, <&gcc GSBI8_H_CLK>;
 278                                 clock-names = "core", "iface";
 279                                 #address-cells = <1>;
 280                                 #size-cells = <0>;
 281                                 status = "disabled";
 282                         };
 283                 };
 284
 285                 gsbi12: gsbi@19c00000 {
 286                         compatible = "qcom,gsbi-v1.0.0";
 287                         cell-index = <12>;
 288                         reg = <0x19c00000 0x100>;
 289                         clocks = <&gcc GSBI12_H_CLK>;
 290                         clock-names = "iface";
 291                         #address-cells = <1>;
 292                         #size-cells = <1>;
 293                         ranges;
 294
 295                         syscon-tcsr = <&tcsr>;
 296
 297                         gsbi12_serial: serial@19c40000 {
 298                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 299                                 reg = <0x19c40000 0x1000>,
 300                                       <0x19c00000 0x1000>;
 301                                 interrupts = <0 195 IRQ_TYPE_LEVEL_HIGH>;
 302                                 clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
 303                                 clock-names = "core", "iface";
 304                                 status = "disabled";
 305                         };
 306
 307                         gsbi12_i2c: i2c@19c80000 {
 308                                 compatible = "qcom,i2c-qup-v1.1.1";
 309                                 reg = <0x19c80000 0x1000>;
 310                                 interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>;
 311                                 clocks = <&gcc GSBI12_QUP_CLK>, <&gcc GSBI12_H_CLK>;
 312                                 clock-names = "core", "iface";
 313                                 #address-cells = <1>;
 314                                 #size-cells = <0>;
 315                                 status = "disabled";
 316                         };
 317                 };
 318
 319                 external-bus@1a100000 {
 320                         compatible = "qcom,msm8660-ebi2";
 321                         #address-cells = <2>;
 322                         #size-cells = <1>;
 323                         ranges = <0 0x0 0x1a800000 0x00800000>,
 324                                  <1 0x0 0x1b000000 0x00800000>,
 325                                  <2 0x0 0x1b800000 0x00800000>,
 326                                  <3 0x0 0x1d000000 0x08000000>,
 327                                  <4 0x0 0x1c800000 0x00800000>,
 328                                  <5 0x0 0x1c000000 0x00800000>;
 329                         reg = <0x1a100000 0x1000>, <0x1a110000 0x1000>;
 330                         reg-names = "ebi2", "xmem";
 331                         clocks = <&gcc EBI2_2X_CLK>, <&gcc EBI2_CLK>;
 332                         clock-names = "ebi2x", "ebi2";
 333                         status = "disabled";
 334                 };
 335
 336                 qcom,ssbi@500000 {
 337                         compatible = "qcom,ssbi";
 338                         reg = <0x500000 0x1000>;
 339                         qcom,controller-type = "pmic-arbiter";
 340
 341                         pm8058: pmic@0 {
 342                                 compatible = "qcom,pm8058";
 343                                 interrupt-parent = <&tlmm>;
 344                                 interrupts = <88 8>;
 345                                 #interrupt-cells = <2>;
 346                                 interrupt-controller;
 347                                 #address-cells = <1>;
 348                                 #size-cells = <0>;
 349
 350                                 pm8058_gpio: gpio@150 {
 351                                         compatible = "qcom,pm8058-gpio",
 352                                                      "qcom,ssbi-gpio";
 353                                         reg = <0x150>;
 354                                         interrupt-controller;
 355                                         #interrupt-cells = <2>;
 356                                         gpio-controller;
 357                                         gpio-ranges = <&pm8058_gpio 0 0 44>;
 358                                         #gpio-cells = <2>;
 359
 360                                 };
 361
 362                                 pm8058_mpps: mpps@50 {
 363                                         compatible = "qcom,pm8058-mpp",
 364                                                      "qcom,ssbi-mpp";
 365                                         reg = <0x50>;
 366                                         gpio-controller;
 367                                         #gpio-cells = <2>;
 368                                         gpio-ranges = <&pm8058_mpps 0 0 12>;
 369                                         interrupt-controller;
 370                                         #interrupt-cells = <2>;
 371                                 };
 372
 373                                 pwrkey@1c {
 374                                         compatible = "qcom,pm8058-pwrkey";
 375                                         reg = <0x1c>;
 376                                         interrupt-parent = <&pm8058>;
 377                                         interrupts = <50 1>, <51 1>;
 378                                         debounce = <15625>;
 379                                         pull-up;
 380                                 };
 381
 382                                 keypad@148 {
 383                                         compatible = "qcom,pm8058-keypad";
 384                                         reg = <0x148>;
 385                                         interrupt-parent = <&pm8058>;
 386                                         interrupts = <74 1>, <75 1>;
 387                                         debounce = <15>;
 388                                         scan-delay = <32>;
 389                                         row-hold = <91500>;
 390                                 };
 391
 392                                 xoadc: xoadc@197 {
 393                                         compatible = "qcom,pm8058-adc";
 394                                         reg = <0x197>;
 395                                         interrupts-extended = <&pm8058 76 IRQ_TYPE_EDGE_RISING>;
 396                                         #address-cells = <2>;
 397                                         #size-cells = <0>;
 398                                         #io-channel-cells = <2>;
 399
 400                                         vcoin: adc-channel@0 {
 401                                                 reg = <0x00 0x00>;
 402                                         };
 403                                         vbat: adc-channel@1 {
 404                                                 reg = <0x00 0x01>;
 405                                         };
 406                                         dcin: adc-channel@2 {
 407                                                 reg = <0x00 0x02>;
 408                                         };
 409                                         ichg: adc-channel@3 {
 410                                                 reg = <0x00 0x03>;
 411                                         };
 412                                         vph_pwr: adc-channel@4 {
 413                                                 reg = <0x00 0x04>;
 414                                         };
 415                                         usb_vbus: adc-channel@a {
 416                                                 reg = <0x00 0x0a>;
 417                                         };
 418                                         die_temp: adc-channel@b {
 419                                                 reg = <0x00 0x0b>;
 420                                         };
 421                                         ref_625mv: adc-channel@c {
 422                                                 reg = <0x00 0x0c>;
 423                                         };
 424                                         ref_1250mv: adc-channel@d {
 425                                                 reg = <0x00 0x0d>;
 426                                         };
 427                                         ref_325mv: adc-channel@e {
 428                                                 reg = <0x00 0x0e>;
 429                                         };
 430                                         ref_muxoff: adc-channel@f {
 431                                                 reg = <0x00 0x0f>;
 432                                         };
 433                                 };
 434
 435                                 rtc@1e8 {
 436                                         compatible = "qcom,pm8058-rtc";
 437                                         reg = <0x1e8>;
 438                                         interrupt-parent = <&pm8058>;
 439                                         interrupts = <39 1>;
 440                                         allow-set-time;
 441                                 };
 442
 443                                 vibrator@4a {
 444                                         compatible = "qcom,pm8058-vib";
 445                                         reg = <0x4a>;
 446                                 };
 447                         };
 448                 };
 449
 450                 l2cc: clock-controller@2082000 {
 451                         compatible = "qcom,kpss-gcc", "syscon";
 452                         reg = <0x02082000 0x1000>;
 453                 };
 454
 455                 rpm: rpm@104000 {
 456                         compatible = "qcom,rpm-msm8660";
 457                         reg = <0x00104000 0x1000>;
 458                         qcom,ipc = <&l2cc 0x8 2>;
 459
 460                         interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
 461                                      <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
 462                                      <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
 463                         interrupt-names = "ack", "err", "wakeup";
 464                         clocks = <&gcc RPM_MSG_RAM_H_CLK>;
 465                         clock-names = "ram";
 466
 467                         rpmcc: clock-controller {
 468                                 compatible = "qcom,rpmcc-msm8660", "qcom,rpmcc";
 469                                 #clock-cells = <1>;
 470                                 clocks = <&pxo_board>;
 471                                 clock-names = "pxo";
 472                         };
 473
 474                         pm8901-regulators {
 475                                 compatible = "qcom,rpm-pm8901-regulators";
 476
 477                                 pm8901_l0: l0 {};
 478                                 pm8901_l1: l1 {};
 479                                 pm8901_l2: l2 {};
 480                                 pm8901_l3: l3 {};
 481                                 pm8901_l4: l4 {};
 482                                 pm8901_l5: l5 {};
 483                                 pm8901_l6: l6 {};
 484
 485                                 /* S0 and S1 Handled as SAW regulators by SPM */
 486                                 pm8901_s2: s2 {};
 487                                 pm8901_s3: s3 {};
 488                                 pm8901_s4: s4 {};
 489
 490                                 pm8901_lvs0: lvs0 {};
 491                                 pm8901_lvs1: lvs1 {};
 492                                 pm8901_lvs2: lvs2 {};
 493                                 pm8901_lvs3: lvs3 {};
 494
 495                                 pm8901_mvs: mvs {};
 496                         };
 497
 498                         pm8058-regulators {
 499                                 compatible = "qcom,rpm-pm8058-regulators";
 500
 501                                 pm8058_l0: l0 {};
 502                                 pm8058_l1: l1 {};
 503                                 pm8058_l2: l2 {};
 504                                 pm8058_l3: l3 {};
 505                                 pm8058_l4: l4 {};
 506                                 pm8058_l5: l5 {};
 507                                 pm8058_l6: l6 {};
 508                                 pm8058_l7: l7 {};
 509                                 pm8058_l8: l8 {};
 510                                 pm8058_l9: l9 {};
 511                                 pm8058_l10: l10 {};
 512                                 pm8058_l11: l11 {};
 513                                 pm8058_l12: l12 {};
 514                                 pm8058_l13: l13 {};
 515                                 pm8058_l14: l14 {};
 516                                 pm8058_l15: l15 {};
 517                                 pm8058_l16: l16 {};
 518                                 pm8058_l17: l17 {};
 519                                 pm8058_l18: l18 {};
 520                                 pm8058_l19: l19 {};
 521                                 pm8058_l20: l20 {};
 522                                 pm8058_l21: l21 {};
 523                                 pm8058_l22: l22 {};
 524                                 pm8058_l23: l23 {};
 525                                 pm8058_l24: l24 {};
 526                                 pm8058_l25: l25 {};
 527
 528                                 pm8058_s0: s0 {};
 529                                 pm8058_s1: s1 {};
 530                                 pm8058_s2: s2 {};
 531                                 pm8058_s3: s3 {};
 532                                 pm8058_s4: s4 {};
 533
 534                                 pm8058_lvs0: lvs0 {};
 535                                 pm8058_lvs1: lvs1 {};
 536
 537                                 pm8058_ncp: ncp {};
 538                         };
 539                 };
 540
 541                 amba {
 542                         compatible = "simple-bus";
 543                         #address-cells = <1>;
 544                         #size-cells = <1>;
 545                         ranges;
 546                         sdcc1: mmc@12400000 {
 547                                 status = "disabled";
 548                                 compatible = "arm,pl18x", "arm,primecell";
 549                                 arm,primecell-periphid = <0x00051180>;
 550                                 reg = <0x12400000 0x8000>;
 551                                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 552                                 interrupt-names = "cmd_irq";
 553                                 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
 554                                 clock-names = "mclk", "apb_pclk";
 555                                 bus-width = <8>;
 556                                 max-frequency = <48000000>;
 557                                 non-removable;
 558                                 cap-sd-highspeed;
 559                                 cap-mmc-highspeed;
 560                         };
 561
 562                         sdcc2: mmc@12140000 {
 563                                 status = "disabled";
 564                                 compatible = "arm,pl18x", "arm,primecell";
 565                                 arm,primecell-periphid = <0x00051180>;
 566                                 reg = <0x12140000 0x8000>;
 567                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 568                                 interrupt-names = "cmd_irq";
 569                                 clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>;
 570                                 clock-names = "mclk", "apb_pclk";
 571                                 bus-width = <8>;
 572                                 max-frequency = <48000000>;
 573                                 cap-sd-highspeed;
 574                                 cap-mmc-highspeed;
 575                         };
 576
 577                         sdcc3: mmc@12180000 {
 578                                 compatible = "arm,pl18x", "arm,primecell";
 579                                 arm,primecell-periphid = <0x00051180>;
 580                                 status = "disabled";
 581                                 reg = <0x12180000 0x8000>;
 582                                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 583                                 interrupt-names = "cmd_irq";
 584                                 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
 585                                 clock-names = "mclk", "apb_pclk";
 586                                 bus-width = <4>;
 587                                 cap-sd-highspeed;
 588                                 cap-mmc-highspeed;
 589                                 max-frequency = <48000000>;
 590                                 no-1-8-v;
 591                         };
 592
 593                         sdcc4: mmc@121c0000 {
 594                                 compatible = "arm,pl18x", "arm,primecell";
 595                                 arm,primecell-periphid = <0x00051180>;
 596                                 status = "disabled";
 597                                 reg = <0x121c0000 0x8000>;
 598                                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 599                                 interrupt-names = "cmd_irq";
 600                                 clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
 601                                 clock-names = "mclk", "apb_pclk";
 602                                 bus-width = <4>;
 603                                 max-frequency = <48000000>;
 604                                 cap-sd-highspeed;
 605                                 cap-mmc-highspeed;
 606                         };
 607
 608                         sdcc5: mmc@12200000 {
 609                                 compatible = "arm,pl18x", "arm,primecell";
 610                                 arm,primecell-periphid = <0x00051180>;
 611                                 status = "disabled";
 612                                 reg = <0x12200000 0x8000>;
 613                                 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
 614                                 interrupt-names = "cmd_irq";
 615                                 clocks = <&gcc SDC5_CLK>, <&gcc SDC5_H_CLK>;
 616                                 clock-names = "mclk", "apb_pclk";
 617                                 bus-width = <4>;
 618                                 cap-sd-highspeed;
 619                                 cap-mmc-highspeed;
 620                                 max-frequency = <48000000>;
 621                         };
 622                 };
 623
 624                 tcsr: syscon@1a400000 {
 625                         compatible = "qcom,tcsr-msm8660", "syscon";
 626                         reg = <0x1a400000 0x100>;
 627                 };
 628         };
 629
 630 };