3 /include/ "skeleton.dtsi"
5 #include <dt-bindings/interrupt-controller/irq.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-msm8660.h>
8 #include <dt-bindings/soc/qcom,gsbi.h>
11 model = "Qualcomm MSM8660";
12 compatible = "qcom,msm8660";
13 interrupt-parent = <&intc>;
20 compatible = "qcom,scorpion";
21 enable-method = "qcom,gcc-msm8660";
24 next-level-cache = <&L2>;
28 compatible = "qcom,scorpion";
29 enable-method = "qcom,gcc-msm8660";
32 next-level-cache = <&L2>;
42 compatible = "qcom,scorpion-mp-pmu";
43 interrupts = <1 9 0x304>;
48 compatible = "fixed-clock";
50 clock-frequency = <19200000>;
54 compatible = "fixed-clock";
56 clock-frequency = <27000000>;
60 compatible = "fixed-clock";
62 clock-frequency = <32768>;
70 compatible = "simple-bus";
72 intc: interrupt-controller@2080000 {
73 compatible = "qcom,msm-8660-qgic";
75 #interrupt-cells = <3>;
76 reg = < 0x02080000 0x1000 >,
77 < 0x02081000 0x1000 >;
81 compatible = "qcom,scss-timer", "qcom,msm-timer";
82 interrupts = <1 0 0x301>,
85 reg = <0x02000000 0x100>;
86 clock-frequency = <27000000>,
88 cpu-offset = <0x40000>;
91 tlmm: pinctrl@800000 {
92 compatible = "qcom,msm8660-pinctrl";
93 reg = <0x800000 0x4000>;
97 interrupts = <0 16 0x4>;
99 #interrupt-cells = <2>;
103 gcc: clock-controller@900000 {
104 compatible = "qcom,gcc-msm8660";
107 reg = <0x900000 0x4000>;
110 gsbi12: gsbi@19c00000 {
111 compatible = "qcom,gsbi-v1.0.0";
113 reg = <0x19c00000 0x100>;
114 clocks = <&gcc GSBI12_H_CLK>;
115 clock-names = "iface";
116 #address-cells = <1>;
120 syscon-tcsr = <&tcsr>;
122 gsbi12_serial: serial@19c40000 {
123 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
124 reg = <0x19c40000 0x1000>,
126 interrupts = <0 195 IRQ_TYPE_NONE>;
127 clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
128 clock-names = "core", "iface";
132 gsbi12_i2c: i2c@19c80000 {
133 compatible = "qcom,i2c-qup-v1.1.1";
134 reg = <0x19c80000 0x1000>;
135 interrupts = <0 196 IRQ_TYPE_NONE>;
136 clocks = <&gcc GSBI12_QUP_CLK>, <&gcc GSBI12_H_CLK>;
137 clock-names = "core", "iface";
138 #address-cells = <1>;
145 compatible = "qcom,ssbi";
146 reg = <0x500000 0x1000>;
147 qcom,controller-type = "pmic-arbiter";
150 compatible = "qcom,pm8058";
151 interrupt-parent = <&tlmm>;
153 #interrupt-cells = <2>;
154 interrupt-controller;
155 #address-cells = <1>;
158 pm8058_gpio: gpio@150 {
159 compatible = "qcom,pm8058-gpio",
162 interrupt-parent = <&pmicintc>;
163 interrupts = <192 IRQ_TYPE_NONE>,
212 pm8058_mpps: mpps@50 {
213 compatible = "qcom,pm8058-mpp",
218 interrupt-parent = <&pmicintc>;
235 compatible = "qcom,pm8058-pwrkey";
237 interrupt-parent = <&pmicintc>;
238 interrupts = <50 1>, <51 1>;
244 compatible = "qcom,pm8058-keypad";
246 interrupt-parent = <&pmicintc>;
247 interrupts = <74 1>, <75 1>;
254 compatible = "qcom,pm8058-rtc";
256 interrupt-parent = <&pmicintc>;
262 compatible = "qcom,pm8058-vib";
268 l2cc: clock-controller@2082000 {
269 compatible = "syscon";
270 reg = <0x02082000 0x1000>;
274 compatible = "qcom,rpm-msm8660";
275 reg = <0x00104000 0x1000>;
276 qcom,ipc = <&l2cc 0x8 2>;
278 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
279 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
280 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
281 interrupt-names = "ack", "err", "wakeup";
282 clocks = <&gcc RPM_MSG_RAM_H_CLK>;
285 rpmcc: clock-controller {
286 compatible = "qcom,rpmcc-apq8660", "qcom,rpmcc";
291 compatible = "qcom,rpm-pm8901-regulators";
301 /* S0 and S1 Handled as SAW regulators by SPM */
306 pm8901_lvs0: lvs0 {};
307 pm8901_lvs1: lvs1 {};
308 pm8901_lvs2: lvs2 {};
309 pm8901_lvs3: lvs3 {};
315 compatible = "qcom,rpm-pm8058-regulators";
350 pm8058_lvs0: lvs0 {};
351 pm8058_lvs1: lvs1 {};
358 compatible = "simple-bus";
359 #address-cells = <1>;
362 sdcc1: sdcc@12400000 {
364 compatible = "arm,pl18x", "arm,primecell";
365 arm,primecell-periphid = <0x00051180>;
366 reg = <0x12400000 0x8000>;
367 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
368 interrupt-names = "cmd_irq";
369 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
370 clock-names = "mclk", "apb_pclk";
372 max-frequency = <48000000>;
378 sdcc3: sdcc@12180000 {
379 compatible = "arm,pl18x", "arm,primecell";
380 arm,primecell-periphid = <0x00051180>;
382 reg = <0x12180000 0x8000>;
383 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
384 interrupt-names = "cmd_irq";
385 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
386 clock-names = "mclk", "apb_pclk";
390 max-frequency = <48000000>;
394 sdcc5: sdcc@12200000 {
395 compatible = "arm,pl18x", "arm,primecell";
396 arm,primecell-periphid = <0x00051180>;
398 reg = <0x12200000 0x8000>;
399 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
400 interrupt-names = "cmd_irq";
401 clocks = <&gcc SDC5_CLK>, <&gcc SDC5_H_CLK>;
402 clock-names = "mclk", "apb_pclk";
406 max-frequency = <48000000>;
410 tcsr: syscon@1a400000 {
411 compatible = "qcom,tcsr-msm8660", "syscon";
412 reg = <0x1a400000 0x100>;